1 #ifndef __CONFIG_H 2 #define __CONFIG_H 3 4 #undef DEBUG 5 6 #define CONFIG_SH 1 7 #define CONFIG_SH4 1 8 #define CONFIG_CPU_SH7751 1 9 #define CONFIG_CPU_SH_TYPE_R 1 10 #define CONFIG_R2DPLUS 1 11 #define __LITTLE_ENDIAN__ 1 12 13 /* 14 * Command line configuration. 15 */ 16 #include <config_cmd_default.h> 17 18 #define CONFIG_CMD_DFL 19 #define CONFIG_CMD_CACHE 20 #define CONFIG_CMD_FLASH 21 #define CONFIG_CMD_PCI 22 #define CONFIG_CMD_NET 23 #define CONFIG_CMD_PING 24 #define CONFIG_CMD_IDE 25 #define CONFIG_CMD_EXT2 26 #define CONFIG_DOS_PARTITION 27 #define CONFIG_CMD_SH_ZIMAGEBOOT 28 29 /* SCIF */ 30 #define CONFIG_SCIF_CONSOLE 1 31 #define CONFIG_BAUDRATE 115200 32 #define CONFIG_CONS_SCIF1 1 33 #define CONFIG_BOARD_LATE_INIT 34 35 #define CONFIG_BOOTDELAY -1 36 #define CONFIG_BOOTARGS "console=ttySC0,115200" 37 #define CONFIG_ENV_OVERWRITE 1 38 39 /* SDRAM */ 40 #define CONFIG_SYS_SDRAM_BASE (0x8C000000) 41 #define CONFIG_SYS_SDRAM_SIZE (0x04000000) 42 43 #define CONFIG_SYS_TEXT_BASE 0x0FFC0000 44 #define CONFIG_SYS_LONGHELP 45 #define CONFIG_SYS_PROMPT "=> " 46 #define CONFIG_SYS_CBSIZE 256 47 #define CONFIG_SYS_PBSIZE 256 48 #define CONFIG_SYS_MAXARGS 16 49 #define CONFIG_SYS_BARGSIZE 512 50 /* List of legal baudrate settings for this board */ 51 #define CONFIG_SYS_BAUDRATE_TABLE { 115200, 57600, 38400, 19200, 9600 } 52 53 #define CONFIG_SYS_MEMTEST_START (CONFIG_SYS_SDRAM_BASE) 54 #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_TEXT_BASE - 0x100000) 55 56 #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 32 * 1024 * 1024) 57 /* Address of u-boot image in Flash */ 58 #define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE) 59 #define CONFIG_SYS_MONITOR_LEN (256 * 1024) 60 /* Size of DRAM reserved for malloc() use */ 61 #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) 62 #define CONFIG_SYS_BOOTMAPSZ (8 * 1024 * 1024) 63 64 /* 65 * NOR Flash ( Spantion S29GL256P ) 66 */ 67 #define CONFIG_SYS_FLASH_CFI 68 #define CONFIG_FLASH_CFI_DRIVER 69 #define CONFIG_SYS_FLASH_BASE (0xA0000000) 70 #define CONFIG_SYS_MAX_FLASH_BANKS (1) 71 #define CONFIG_SYS_MAX_FLASH_SECT 256 72 #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE } 73 74 #define CONFIG_ENV_IS_IN_FLASH 75 #define CONFIG_ENV_SECT_SIZE 0x40000 76 #define CONFIG_ENV_SIZE (CONFIG_ENV_SECT_SIZE) 77 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN) 78 79 /* 80 * SuperH Clock setting 81 */ 82 #define CONFIG_SYS_CLK_FREQ 60000000 83 #define CONFIG_SYS_TMU_CLK_DIV 4 84 #define CONFIG_SYS_HZ 1000 85 #define CONFIG_SYS_PLL_SETTLING_TIME 100/* in us */ 86 87 /* 88 * IDE support 89 */ 90 #define CONFIG_IDE_RESET 1 91 #define CONFIG_SYS_PIO_MODE 1 92 #define CONFIG_SYS_IDE_MAXBUS 1 /* IDE bus */ 93 #define CONFIG_SYS_IDE_MAXDEVICE 1 94 #define CONFIG_SYS_ATA_BASE_ADDR 0xb4000000 95 #define CONFIG_SYS_ATA_STRIDE 2 /* 1bit shift */ 96 #define CONFIG_SYS_ATA_DATA_OFFSET 0x1000 /* data reg offset */ 97 #define CONFIG_SYS_ATA_REG_OFFSET 0x1000 /* reg offset */ 98 #define CONFIG_SYS_ATA_ALT_OFFSET 0x800 /* alternate register offset */ 99 #define CONFIG_IDE_SWAP_IO 100 101 /* 102 * SuperH PCI Bridge Configration 103 */ 104 #define CONFIG_PCI 105 #define CONFIG_SH4_PCI 106 #define CONFIG_SH7751_PCI 107 #define CONFIG_PCI_PNP 108 #define CONFIG_PCI_SCAN_SHOW 1 109 #define __io 110 #define __mem_pci 111 112 #define CONFIG_PCI_MEM_BUS 0xFD000000 /* Memory space base addr */ 113 #define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS 114 #define CONFIG_PCI_MEM_SIZE 0x01000000 /* Size of Memory window */ 115 #define CONFIG_PCI_IO_BUS 0xFE240000 /* IO space base address */ 116 #define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS 117 #define CONFIG_PCI_IO_SIZE 0x00040000 /* Size of IO window */ 118 #define CONFIG_PCI_SYS_BUS (CONFIG_SYS_SDRAM_BASE & 0x1fffffff) 119 #define CONFIG_PCI_SYS_PHYS (CONFIG_SYS_SDRAM_BASE & 0x1fffffff) 120 #define CONFIG_PCI_SYS_SIZE CONFIG_SYS_SDRAM_SIZE 121 122 /* 123 * Network device (RTL8139) support 124 */ 125 #define CONFIG_RTL8139 126 127 #endif /* __CONFIG_H */ 128