1 /* 2 * Configuation settings for the Renesas Solutions r0p7734 board 3 * 4 * Copyright (C) 2010, 2011 Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com> 5 * 6 * SPDX-License-Identifier: GPL-2.0+ 7 */ 8 9 #ifndef __R0P7734_H 10 #define __R0P7734_H 11 12 #undef DEBUG 13 #define CONFIG_SH 1 14 #define CONFIG_SH4 1 15 #define CONFIG_SH4A 1 16 #define CONFIG_CPU_SH7734 1 17 #define CONFIG_R0P7734 1 18 #define CONFIG_400MHZ_MODE 1 19 /* #define CONFIG_533MHZ_MODE 1 */ 20 21 #define CONFIG_BOARD_LATE_INIT 22 #define CONFIG_SYS_TEXT_BASE 0x8FFC0000 23 24 #define CONFIG_CMD_FLASH 25 #define CONFIG_CMD_MEMORY 26 #define CONFIG_CMD_NET 27 #define CONFIG_CMD_PING 28 #define CONFIG_CMD_MII 29 #define CONFIG_CMD_NFS 30 #define CONFIG_CMD_SDRAM 31 #define CONFIG_CMD_ENV 32 #define CONFIG_CMD_SAVEENV 33 34 #define CONFIG_BAUDRATE 115200 35 #define CONFIG_BOOTDELAY 3 36 #define CONFIG_BOOTARGS "console=ttySC3,115200" 37 38 #define CONFIG_VERSION_VARIABLE 39 #undef CONFIG_SHOW_BOOT_PROGRESS 40 41 /* Ether */ 42 #define CONFIG_SH_ETHER 1 43 #define CONFIG_SH_ETHER_USE_PORT (0) 44 #define CONFIG_SH_ETHER_PHY_ADDR (0x0) 45 #define CONFIG_PHYLIB 46 #define CONFIG_PHY_SMSC 1 47 #define CONFIG_BITBANGMII 48 #define CONFIG_BITBANGMII_MULTI 49 #define CONFIG_SH_ETHER_SH7734_MII (0x00) /* MII */ 50 #define CONFIG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_MII 51 #ifndef CONFIG_SH_ETHER 52 # define CONFIG_SMC911X 53 # define CONFIG_SMC911X_16_BIT 54 # define CONFIG_SMC911X_BASE (0x84000000) 55 #endif 56 57 58 /* I2C */ 59 #define CONFIG_CMD_I2C 60 #define CONFIG_SH_SH7734_I2C 1 61 #define CONFIG_HARD_I2C 1 62 #define CONFIG_I2C_MULTI_BUS 1 63 #define CONFIG_SYS_MAX_I2C_BUS 2 64 #define CONFIG_SYS_I2C_MODULE 0 65 #define CONFIG_SYS_I2C_SPEED 100000 /* 100 kHz */ 66 #define CONFIG_SYS_I2C_SLAVE 0x50 67 #define CONFIG_SH_I2C_DATA_HIGH 4 68 #define CONFIG_SH_I2C_DATA_LOW 5 69 #define CONFIG_SH_I2C_CLOCK 500000000 70 #define CONFIG_SH_I2C_BASE0 0xFFC70000 71 #define CONFIG_SH_I2C_BASE1 0xFFC7100 72 73 /* undef to save memory */ 74 #define CONFIG_SYS_LONGHELP 75 /* Monitor Command Prompt */ 76 /* Buffer size for input from the Console */ 77 #define CONFIG_SYS_CBSIZE 256 78 /* Buffer size for Console output */ 79 #define CONFIG_SYS_PBSIZE 256 80 /* max args accepted for monitor commands */ 81 #define CONFIG_SYS_MAXARGS 16 82 /* Buffer size for Boot Arguments passed to kernel */ 83 #define CONFIG_SYS_BARGSIZE 512 84 /* List of legal baudrate settings for this board */ 85 #define CONFIG_SYS_BAUDRATE_TABLE { 115200 } 86 87 /* SCIF */ 88 #define CONFIG_SCIF_CONSOLE 1 89 #define CONFIG_SCIF 1 90 #define CONFIG_CONS_SCIF3 1 91 92 /* Suppress display of console information at boot */ 93 #undef CONFIG_SYS_CONSOLE_INFO_QUIET 94 #undef CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE 95 #undef CONFIG_SYS_CONSOLE_ENV_OVERWRITE 96 97 /* SDRAM */ 98 #define CONFIG_SYS_SDRAM_BASE (0x88000000) 99 #define CONFIG_SYS_SDRAM_SIZE (128 * 1024 * 1024) 100 #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 16 * 1024 * 1024) 101 102 #define CONFIG_SYS_MEMTEST_START (CONFIG_SYS_SDRAM_BASE) 103 #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + 100 * 1024 * 1024) 104 /* Enable alternate, more extensive, memory test */ 105 #undef CONFIG_SYS_ALT_MEMTEST 106 /* Scratch address used by the alternate memory test */ 107 #undef CONFIG_SYS_MEMTEST_SCRATCH 108 109 /* Enable temporary baudrate change while serial download */ 110 #undef CONFIG_SYS_LOADS_BAUD_CHANGE 111 112 /* FLASH */ 113 #define CONFIG_FLASH_CFI_DRIVER 1 114 #define CONFIG_SYS_FLASH_CFI 115 #undef CONFIG_SYS_FLASH_QUIET_TEST 116 #define CONFIG_SYS_FLASH_EMPTY_INFO 117 #define CONFIG_SYS_FLASH_BASE (0xA0000000) 118 #define CONFIG_SYS_MAX_FLASH_SECT 512 119 120 /* if you use all NOR Flash , you change dip-switch. Please see Manual. */ 121 #define CONFIG_SYS_MAX_FLASH_BANKS 1 122 #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE } 123 124 /* Timeout for Flash erase operations (in ms) */ 125 #define CONFIG_SYS_FLASH_ERASE_TOUT (3 * 1000) 126 /* Timeout for Flash write operations (in ms) */ 127 #define CONFIG_SYS_FLASH_WRITE_TOUT (3 * 1000) 128 /* Timeout for Flash set sector lock bit operations (in ms) */ 129 #define CONFIG_SYS_FLASH_LOCK_TOUT (3 * 1000) 130 /* Timeout for Flash clear lock bit operations (in ms) */ 131 #define CONFIG_SYS_FLASH_UNLOCK_TOUT (3 * 1000) 132 133 /* 134 * Use hardware flash sectors protection instead 135 * of U-Boot software protection 136 */ 137 #undef CONFIG_SYS_FLASH_PROTECTION 138 #undef CONFIG_SYS_DIRECT_FLASH_TFTP 139 140 /* Address of u-boot image in Flash (NOT run time address in SDRAM) ?!? */ 141 #define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE) 142 /* Monitor size */ 143 #define CONFIG_SYS_MONITOR_LEN (256 * 1024) 144 /* Size of DRAM reserved for malloc() use */ 145 #define CONFIG_SYS_MALLOC_LEN (256 * 1024) 146 /* size in bytes reserved for initial data */ 147 #define CONFIG_SYS_GBL_DATA_SIZE (256) 148 #define CONFIG_SYS_BOOTMAPSZ (8 * 1024 * 1024) 149 150 /* ENV setting */ 151 #define CONFIG_ENV_IS_IN_FLASH 152 #define CONFIG_ENV_OVERWRITE 1 153 #define CONFIG_ENV_SECT_SIZE (128 * 1024) 154 #define CONFIG_ENV_SIZE (CONFIG_ENV_SECT_SIZE) 155 #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_SYS_MONITOR_LEN) 156 /* Offset of env Flash sector relative to CONFIG_SYS_FLASH_BASE */ 157 #define CONFIG_ENV_OFFSET (CONFIG_ENV_ADDR - CONFIG_SYS_FLASH_BASE) 158 #define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SECT_SIZE) 159 160 /* Board Clock */ 161 #if defined(CONFIG_400MHZ_MODE) 162 #define CONFIG_SYS_CLK_FREQ 50000000 163 #else 164 #define CONFIG_SYS_CLK_FREQ 44444444 165 #endif 166 #define CONFIG_SH_TMU_CLK_FREQ CONFIG_SYS_CLK_FREQ 167 #define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ 168 #define CONFIG_SYS_TMU_CLK_DIV 4 169 170 #endif /* __R0P7734_H */ 171