1 /* 2 * Configuation settings for the Renesas Solutions r0p7734 board 3 * 4 * Copyright (C) 2010, 2011 Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com> 5 * 6 * SPDX-License-Identifier: GPL-2.0+ 7 */ 8 9 #ifndef __R0P7734_H 10 #define __R0P7734_H 11 12 #undef DEBUG 13 #define CONFIG_CPU_SH7734 1 14 #define CONFIG_R0P7734 1 15 #define CONFIG_400MHZ_MODE 1 16 /* #define CONFIG_533MHZ_MODE 1 */ 17 18 #define CONFIG_BOARD_LATE_INIT 19 #define CONFIG_SYS_TEXT_BASE 0x8FFC0000 20 21 #define CONFIG_CMD_FLASH 22 #define CONFIG_CMD_MEMORY 23 #define CONFIG_CMD_NET 24 #define CONFIG_CMD_PING 25 #define CONFIG_CMD_MII 26 #define CONFIG_CMD_NFS 27 #define CONFIG_CMD_SDRAM 28 #define CONFIG_CMD_ENV 29 #define CONFIG_CMD_SAVEENV 30 31 #define CONFIG_BAUDRATE 115200 32 #define CONFIG_BOOTDELAY 3 33 #define CONFIG_BOOTARGS "console=ttySC3,115200" 34 35 #define CONFIG_VERSION_VARIABLE 36 #undef CONFIG_SHOW_BOOT_PROGRESS 37 38 /* Ether */ 39 #define CONFIG_SH_ETHER 1 40 #define CONFIG_SH_ETHER_USE_PORT (0) 41 #define CONFIG_SH_ETHER_PHY_ADDR (0x0) 42 #define CONFIG_PHYLIB 43 #define CONFIG_PHY_SMSC 1 44 #define CONFIG_BITBANGMII 45 #define CONFIG_BITBANGMII_MULTI 46 #define CONFIG_SH_ETHER_SH7734_MII (0x00) /* MII */ 47 #define CONFIG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_MII 48 #ifndef CONFIG_SH_ETHER 49 # define CONFIG_SMC911X 50 # define CONFIG_SMC911X_16_BIT 51 # define CONFIG_SMC911X_BASE (0x84000000) 52 #endif 53 54 55 /* I2C */ 56 #define CONFIG_CMD_I2C 57 #define CONFIG_SH_SH7734_I2C 1 58 #define CONFIG_HARD_I2C 1 59 #define CONFIG_I2C_MULTI_BUS 1 60 #define CONFIG_SYS_MAX_I2C_BUS 2 61 #define CONFIG_SYS_I2C_MODULE 0 62 #define CONFIG_SYS_I2C_SPEED 100000 /* 100 kHz */ 63 #define CONFIG_SYS_I2C_SLAVE 0x50 64 #define CONFIG_SH_I2C_DATA_HIGH 4 65 #define CONFIG_SH_I2C_DATA_LOW 5 66 #define CONFIG_SH_I2C_CLOCK 500000000 67 #define CONFIG_SH_I2C_BASE0 0xFFC70000 68 #define CONFIG_SH_I2C_BASE1 0xFFC7100 69 70 /* undef to save memory */ 71 #define CONFIG_SYS_LONGHELP 72 /* Monitor Command Prompt */ 73 /* Buffer size for input from the Console */ 74 #define CONFIG_SYS_CBSIZE 256 75 /* Buffer size for Console output */ 76 #define CONFIG_SYS_PBSIZE 256 77 /* max args accepted for monitor commands */ 78 #define CONFIG_SYS_MAXARGS 16 79 /* Buffer size for Boot Arguments passed to kernel */ 80 #define CONFIG_SYS_BARGSIZE 512 81 /* List of legal baudrate settings for this board */ 82 #define CONFIG_SYS_BAUDRATE_TABLE { 115200 } 83 84 /* SCIF */ 85 #define CONFIG_SCIF_CONSOLE 1 86 #define CONFIG_SCIF 1 87 #define CONFIG_CONS_SCIF3 1 88 89 /* Suppress display of console information at boot */ 90 #undef CONFIG_SYS_CONSOLE_INFO_QUIET 91 #undef CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE 92 #undef CONFIG_SYS_CONSOLE_ENV_OVERWRITE 93 94 /* SDRAM */ 95 #define CONFIG_SYS_SDRAM_BASE (0x88000000) 96 #define CONFIG_SYS_SDRAM_SIZE (128 * 1024 * 1024) 97 #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 16 * 1024 * 1024) 98 99 #define CONFIG_SYS_MEMTEST_START (CONFIG_SYS_SDRAM_BASE) 100 #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + 100 * 1024 * 1024) 101 /* Enable alternate, more extensive, memory test */ 102 #undef CONFIG_SYS_ALT_MEMTEST 103 /* Scratch address used by the alternate memory test */ 104 #undef CONFIG_SYS_MEMTEST_SCRATCH 105 106 /* Enable temporary baudrate change while serial download */ 107 #undef CONFIG_SYS_LOADS_BAUD_CHANGE 108 109 /* FLASH */ 110 #define CONFIG_FLASH_CFI_DRIVER 1 111 #define CONFIG_SYS_FLASH_CFI 112 #undef CONFIG_SYS_FLASH_QUIET_TEST 113 #define CONFIG_SYS_FLASH_EMPTY_INFO 114 #define CONFIG_SYS_FLASH_BASE (0xA0000000) 115 #define CONFIG_SYS_MAX_FLASH_SECT 512 116 117 /* if you use all NOR Flash , you change dip-switch. Please see Manual. */ 118 #define CONFIG_SYS_MAX_FLASH_BANKS 1 119 #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE } 120 121 /* Timeout for Flash erase operations (in ms) */ 122 #define CONFIG_SYS_FLASH_ERASE_TOUT (3 * 1000) 123 /* Timeout for Flash write operations (in ms) */ 124 #define CONFIG_SYS_FLASH_WRITE_TOUT (3 * 1000) 125 /* Timeout for Flash set sector lock bit operations (in ms) */ 126 #define CONFIG_SYS_FLASH_LOCK_TOUT (3 * 1000) 127 /* Timeout for Flash clear lock bit operations (in ms) */ 128 #define CONFIG_SYS_FLASH_UNLOCK_TOUT (3 * 1000) 129 130 /* 131 * Use hardware flash sectors protection instead 132 * of U-Boot software protection 133 */ 134 #undef CONFIG_SYS_FLASH_PROTECTION 135 #undef CONFIG_SYS_DIRECT_FLASH_TFTP 136 137 /* Address of u-boot image in Flash (NOT run time address in SDRAM) ?!? */ 138 #define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE) 139 /* Monitor size */ 140 #define CONFIG_SYS_MONITOR_LEN (256 * 1024) 141 /* Size of DRAM reserved for malloc() use */ 142 #define CONFIG_SYS_MALLOC_LEN (256 * 1024) 143 #define CONFIG_SYS_BOOTMAPSZ (8 * 1024 * 1024) 144 145 /* ENV setting */ 146 #define CONFIG_ENV_IS_IN_FLASH 147 #define CONFIG_ENV_OVERWRITE 1 148 #define CONFIG_ENV_SECT_SIZE (128 * 1024) 149 #define CONFIG_ENV_SIZE (CONFIG_ENV_SECT_SIZE) 150 #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_SYS_MONITOR_LEN) 151 /* Offset of env Flash sector relative to CONFIG_SYS_FLASH_BASE */ 152 #define CONFIG_ENV_OFFSET (CONFIG_ENV_ADDR - CONFIG_SYS_FLASH_BASE) 153 #define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SECT_SIZE) 154 155 /* Board Clock */ 156 #if defined(CONFIG_400MHZ_MODE) 157 #define CONFIG_SYS_CLK_FREQ 50000000 158 #else 159 #define CONFIG_SYS_CLK_FREQ 44444444 160 #endif 161 #define CONFIG_SH_TMU_CLK_FREQ CONFIG_SYS_CLK_FREQ 162 #define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ 163 #define CONFIG_SYS_TMU_CLK_DIV 4 164 165 #endif /* __R0P7734_H */ 166