1 /* 2 * Configuation settings for the Renesas Solutions r0p7734 board 3 * 4 * Copyright (C) 2010, 2011 Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com> 5 * 6 * SPDX-License-Identifier: GPL-2.0+ 7 */ 8 9 #ifndef __R0P7734_H 10 #define __R0P7734_H 11 12 #undef DEBUG 13 #define CONFIG_CPU_SH7734 1 14 #define CONFIG_R0P7734 1 15 #define CONFIG_400MHZ_MODE 1 16 /* #define CONFIG_533MHZ_MODE 1 */ 17 18 #define CONFIG_BOARD_LATE_INIT 19 #define CONFIG_SYS_TEXT_BASE 0x8FFC0000 20 21 #define CONFIG_CMD_PING 22 #define CONFIG_CMD_MII 23 #define CONFIG_CMD_SDRAM 24 #define CONFIG_CMD_ENV 25 26 #define CONFIG_BAUDRATE 115200 27 #define CONFIG_BOOTDELAY 3 28 #define CONFIG_BOOTARGS "console=ttySC3,115200" 29 30 #define CONFIG_VERSION_VARIABLE 31 #undef CONFIG_SHOW_BOOT_PROGRESS 32 33 /* Ether */ 34 #define CONFIG_SH_ETHER 1 35 #define CONFIG_SH_ETHER_USE_PORT (0) 36 #define CONFIG_SH_ETHER_PHY_ADDR (0x0) 37 #define CONFIG_PHYLIB 38 #define CONFIG_PHY_SMSC 1 39 #define CONFIG_BITBANGMII 40 #define CONFIG_BITBANGMII_MULTI 41 #define CONFIG_SH_ETHER_SH7734_MII (0x00) /* MII */ 42 #define CONFIG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_MII 43 #ifndef CONFIG_SH_ETHER 44 # define CONFIG_SMC911X 45 # define CONFIG_SMC911X_16_BIT 46 # define CONFIG_SMC911X_BASE (0x84000000) 47 #endif 48 49 50 /* I2C */ 51 #define CONFIG_CMD_I2C 52 #define CONFIG_SH_SH7734_I2C 1 53 #define CONFIG_HARD_I2C 1 54 #define CONFIG_I2C_MULTI_BUS 1 55 #define CONFIG_SYS_MAX_I2C_BUS 2 56 #define CONFIG_SYS_I2C_MODULE 0 57 #define CONFIG_SYS_I2C_SPEED 100000 /* 100 kHz */ 58 #define CONFIG_SYS_I2C_SLAVE 0x50 59 #define CONFIG_SH_I2C_DATA_HIGH 4 60 #define CONFIG_SH_I2C_DATA_LOW 5 61 #define CONFIG_SH_I2C_CLOCK 500000000 62 #define CONFIG_SH_I2C_BASE0 0xFFC70000 63 #define CONFIG_SH_I2C_BASE1 0xFFC7100 64 65 /* undef to save memory */ 66 #define CONFIG_SYS_LONGHELP 67 /* Monitor Command Prompt */ 68 /* Buffer size for input from the Console */ 69 #define CONFIG_SYS_CBSIZE 256 70 /* Buffer size for Console output */ 71 #define CONFIG_SYS_PBSIZE 256 72 /* max args accepted for monitor commands */ 73 #define CONFIG_SYS_MAXARGS 16 74 /* Buffer size for Boot Arguments passed to kernel */ 75 #define CONFIG_SYS_BARGSIZE 512 76 /* List of legal baudrate settings for this board */ 77 #define CONFIG_SYS_BAUDRATE_TABLE { 115200 } 78 79 /* SCIF */ 80 #define CONFIG_SCIF_CONSOLE 1 81 #define CONFIG_SCIF 1 82 #define CONFIG_CONS_SCIF3 1 83 84 /* Suppress display of console information at boot */ 85 #undef CONFIG_SYS_CONSOLE_INFO_QUIET 86 #undef CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE 87 #undef CONFIG_SYS_CONSOLE_ENV_OVERWRITE 88 89 /* SDRAM */ 90 #define CONFIG_SYS_SDRAM_BASE (0x88000000) 91 #define CONFIG_SYS_SDRAM_SIZE (128 * 1024 * 1024) 92 #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 16 * 1024 * 1024) 93 94 #define CONFIG_SYS_MEMTEST_START (CONFIG_SYS_SDRAM_BASE) 95 #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + 100 * 1024 * 1024) 96 /* Enable alternate, more extensive, memory test */ 97 #undef CONFIG_SYS_ALT_MEMTEST 98 /* Scratch address used by the alternate memory test */ 99 #undef CONFIG_SYS_MEMTEST_SCRATCH 100 101 /* Enable temporary baudrate change while serial download */ 102 #undef CONFIG_SYS_LOADS_BAUD_CHANGE 103 104 /* FLASH */ 105 #define CONFIG_FLASH_CFI_DRIVER 1 106 #define CONFIG_SYS_FLASH_CFI 107 #undef CONFIG_SYS_FLASH_QUIET_TEST 108 #define CONFIG_SYS_FLASH_EMPTY_INFO 109 #define CONFIG_SYS_FLASH_BASE (0xA0000000) 110 #define CONFIG_SYS_MAX_FLASH_SECT 512 111 112 /* if you use all NOR Flash , you change dip-switch. Please see Manual. */ 113 #define CONFIG_SYS_MAX_FLASH_BANKS 1 114 #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE } 115 116 /* Timeout for Flash erase operations (in ms) */ 117 #define CONFIG_SYS_FLASH_ERASE_TOUT (3 * 1000) 118 /* Timeout for Flash write operations (in ms) */ 119 #define CONFIG_SYS_FLASH_WRITE_TOUT (3 * 1000) 120 /* Timeout for Flash set sector lock bit operations (in ms) */ 121 #define CONFIG_SYS_FLASH_LOCK_TOUT (3 * 1000) 122 /* Timeout for Flash clear lock bit operations (in ms) */ 123 #define CONFIG_SYS_FLASH_UNLOCK_TOUT (3 * 1000) 124 125 /* 126 * Use hardware flash sectors protection instead 127 * of U-Boot software protection 128 */ 129 #undef CONFIG_SYS_FLASH_PROTECTION 130 #undef CONFIG_SYS_DIRECT_FLASH_TFTP 131 132 /* Address of u-boot image in Flash (NOT run time address in SDRAM) ?!? */ 133 #define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE) 134 /* Monitor size */ 135 #define CONFIG_SYS_MONITOR_LEN (256 * 1024) 136 /* Size of DRAM reserved for malloc() use */ 137 #define CONFIG_SYS_MALLOC_LEN (256 * 1024) 138 #define CONFIG_SYS_BOOTMAPSZ (8 * 1024 * 1024) 139 140 /* ENV setting */ 141 #define CONFIG_ENV_IS_IN_FLASH 142 #define CONFIG_ENV_OVERWRITE 1 143 #define CONFIG_ENV_SECT_SIZE (128 * 1024) 144 #define CONFIG_ENV_SIZE (CONFIG_ENV_SECT_SIZE) 145 #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_SYS_MONITOR_LEN) 146 /* Offset of env Flash sector relative to CONFIG_SYS_FLASH_BASE */ 147 #define CONFIG_ENV_OFFSET (CONFIG_ENV_ADDR - CONFIG_SYS_FLASH_BASE) 148 #define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SECT_SIZE) 149 150 /* Board Clock */ 151 #if defined(CONFIG_400MHZ_MODE) 152 #define CONFIG_SYS_CLK_FREQ 50000000 153 #else 154 #define CONFIG_SYS_CLK_FREQ 44444444 155 #endif 156 #define CONFIG_SH_TMU_CLK_FREQ CONFIG_SYS_CLK_FREQ 157 #define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ 158 #define CONFIG_SYS_TMU_CLK_DIV 4 159 160 #endif /* __R0P7734_H */ 161