1 /* 2 * Configuation settings for the Renesas Solutions r0p7734 board 3 * 4 * Copyright (C) 2010, 2011 Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com> 5 * 6 * SPDX-License-Identifier: GPL-2.0+ 7 */ 8 9 #ifndef __R0P7734_H 10 #define __R0P7734_H 11 12 #undef DEBUG 13 #define CONFIG_CPU_SH7734 1 14 #define CONFIG_R0P7734 1 15 #define CONFIG_400MHZ_MODE 1 16 /* #define CONFIG_533MHZ_MODE 1 */ 17 18 #define CONFIG_BOARD_LATE_INIT 19 #define CONFIG_SYS_TEXT_BASE 0x8FFC0000 20 21 #define CONFIG_CMD_SDRAM 22 #define CONFIG_CMD_ENV 23 24 #define CONFIG_BAUDRATE 115200 25 #define CONFIG_BOOTARGS "console=ttySC3,115200" 26 27 #undef CONFIG_SHOW_BOOT_PROGRESS 28 29 /* Ether */ 30 #define CONFIG_SH_ETHER 1 31 #define CONFIG_SH_ETHER_USE_PORT (0) 32 #define CONFIG_SH_ETHER_PHY_ADDR (0x0) 33 #define CONFIG_PHYLIB 34 #define CONFIG_PHY_SMSC 1 35 #define CONFIG_BITBANGMII 36 #define CONFIG_BITBANGMII_MULTI 37 #define CONFIG_SH_ETHER_SH7734_MII (0x00) /* MII */ 38 #define CONFIG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_MII 39 #ifndef CONFIG_SH_ETHER 40 # define CONFIG_SMC911X 41 # define CONFIG_SMC911X_16_BIT 42 # define CONFIG_SMC911X_BASE (0x84000000) 43 #endif 44 45 /* I2C */ 46 #define CONFIG_SH_SH7734_I2C 1 47 #define CONFIG_HARD_I2C 1 48 #define CONFIG_I2C_MULTI_BUS 1 49 #define CONFIG_SYS_MAX_I2C_BUS 2 50 #define CONFIG_SYS_I2C_MODULE 0 51 #define CONFIG_SYS_I2C_SPEED 100000 /* 100 kHz */ 52 #define CONFIG_SYS_I2C_SLAVE 0x50 53 #define CONFIG_SH_I2C_DATA_HIGH 4 54 #define CONFIG_SH_I2C_DATA_LOW 5 55 #define CONFIG_SH_I2C_CLOCK 500000000 56 #define CONFIG_SH_I2C_BASE0 0xFFC70000 57 #define CONFIG_SH_I2C_BASE1 0xFFC7100 58 59 /* undef to save memory */ 60 #define CONFIG_SYS_LONGHELP 61 /* Monitor Command Prompt */ 62 /* Buffer size for input from the Console */ 63 #define CONFIG_SYS_CBSIZE 256 64 /* Buffer size for Console output */ 65 #define CONFIG_SYS_PBSIZE 256 66 /* max args accepted for monitor commands */ 67 #define CONFIG_SYS_MAXARGS 16 68 /* Buffer size for Boot Arguments passed to kernel */ 69 #define CONFIG_SYS_BARGSIZE 512 70 /* List of legal baudrate settings for this board */ 71 #define CONFIG_SYS_BAUDRATE_TABLE { 115200 } 72 73 /* SCIF */ 74 #define CONFIG_SCIF_CONSOLE 1 75 #define CONFIG_SCIF 1 76 #define CONFIG_CONS_SCIF3 1 77 78 /* Suppress display of console information at boot */ 79 80 /* SDRAM */ 81 #define CONFIG_SYS_SDRAM_BASE (0x88000000) 82 #define CONFIG_SYS_SDRAM_SIZE (128 * 1024 * 1024) 83 #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 16 * 1024 * 1024) 84 85 #define CONFIG_SYS_MEMTEST_START (CONFIG_SYS_SDRAM_BASE) 86 #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + 100 * 1024 * 1024) 87 /* Enable alternate, more extensive, memory test */ 88 #undef CONFIG_SYS_ALT_MEMTEST 89 /* Scratch address used by the alternate memory test */ 90 #undef CONFIG_SYS_MEMTEST_SCRATCH 91 92 /* Enable temporary baudrate change while serial download */ 93 #undef CONFIG_SYS_LOADS_BAUD_CHANGE 94 95 /* FLASH */ 96 #define CONFIG_FLASH_CFI_DRIVER 1 97 #define CONFIG_SYS_FLASH_CFI 98 #undef CONFIG_SYS_FLASH_QUIET_TEST 99 #define CONFIG_SYS_FLASH_EMPTY_INFO 100 #define CONFIG_SYS_FLASH_BASE (0xA0000000) 101 #define CONFIG_SYS_MAX_FLASH_SECT 512 102 103 /* if you use all NOR Flash , you change dip-switch. Please see Manual. */ 104 #define CONFIG_SYS_MAX_FLASH_BANKS 1 105 #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE } 106 107 /* Timeout for Flash erase operations (in ms) */ 108 #define CONFIG_SYS_FLASH_ERASE_TOUT (3 * 1000) 109 /* Timeout for Flash write operations (in ms) */ 110 #define CONFIG_SYS_FLASH_WRITE_TOUT (3 * 1000) 111 /* Timeout for Flash set sector lock bit operations (in ms) */ 112 #define CONFIG_SYS_FLASH_LOCK_TOUT (3 * 1000) 113 /* Timeout for Flash clear lock bit operations (in ms) */ 114 #define CONFIG_SYS_FLASH_UNLOCK_TOUT (3 * 1000) 115 116 /* 117 * Use hardware flash sectors protection instead 118 * of U-Boot software protection 119 */ 120 #undef CONFIG_SYS_FLASH_PROTECTION 121 #undef CONFIG_SYS_DIRECT_FLASH_TFTP 122 123 /* Address of u-boot image in Flash (NOT run time address in SDRAM) ?!? */ 124 #define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE) 125 /* Monitor size */ 126 #define CONFIG_SYS_MONITOR_LEN (256 * 1024) 127 /* Size of DRAM reserved for malloc() use */ 128 #define CONFIG_SYS_MALLOC_LEN (256 * 1024) 129 #define CONFIG_SYS_BOOTMAPSZ (8 * 1024 * 1024) 130 131 /* ENV setting */ 132 #define CONFIG_ENV_IS_IN_FLASH 133 #define CONFIG_ENV_OVERWRITE 1 134 #define CONFIG_ENV_SECT_SIZE (128 * 1024) 135 #define CONFIG_ENV_SIZE (CONFIG_ENV_SECT_SIZE) 136 #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_SYS_MONITOR_LEN) 137 /* Offset of env Flash sector relative to CONFIG_SYS_FLASH_BASE */ 138 #define CONFIG_ENV_OFFSET (CONFIG_ENV_ADDR - CONFIG_SYS_FLASH_BASE) 139 #define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SECT_SIZE) 140 141 /* Board Clock */ 142 #if defined(CONFIG_400MHZ_MODE) 143 #define CONFIG_SYS_CLK_FREQ 50000000 144 #else 145 #define CONFIG_SYS_CLK_FREQ 44444444 146 #endif 147 #define CONFIG_SH_TMU_CLK_FREQ CONFIG_SYS_CLK_FREQ 148 #define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ 149 #define CONFIG_SYS_TMU_CLK_DIV 4 150 151 #endif /* __R0P7734_H */ 152