1a65b25d1SBin Meng /* 2a65b25d1SBin Meng * Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com> 3a65b25d1SBin Meng * 4a65b25d1SBin Meng * SPDX-License-Identifier: GPL-2.0+ 5a65b25d1SBin Meng */ 6a65b25d1SBin Meng 7a65b25d1SBin Meng /* 8a65b25d1SBin Meng * board/config.h - configuration options, board specific 9a65b25d1SBin Meng */ 10a65b25d1SBin Meng 11a65b25d1SBin Meng #ifndef __CONFIG_H 12a65b25d1SBin Meng #define __CONFIG_H 13a65b25d1SBin Meng 14a65b25d1SBin Meng #include <configs/x86-common.h> 15a65b25d1SBin Meng 16a65b25d1SBin Meng #define CONFIG_SYS_MONITOR_LEN (1 << 20) 17a65b25d1SBin Meng 18b6ff6ce6SBin Meng #define CONFIG_STD_DEVICES_SETTINGS "stdin=serial,i8042-kbd\0" \ 19fcda8c38SBin Meng "stdout=serial,vidconsole\0" \ 20fcda8c38SBin Meng "stderr=serial,vidconsole\0" 21a65b25d1SBin Meng 222aa3a7fbSBin Meng /* 232aa3a7fbSBin Meng * ATA/SATA support for QEMU x86 targets 242aa3a7fbSBin Meng * - Only legacy IDE controller is supported for QEMU '-M pc' target 252aa3a7fbSBin Meng * - AHCI controller is supported for QEMU '-M q35' target 262aa3a7fbSBin Meng * 272aa3a7fbSBin Meng * Default configuraion is to support the QEMU default x86 target 282aa3a7fbSBin Meng * Undefine CONFIG_CMD_IDE to support q35 target 292aa3a7fbSBin Meng */ 302aa3a7fbSBin Meng #define CONFIG_CMD_IDE 312aa3a7fbSBin Meng #ifdef CONFIG_CMD_IDE 322aa3a7fbSBin Meng #define CONFIG_SYS_IDE_MAXBUS 2 332aa3a7fbSBin Meng #define CONFIG_SYS_IDE_MAXDEVICE 4 342aa3a7fbSBin Meng #define CONFIG_SYS_ATA_BASE_ADDR 0 352aa3a7fbSBin Meng #define CONFIG_SYS_ATA_DATA_OFFSET 0 362aa3a7fbSBin Meng #define CONFIG_SYS_ATA_REG_OFFSET 0 372aa3a7fbSBin Meng #define CONFIG_SYS_ATA_ALT_OFFSET 0 382aa3a7fbSBin Meng #define CONFIG_SYS_ATA_IDE0_OFFSET 0x1f0 392aa3a7fbSBin Meng #define CONFIG_SYS_ATA_IDE1_OFFSET 0x170 402aa3a7fbSBin Meng #define CONFIG_ATAPI 412aa3a7fbSBin Meng 422aa3a7fbSBin Meng #undef CONFIG_SCSI_AHCI 43c649e3c9SSimon Glass #undef CONFIG_SCSI 442aa3a7fbSBin Meng #else 45a65b25d1SBin Meng #define CONFIG_SCSI_DEV_LIST \ 462aa3a7fbSBin Meng {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_AHCI} 472aa3a7fbSBin Meng #endif 48a65b25d1SBin Meng 49a65b25d1SBin Meng /* GPIO is not supported */ 50a65b25d1SBin Meng #undef CONFIG_INTEL_ICH6_GPIO 51a65b25d1SBin Meng 52a65b25d1SBin Meng /* SPI is not supported */ 53a65b25d1SBin Meng #undef CONFIG_ENV_IS_IN_SPI_FLASH 54a65b25d1SBin Meng #define CONFIG_ENV_IS_NOWHERE 55a65b25d1SBin Meng 56*73d2de2bSBin Meng #define CONFIG_SPL_FRAMEWORK 57*73d2de2bSBin Meng 58*73d2de2bSBin Meng #define CONFIG_SPL_TEXT_BASE 0xfffd0000 59*73d2de2bSBin Meng 60*73d2de2bSBin Meng #define BOOT_DEVICE_SPI 10 61*73d2de2bSBin Meng 62*73d2de2bSBin Meng #define CONFIG_SPL_BOARD_LOAD_IMAGE 63*73d2de2bSBin Meng #define BOOT_DEVICE_BOARD 11 64*73d2de2bSBin Meng 65a65b25d1SBin Meng #endif /* __CONFIG_H */ 66