1 /*
2  * Copyright 2011-2014 Freescale Semiconductor, Inc.
3  *
4  * SPDX-License-Identifier:	GPL-2.0+
5  */
6 
7 /*
8  * Corenet DS style board configuration file
9  */
10 #ifndef __QEMU_PPCE500_H
11 #define __QEMU_PPCE500_H
12 
13 #undef CONFIG_SYS_TEXT_BASE
14 #define CONFIG_SYS_TEXT_BASE	0xf01000 /* 15 MB */
15 
16 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
17 
18 #define CONFIG_SYS_RAMBOOT
19 
20 #define CONFIG_PCI1		1	/* PCI controller 1 */
21 #define CONFIG_FSL_PCI_INIT		/* Use common FSL init code */
22 #define CONFIG_SYS_PCI_64BIT		/* enable 64-bit PCI resources */
23 
24 #define CONFIG_ENV_OVERWRITE
25 
26 #define CONFIG_ENABLE_36BIT_PHYS
27 
28 #define CONFIG_ADDR_MAP
29 #define CONFIG_SYS_NUM_ADDR_MAP		16	/* number of TLB1 entries */
30 
31 #define CONFIG_SYS_MEMTEST_START	0x00200000	/* memtest works on */
32 #define CONFIG_SYS_MEMTEST_END		0x00400000
33 #define CONFIG_SYS_ALT_MEMTEST
34 #define CONFIG_PANIC_HANG	/* do not reset board on panic */
35 
36 /* Needed to fill the ccsrbar pointer */
37 
38 /* Virtual address to CCSRBAR */
39 #define CONFIG_SYS_CCSRBAR		0xe0000000
40 /* Physical address should be a function call */
41 #ifndef __ASSEMBLY__
42 extern unsigned long long get_phys_ccsrbar_addr_early(void);
43 #define CONFIG_SYS_CCSRBAR_PHYS_HIGH (get_phys_ccsrbar_addr_early() >> 32)
44 #define CONFIG_SYS_CCSRBAR_PHYS_LOW get_phys_ccsrbar_addr_early()
45 #else
46 #define CONFIG_SYS_CCSRBAR_PHYS_HIGH 0x0
47 #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
48 #endif
49 
50 /* Virtual address range for PCI region maps */
51 #define CONFIG_SYS_PCI_MAP_START	0x80000000
52 #define CONFIG_SYS_PCI_MAP_END		0xe8000000
53 
54 /* Virtual address to a temporary map if we need it (max 128MB) */
55 #define CONFIG_SYS_TMPVIRT		0xe8000000
56 
57 /*
58  * DDR Setup
59  */
60 #define CONFIG_VERY_BIG_RAM
61 #define CONFIG_SYS_DDR_SDRAM_BASE	0x00000000
62 #define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_DDR_SDRAM_BASE
63 
64 #define CONFIG_CHIP_SELECTS_PER_CTRL	0
65 
66 #define CONFIG_SYS_CLK_FREQ        33000000
67 
68 #define CONFIG_SYS_BOOT_BLOCK		0x00000000	/* boot TLB */
69 
70 #define CONFIG_SYS_MONITOR_BASE		CONFIG_SYS_TEXT_BASE
71 
72 #define CONFIG_HWCONFIG
73 
74 #define CONFIG_SYS_INIT_RAM_ADDR		0x00100000
75 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH	0x0
76 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW	0x00100000
77 /* The assembler doesn't like typecast */
78 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
79 	((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
80 	  CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
81 #define CONFIG_SYS_INIT_RAM_SIZE		0x00004000
82 
83 #define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - \
84 					GENERATED_GBL_DATA_SIZE)
85 #define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
86 
87 #define CONFIG_SYS_MONITOR_LEN		(512 * 1024)
88 #define CONFIG_SYS_MALLOC_LEN		(4 * 1024 * 1024)
89 
90 #define CONFIG_CONS_INDEX	1
91 #define CONFIG_SYS_NS16550_SERIAL
92 #define CONFIG_SYS_NS16550_REG_SIZE	1
93 #define CONFIG_SYS_NS16550_CLK		(get_bus_freq(0))
94 
95 #define CONFIG_SYS_BAUDRATE_TABLE	\
96 	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
97 
98 #define CONFIG_SYS_NS16550_COM1	(CONFIG_SYS_CCSRBAR+0x4500)
99 #define CONFIG_SYS_NS16550_COM2	(CONFIG_SYS_CCSRBAR+0x4600)
100 
101 /*
102  * General PCI
103  * Memory space is mapped 1-1, but I/O space must start from 0.
104  */
105 
106 #ifdef CONFIG_PCI
107 #define CONFIG_PCI_INDIRECT_BRIDGE
108 
109 #define CONFIG_PCI_SCAN_SHOW		/* show pci devices on startup */
110 #endif	/* CONFIG_PCI */
111 
112 #define CONFIG_LBA48
113 
114 /*
115  * Environment
116  */
117 #define CONFIG_ENV_SIZE		0x2000
118 
119 #define CONFIG_LOADS_ECHO		/* echo on for serial download */
120 
121 #define CONFIG_LAST_STAGE_INIT
122 
123 /*
124  * Command line configuration.
125  */
126 
127 /*
128  * Miscellaneous configurable options
129  */
130 #define CONFIG_SYS_LONGHELP			/* undef to save memory	*/
131 #define CONFIG_CMDLINE_EDITING			/* Command-line editing */
132 #define CONFIG_AUTO_COMPLETE			/* add autocompletion support */
133 #define CONFIG_SYS_LOAD_ADDR	0x2000000	/* default load address */
134 #define CONFIG_SYS_CBSIZE	256		/* Console I/O Buffer Size */
135 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
136 #define CONFIG_SYS_MAXARGS	16		/* max number of command args */
137 #define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */
138 
139 /*
140  * For booting Linux, the board info and command line data
141  * have to be in the first 64 MB of memory, since this is
142  * the maximum mapped by the Linux kernel during initialization.
143  */
144 #define CONFIG_SYS_BOOTMAPSZ	(64 << 20)	/* Initial map for Linux*/
145 #define CONFIG_SYS_BOOTM_LEN	(64 << 20)	/* Increase max gunzip size */
146 
147 /*
148  * Environment Configuration
149  */
150 #define CONFIG_ROOTPATH		"/opt/nfsroot"
151 #define CONFIG_BOOTFILE		"uImage"
152 #define CONFIG_UBOOTPATH	"u-boot.bin"	/* U-Boot image on TFTP server*/
153 
154 /* default location for tftp and bootm */
155 #define CONFIG_LOADADDR		1000000
156 
157 #define CONFIG_BOOTCOMMAND		\
158 	"test -n \"$qemu_kernel_addr\" && bootm $qemu_kernel_addr - $fdt_addr_r\0"
159 
160 #endif	/* __QEMU_PPCE500_H */
161