1 /*
2  * Copyright 2011-2014 Freescale Semiconductor, Inc.
3  *
4  * SPDX-License-Identifier:	GPL-2.0+
5  */
6 
7 /*
8  * Corenet DS style board configuration file
9  */
10 #ifndef __QEMU_PPCE500_H
11 #define __QEMU_PPCE500_H
12 
13 #define CONFIG_CMD_REGINFO
14 
15 /* High Level Configuration Options */
16 #define CONFIG_BOOKE
17 #define CONFIG_E500			/* BOOKE e500 family */
18 
19 #undef CONFIG_SYS_TEXT_BASE
20 #define CONFIG_SYS_TEXT_BASE	0xf01000 /* 15 MB */
21 
22 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
23 
24 #define CONFIG_SYS_RAMBOOT
25 
26 #define CONFIG_PCI1		1	/* PCI controller 1 */
27 #define CONFIG_FSL_PCI_INIT		/* Use common FSL init code */
28 #define CONFIG_SYS_PCI_64BIT		/* enable 64-bit PCI resources */
29 
30 #define CONFIG_ENV_OVERWRITE
31 
32 #define CONFIG_ENABLE_36BIT_PHYS
33 
34 #define CONFIG_ADDR_MAP
35 #define CONFIG_SYS_NUM_ADDR_MAP		16	/* number of TLB1 entries */
36 
37 #define CONFIG_SYS_MEMTEST_START	0x00200000	/* memtest works on */
38 #define CONFIG_SYS_MEMTEST_END		0x00400000
39 #define CONFIG_SYS_ALT_MEMTEST
40 #define CONFIG_PANIC_HANG	/* do not reset board on panic */
41 
42 /* Needed to fill the ccsrbar pointer */
43 #define CONFIG_BOARD_EARLY_INIT_F
44 
45 /* Virtual address to CCSRBAR */
46 #define CONFIG_SYS_CCSRBAR		0xe0000000
47 /* Physical address should be a function call */
48 #ifndef __ASSEMBLY__
49 extern unsigned long long get_phys_ccsrbar_addr_early(void);
50 #define CONFIG_SYS_CCSRBAR_PHYS_HIGH (get_phys_ccsrbar_addr_early() >> 32)
51 #define CONFIG_SYS_CCSRBAR_PHYS_LOW get_phys_ccsrbar_addr_early()
52 #else
53 #define CONFIG_SYS_CCSRBAR_PHYS_HIGH 0x0
54 #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
55 #endif
56 
57 /* Virtual address range for PCI region maps */
58 #define CONFIG_SYS_PCI_MAP_START	0x80000000
59 #define CONFIG_SYS_PCI_MAP_END		0xe8000000
60 
61 /* Virtual address to a temporary map if we need it (max 128MB) */
62 #define CONFIG_SYS_TMPVIRT		0xe8000000
63 
64 /*
65  * DDR Setup
66  */
67 #define CONFIG_VERY_BIG_RAM
68 #define CONFIG_SYS_DDR_SDRAM_BASE	0x00000000
69 #define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_DDR_SDRAM_BASE
70 
71 #define CONFIG_CHIP_SELECTS_PER_CTRL	0
72 
73 #define CONFIG_SYS_CLK_FREQ        33000000
74 
75 #define CONFIG_SYS_NO_FLASH
76 
77 #define CONFIG_SYS_BOOT_BLOCK		0x00000000	/* boot TLB */
78 
79 #define CONFIG_SYS_MONITOR_BASE		CONFIG_SYS_TEXT_BASE
80 
81 #define CONFIG_ENV_IS_NOWHERE
82 
83 #define CONFIG_HWCONFIG
84 
85 #define CONFIG_SYS_INIT_RAM_ADDR		0x00100000
86 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH	0x0
87 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW	0x00100000
88 /* The assembler doesn't like typecast */
89 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
90 	((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
91 	  CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
92 #define CONFIG_SYS_INIT_RAM_SIZE		0x00004000
93 
94 #define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - \
95 					GENERATED_GBL_DATA_SIZE)
96 #define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
97 
98 #define CONFIG_SYS_MONITOR_LEN		(512 * 1024)
99 #define CONFIG_SYS_MALLOC_LEN		(4 * 1024 * 1024)
100 
101 #define CONFIG_CONS_INDEX	1
102 #define CONFIG_SYS_NS16550_SERIAL
103 #define CONFIG_SYS_NS16550_REG_SIZE	1
104 #define CONFIG_SYS_NS16550_CLK		(get_bus_freq(0))
105 
106 #define CONFIG_SYS_BAUDRATE_TABLE	\
107 	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
108 
109 #define CONFIG_SYS_NS16550_COM1	(CONFIG_SYS_CCSRBAR+0x4500)
110 #define CONFIG_SYS_NS16550_COM2	(CONFIG_SYS_CCSRBAR+0x4600)
111 
112 /*
113  * General PCI
114  * Memory space is mapped 1-1, but I/O space must start from 0.
115  */
116 
117 #ifdef CONFIG_PCI
118 #define CONFIG_PCI_INDIRECT_BRIDGE
119 
120 #define CONFIG_PCI_SCAN_SHOW		/* show pci devices on startup */
121 #define CONFIG_DOS_PARTITION
122 #endif	/* CONFIG_PCI */
123 
124 #define CONFIG_LBA48
125 #define CONFIG_DOS_PARTITION
126 
127 /*
128  * Environment
129  */
130 #define CONFIG_ENV_SIZE		0x2000
131 
132 #define CONFIG_LOADS_ECHO		/* echo on for serial download */
133 
134 #define CONFIG_LAST_STAGE_INIT
135 
136 /*
137  * Command line configuration.
138  */
139 #define CONFIG_CMD_IRQ
140 
141 #ifdef CONFIG_PCI
142 #define CONFIG_CMD_PCI
143 #endif
144 
145 /*
146  * Miscellaneous configurable options
147  */
148 #define CONFIG_SYS_LONGHELP			/* undef to save memory	*/
149 #define CONFIG_CMDLINE_EDITING			/* Command-line editing */
150 #define CONFIG_AUTO_COMPLETE			/* add autocompletion support */
151 #define CONFIG_SYS_LOAD_ADDR	0x2000000	/* default load address */
152 #define CONFIG_SYS_CBSIZE	256		/* Console I/O Buffer Size */
153 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
154 #define CONFIG_SYS_MAXARGS	16		/* max number of command args */
155 #define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */
156 
157 /*
158  * For booting Linux, the board info and command line data
159  * have to be in the first 64 MB of memory, since this is
160  * the maximum mapped by the Linux kernel during initialization.
161  */
162 #define CONFIG_SYS_BOOTMAPSZ	(64 << 20)	/* Initial map for Linux*/
163 #define CONFIG_SYS_BOOTM_LEN	(64 << 20)	/* Increase max gunzip size */
164 
165 /*
166  * Environment Configuration
167  */
168 #define CONFIG_ROOTPATH		"/opt/nfsroot"
169 #define CONFIG_BOOTFILE		"uImage"
170 #define CONFIG_UBOOTPATH	"u-boot.bin"	/* U-Boot image on TFTP server*/
171 
172 /* default location for tftp and bootm */
173 #define CONFIG_LOADADDR		1000000
174 
175 #define CONFIG_BAUDRATE	115200
176 
177 #define CONFIG_BOOTCOMMAND		\
178 	"test -n \"$qemu_kernel_addr\" && bootm $qemu_kernel_addr - $fdt_addr_r\0"
179 
180 #endif	/* __QEMU_PPCE500_H */
181