1 /*
2  * Copyright 2011-2014 Freescale Semiconductor, Inc.
3  *
4  * SPDX-License-Identifier:	GPL-2.0+
5  */
6 
7 /*
8  * Corenet DS style board configuration file
9  */
10 #ifndef __QEMU_PPCE500_H
11 #define __QEMU_PPCE500_H
12 
13 #define CONFIG_CMD_REGINFO
14 
15 #undef CONFIG_SYS_TEXT_BASE
16 #define CONFIG_SYS_TEXT_BASE	0xf01000 /* 15 MB */
17 
18 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
19 
20 #define CONFIG_SYS_RAMBOOT
21 
22 #define CONFIG_PCI1		1	/* PCI controller 1 */
23 #define CONFIG_FSL_PCI_INIT		/* Use common FSL init code */
24 #define CONFIG_SYS_PCI_64BIT		/* enable 64-bit PCI resources */
25 
26 #define CONFIG_ENV_OVERWRITE
27 
28 #define CONFIG_ENABLE_36BIT_PHYS
29 
30 #define CONFIG_ADDR_MAP
31 #define CONFIG_SYS_NUM_ADDR_MAP		16	/* number of TLB1 entries */
32 
33 #define CONFIG_SYS_MEMTEST_START	0x00200000	/* memtest works on */
34 #define CONFIG_SYS_MEMTEST_END		0x00400000
35 #define CONFIG_SYS_ALT_MEMTEST
36 #define CONFIG_PANIC_HANG	/* do not reset board on panic */
37 
38 /* Needed to fill the ccsrbar pointer */
39 
40 /* Virtual address to CCSRBAR */
41 #define CONFIG_SYS_CCSRBAR		0xe0000000
42 /* Physical address should be a function call */
43 #ifndef __ASSEMBLY__
44 extern unsigned long long get_phys_ccsrbar_addr_early(void);
45 #define CONFIG_SYS_CCSRBAR_PHYS_HIGH (get_phys_ccsrbar_addr_early() >> 32)
46 #define CONFIG_SYS_CCSRBAR_PHYS_LOW get_phys_ccsrbar_addr_early()
47 #else
48 #define CONFIG_SYS_CCSRBAR_PHYS_HIGH 0x0
49 #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
50 #endif
51 
52 /* Virtual address range for PCI region maps */
53 #define CONFIG_SYS_PCI_MAP_START	0x80000000
54 #define CONFIG_SYS_PCI_MAP_END		0xe8000000
55 
56 /* Virtual address to a temporary map if we need it (max 128MB) */
57 #define CONFIG_SYS_TMPVIRT		0xe8000000
58 
59 /*
60  * DDR Setup
61  */
62 #define CONFIG_VERY_BIG_RAM
63 #define CONFIG_SYS_DDR_SDRAM_BASE	0x00000000
64 #define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_DDR_SDRAM_BASE
65 
66 #define CONFIG_CHIP_SELECTS_PER_CTRL	0
67 
68 #define CONFIG_SYS_CLK_FREQ        33000000
69 
70 #define CONFIG_SYS_BOOT_BLOCK		0x00000000	/* boot TLB */
71 
72 #define CONFIG_SYS_MONITOR_BASE		CONFIG_SYS_TEXT_BASE
73 
74 #define CONFIG_ENV_IS_NOWHERE
75 
76 #define CONFIG_HWCONFIG
77 
78 #define CONFIG_SYS_INIT_RAM_ADDR		0x00100000
79 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH	0x0
80 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW	0x00100000
81 /* The assembler doesn't like typecast */
82 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
83 	((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
84 	  CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
85 #define CONFIG_SYS_INIT_RAM_SIZE		0x00004000
86 
87 #define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - \
88 					GENERATED_GBL_DATA_SIZE)
89 #define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
90 
91 #define CONFIG_SYS_MONITOR_LEN		(512 * 1024)
92 #define CONFIG_SYS_MALLOC_LEN		(4 * 1024 * 1024)
93 
94 #define CONFIG_CONS_INDEX	1
95 #define CONFIG_SYS_NS16550_SERIAL
96 #define CONFIG_SYS_NS16550_REG_SIZE	1
97 #define CONFIG_SYS_NS16550_CLK		(get_bus_freq(0))
98 
99 #define CONFIG_SYS_BAUDRATE_TABLE	\
100 	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
101 
102 #define CONFIG_SYS_NS16550_COM1	(CONFIG_SYS_CCSRBAR+0x4500)
103 #define CONFIG_SYS_NS16550_COM2	(CONFIG_SYS_CCSRBAR+0x4600)
104 
105 /*
106  * General PCI
107  * Memory space is mapped 1-1, but I/O space must start from 0.
108  */
109 
110 #ifdef CONFIG_PCI
111 #define CONFIG_PCI_INDIRECT_BRIDGE
112 
113 #define CONFIG_PCI_SCAN_SHOW		/* show pci devices on startup */
114 #endif	/* CONFIG_PCI */
115 
116 #define CONFIG_LBA48
117 
118 /*
119  * Environment
120  */
121 #define CONFIG_ENV_SIZE		0x2000
122 
123 #define CONFIG_LOADS_ECHO		/* echo on for serial download */
124 
125 #define CONFIG_LAST_STAGE_INIT
126 
127 /*
128  * Command line configuration.
129  */
130 #define CONFIG_CMD_IRQ
131 
132 #ifdef CONFIG_PCI
133 #define CONFIG_CMD_PCI
134 #endif
135 
136 /*
137  * Miscellaneous configurable options
138  */
139 #define CONFIG_SYS_LONGHELP			/* undef to save memory	*/
140 #define CONFIG_CMDLINE_EDITING			/* Command-line editing */
141 #define CONFIG_AUTO_COMPLETE			/* add autocompletion support */
142 #define CONFIG_SYS_LOAD_ADDR	0x2000000	/* default load address */
143 #define CONFIG_SYS_CBSIZE	256		/* Console I/O Buffer Size */
144 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
145 #define CONFIG_SYS_MAXARGS	16		/* max number of command args */
146 #define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */
147 
148 /*
149  * For booting Linux, the board info and command line data
150  * have to be in the first 64 MB of memory, since this is
151  * the maximum mapped by the Linux kernel during initialization.
152  */
153 #define CONFIG_SYS_BOOTMAPSZ	(64 << 20)	/* Initial map for Linux*/
154 #define CONFIG_SYS_BOOTM_LEN	(64 << 20)	/* Increase max gunzip size */
155 
156 /*
157  * Environment Configuration
158  */
159 #define CONFIG_ROOTPATH		"/opt/nfsroot"
160 #define CONFIG_BOOTFILE		"uImage"
161 #define CONFIG_UBOOTPATH	"u-boot.bin"	/* U-Boot image on TFTP server*/
162 
163 /* default location for tftp and bootm */
164 #define CONFIG_LOADADDR		1000000
165 
166 #define CONFIG_BAUDRATE	115200
167 
168 #define CONFIG_BOOTCOMMAND		\
169 	"test -n \"$qemu_kernel_addr\" && bootm $qemu_kernel_addr - $fdt_addr_r\0"
170 
171 #endif	/* __QEMU_PPCE500_H */
172