1 /* 2 * (C) Copyright 2010 3 * Ilko Iliev <iliev@ronetix.at> 4 * Asen Dimov <dimov@ronetix.at> 5 * Ronetix GmbH <www.ronetix.at> 6 * 7 * (C) Copyright 2007-2008 8 * Stelian Pop <stelian.pop@leadtechdesign.com> 9 * Lead Tech Design <www.leadtechdesign.com> 10 * 11 * Configuation settings for the PM9G45 board. 12 * 13 * See file CREDITS for list of people who contributed to this 14 * project. 15 * 16 * This program is free software; you can redistribute it and/or 17 * modify it under the terms of the GNU General Public License as 18 * published by the Free Software Foundation; either version 2 of 19 * the License, or (at your option) any later version. 20 * 21 * This program is distributed in the hope that it will be useful, 22 * but WITHOUT ANY WARRANTY; without even the implied warranty of 23 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 24 * GNU General Public License for more details. 25 * 26 * You should have received a copy of the GNU General Public License 27 * along with this program; if not, write to the Free Software 28 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 29 * MA 02111-1307 USA 30 */ 31 32 #ifndef __CONFIG_H 33 #define __CONFIG_H 34 35 #define CONFIG_ARM926EJS 1 /* This is an ARM926EJS Core */ 36 #define CONFIG_PM9G45 1 /* It's an Ronetix PM9G45 */ 37 #define CONFIG_AT91SAM9G45 1 /* It's an Atmel AT91SAM9G45 SoC */ 38 39 /* ARM asynchronous clock */ 40 #define CONFIG_SYS_AT91_MAIN_CLOCK 12000000 /* from 12 MHz crystal */ 41 #define CONFIG_SYS_HZ 1000 42 43 #define CONFIG_ARCH_CPU_INIT 44 45 #define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ 46 #define CONFIG_SETUP_MEMORY_TAGS 1 47 #define CONFIG_INITRD_TAG 1 48 49 #define CONFIG_SKIP_LOWLEVEL_INIT 50 51 /* 52 * Hardware drivers 53 */ 54 #define CONFIG_AT91_GPIO 1 55 #define CONFIG_ATMEL_USART 1 56 #define CONFIG_USART3 1 /* USART 3 is DBGU */ 57 58 #define CONFIG_SYS_USE_NANDFLASH 1 59 60 /* LED */ 61 #define CONFIG_AT91_LED 62 #define CONFIG_RED_LED AT91_PIO_PORTD, 31 /* this is the user1 led */ 63 #define CONFIG_GREEN_LED AT91_PIO_PORTD, 0 /* this is the user2 led */ 64 65 #define CONFIG_BOOTDELAY 3 66 67 /* 68 * BOOTP options 69 */ 70 #define CONFIG_BOOTP_BOOTFILESIZE 1 71 #define CONFIG_BOOTP_BOOTPATH 1 72 #define CONFIG_BOOTP_GATEWAY 1 73 #define CONFIG_BOOTP_HOSTNAME 1 74 75 /* 76 * Command line configuration. 77 */ 78 #include <config_cmd_default.h> 79 #undef CONFIG_CMD_FPGA 80 #undef CONFIG_CMD_IMLS 81 82 #define CONFIG_CMD_PING 1 83 #define CONFIG_CMD_DHCP 1 84 #define CONFIG_CMD_NAND 1 85 #define CONFIG_CMD_USB 1 86 87 #define CONFIG_CMD_JFFS2 1 88 #define CONFIG_JFFS2_CMDLINE 1 89 #define CONFIG_JFFS2_NAND 1 90 #define CONFIG_JFFS2_DEV "nand0" /* NAND dev jffs2 lives on */ 91 #define CONFIG_JFFS2_PART_OFFSET 0 /* start of jffs2 partition */ 92 #define CONFIG_JFFS2_PART_SIZE (256 * 1024 * 1024) /* partition */ 93 94 /* SDRAM */ 95 #define CONFIG_NR_DRAM_BANKS 1 96 #define PHYS_SDRAM 0x70000000 97 #define PHYS_SDRAM_SIZE 0x08000000 /* 128 megs */ 98 99 /* NOR flash, not available */ 100 #define CONFIG_SYS_NO_FLASH 1 101 #undef CONFIG_CMD_FLASH 102 103 /* NAND flash */ 104 #ifdef CONFIG_CMD_NAND 105 #define CONFIG_NAND_MAX_CHIPS 1 106 #define CONFIG_NAND_ATMEL 107 #define CONFIG_SYS_MAX_NAND_DEVICE 1 108 #define CONFIG_SYS_NAND_BASE 0x40000000 109 #define CONFIG_SYS_NAND_DBW_8 1 110 /* our ALE is AD21 */ 111 #define CONFIG_SYS_NAND_MASK_ALE (1 << 21) 112 /* our CLE is AD22 */ 113 #define CONFIG_SYS_NAND_MASK_CLE (1 << 22) 114 #define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIO_PORTC, 14 115 #define CONFIG_SYS_NAND_READY_PIN AT91_PIO_PORTD, 3 116 117 #endif 118 119 /* Ethernet */ 120 #define CONFIG_MACB 1 121 #define CONFIG_RMII 1 122 #define CONFIG_NET_MULTI 1 123 #define CONFIG_NET_RETRY_COUNT 20 124 #define CONFIG_RESET_PHY_R 1 125 126 /* USB */ 127 #define CONFIG_USB_ATMEL 128 #define CONFIG_USB_OHCI_NEW 1 129 #define CONFIG_DOS_PARTITION 1 130 #define CONFIG_SYS_USB_OHCI_CPU_INIT 1 131 #define CONFIG_SYS_USB_OHCI_REGS_BASE 0x00700000 /* _UHP_OHCI_BASE */ 132 #define CONFIG_SYS_USB_OHCI_SLOT_NAME "at91sam9g45" 133 #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2 134 #define CONFIG_USB_STORAGE 1 135 136 /* board specific(not enough SRAM) */ 137 #define CONFIG_AT91SAM9G45_LCD_BASE PHYS_SDRAM + 0xE00000 138 139 #define CONFIG_SYS_LOAD_ADDR PHYS_SDRAM + 0x2000000 /* load addr */ 140 141 #define CONFIG_SYS_MEMTEST_START PHYS_SDRAM 142 #define CONFIG_SYS_MEMTEST_END CONFIG_AT91SAM9G45_LCD_BASE 143 144 /* bootstrap + u-boot + env + linux in nandflash */ 145 #define CONFIG_ENV_IS_IN_NAND 1 146 #define CONFIG_ENV_OFFSET 0x60000 147 #define CONFIG_ENV_OFFSET_REDUND 0x80000 148 #define CONFIG_ENV_SIZE 0x20000 /* 1 sector = 128 kB */ 149 #define CONFIG_BOOTCOMMAND "nand read 0x72000000 0x200000 0x200000; bootm" 150 #define CONFIG_BOOTARGS "fbcon=rotate:3 console=tty0 " \ 151 "console=ttyS0,115200 " \ 152 "root=/dev/mtdblock4 " \ 153 "mtdparts=atmel_nand:128k(bootstrap)ro," \ 154 "256k(uboot)ro,1664k(env)," \ 155 "2M(linux)ro,-(root) rw " \ 156 "rootfstype=jffs2" 157 158 #define CONFIG_BAUDRATE 115200 159 #define CONFIG_SYS_BAUDRATE_TABLE {115200 , 19200, 38400, 57600, 9600 } 160 161 #define CONFIG_SYS_PROMPT "U-Boot> " 162 #define CONFIG_SYS_CBSIZE 256 163 #define CONFIG_SYS_MAXARGS 16 164 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ 165 sizeof(CONFIG_SYS_PROMPT) + 16) 166 #define CONFIG_SYS_LONGHELP 1 167 #define CONFIG_CMDLINE_EDITING 1 168 #define CONFIG_AUTO_COMPLETE 169 #define CONFIG_SYS_HUSH_PARSER 170 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> " 171 172 /* 173 * Size of malloc() pool 174 */ 175 #define CONFIG_SYS_MALLOC_LEN ROUND(3 * CONFIG_ENV_SIZE + 128*1024,\ 176 0x1000) 177 178 #define CONFIG_STACKSIZE (32*1024) /* regular stack */ 179 180 #ifdef CONFIG_USE_IRQ 181 #error CONFIG_USE_IRQ not supported 182 #endif 183 184 #endif 185