1 /* 2 * (C) Copyright 2010 3 * Ilko Iliev <iliev@ronetix.at> 4 * Asen Dimov <dimov@ronetix.at> 5 * Ronetix GmbH <www.ronetix.at> 6 * 7 * (C) Copyright 2007-2008 8 * Stelian Pop <stelian@popies.net> 9 * Lead Tech Design <www.leadtechdesign.com> 10 * 11 * Configuation settings for the PM9G45 board. 12 * 13 * SPDX-License-Identifier: GPL-2.0+ 14 */ 15 16 #ifndef __CONFIG_H 17 #define __CONFIG_H 18 19 /* 20 * SoC must be defined first, before hardware.h is included. 21 * In this case SoC is defined in boards.cfg. 22 */ 23 #include <asm/hardware.h> 24 25 #define CONFIG_SYS_AT91_CPU_NAME "AT91SAM9G45" 26 27 #define CONFIG_MACH_TYPE MACH_TYPE_PM9G45 28 29 /* ARM asynchronous clock */ 30 #define CONFIG_SYS_AT91_MAIN_CLOCK 12000000 /* from 12 MHz crystal */ 31 #define CONFIG_SYS_AT91_SLOW_CLOCK 32768 /* slow clock xtal */ 32 33 #define CONFIG_ARCH_CPU_INIT 34 35 #define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ 36 #define CONFIG_SETUP_MEMORY_TAGS 1 37 #define CONFIG_INITRD_TAG 1 38 39 #define CONFIG_SKIP_LOWLEVEL_INIT 40 41 /* 42 * Hardware drivers 43 */ 44 #define CONFIG_AT91_GPIO 1 45 #define CONFIG_ATMEL_USART 1 46 #define CONFIG_USART_BASE ATMEL_BASE_DBGU 47 #define CONFIG_USART_ID ATMEL_ID_SYS 48 49 #define CONFIG_SYS_USE_NANDFLASH 1 50 51 /* LED */ 52 #define CONFIG_AT91_LED 53 #define CONFIG_RED_LED GPIO_PIN_PD(31) /* this is the user1 led */ 54 #define CONFIG_GREEN_LED GPIO_PIN_PD(0) /* this is the user2 led */ 55 56 57 /* 58 * BOOTP options 59 */ 60 #define CONFIG_BOOTP_BOOTFILESIZE 1 61 62 #define CONFIG_JFFS2_CMDLINE 1 63 #define CONFIG_JFFS2_NAND 1 64 #define CONFIG_JFFS2_DEV "nand0" /* NAND dev jffs2 lives on */ 65 #define CONFIG_JFFS2_PART_OFFSET 0 /* start of jffs2 partition */ 66 #define CONFIG_JFFS2_PART_SIZE (256 * 1024 * 1024) /* partition */ 67 68 /* SDRAM */ 69 #define CONFIG_NR_DRAM_BANKS 1 70 #define PHYS_SDRAM 0x70000000 71 #define PHYS_SDRAM_SIZE 0x08000000 /* 128 megs */ 72 73 /* NAND flash */ 74 #ifdef CONFIG_CMD_NAND 75 #define CONFIG_NAND_ATMEL 76 #define CONFIG_SYS_MAX_NAND_DEVICE 1 77 #define CONFIG_SYS_NAND_BASE 0x40000000 78 #define CONFIG_SYS_NAND_DBW_8 1 79 /* our ALE is AD21 */ 80 #define CONFIG_SYS_NAND_MASK_ALE (1 << 21) 81 /* our CLE is AD22 */ 82 #define CONFIG_SYS_NAND_MASK_CLE (1 << 22) 83 #define CONFIG_SYS_NAND_ENABLE_PIN GPIO_PIN_PC(14) 84 #define CONFIG_SYS_NAND_READY_PIN GPIO_PIN_PD(3) 85 86 #endif 87 88 /* Ethernet */ 89 #define CONFIG_MACB 1 90 #define CONFIG_RMII 1 91 #define CONFIG_NET_RETRY_COUNT 20 92 #define CONFIG_RESET_PHY_R 1 93 94 /* USB */ 95 #define CONFIG_USB_ATMEL 96 #define CONFIG_USB_ATMEL_CLK_SEL_UPLL 97 #define CONFIG_USB_OHCI_NEW 1 98 #define CONFIG_SYS_USB_OHCI_CPU_INIT 1 99 #define CONFIG_SYS_USB_OHCI_REGS_BASE 0x00700000 /* _UHP_OHCI_BASE */ 100 #define CONFIG_SYS_USB_OHCI_SLOT_NAME "at91sam9g45" 101 #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2 102 103 /* board specific(not enough SRAM) */ 104 #define CONFIG_AT91SAM9G45_LCD_BASE PHYS_SDRAM + 0xE00000 105 106 #define CONFIG_SYS_LOAD_ADDR PHYS_SDRAM + 0x2000000 /* load addr */ 107 108 #define CONFIG_SYS_MEMTEST_START PHYS_SDRAM 109 #define CONFIG_SYS_MEMTEST_END CONFIG_AT91SAM9G45_LCD_BASE 110 111 /* bootstrap + u-boot + env + linux in nandflash */ 112 #define CONFIG_ENV_OFFSET 0x60000 113 #define CONFIG_ENV_OFFSET_REDUND 0x80000 114 #define CONFIG_ENV_SIZE 0x20000 /* 1 sector = 128 kB */ 115 #define CONFIG_BOOTCOMMAND "nand read 0x72000000 0x200000 0x200000; bootm" 116 117 /* 118 * Size of malloc() pool 119 */ 120 #define CONFIG_SYS_MALLOC_LEN ROUND(3 * CONFIG_ENV_SIZE + 128*1024,\ 121 0x1000) 122 123 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM 124 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x1000 - \ 125 GENERATED_GBL_DATA_SIZE) 126 127 #endif 128