1b5d289fcSAsen Dimov /* 2b5d289fcSAsen Dimov * (C) Copyright 2010 3b5d289fcSAsen Dimov * Ilko Iliev <iliev@ronetix.at> 4b5d289fcSAsen Dimov * Asen Dimov <dimov@ronetix.at> 5b5d289fcSAsen Dimov * Ronetix GmbH <www.ronetix.at> 6b5d289fcSAsen Dimov * 7b5d289fcSAsen Dimov * (C) Copyright 2007-2008 8c9e798d3SStelian Pop * Stelian Pop <stelian@popies.net> 9b5d289fcSAsen Dimov * Lead Tech Design <www.leadtechdesign.com> 10b5d289fcSAsen Dimov * 11b5d289fcSAsen Dimov * Configuation settings for the PM9G45 board. 12b5d289fcSAsen Dimov * 131a459660SWolfgang Denk * SPDX-License-Identifier: GPL-2.0+ 14b5d289fcSAsen Dimov */ 15b5d289fcSAsen Dimov 16b5d289fcSAsen Dimov #ifndef __CONFIG_H 17b5d289fcSAsen Dimov #define __CONFIG_H 18b5d289fcSAsen Dimov 19eb6e608bSAsen Dimov /* 20eb6e608bSAsen Dimov * SoC must be defined first, before hardware.h is included. 21eb6e608bSAsen Dimov * In this case SoC is defined in boards.cfg. 22eb6e608bSAsen Dimov */ 23eb6e608bSAsen Dimov #include <asm/hardware.h> 24eb6e608bSAsen Dimov 25b5d289fcSAsen Dimov #define CONFIG_PM9G45 1 /* It's an Ronetix PM9G45 */ 26eb6e608bSAsen Dimov #define CONFIG_SYS_AT91_CPU_NAME "AT91SAM9G45" 27b5d289fcSAsen Dimov 28a3e09cc2SAsen Dimov #define MACH_TYPE_PM9G45 2672 29a3e09cc2SAsen Dimov #define CONFIG_MACH_TYPE MACH_TYPE_PM9G45 30a3e09cc2SAsen Dimov 31b5d289fcSAsen Dimov /* ARM asynchronous clock */ 32b5d289fcSAsen Dimov #define CONFIG_SYS_AT91_MAIN_CLOCK 12000000 /* from 12 MHz crystal */ 33eb6e608bSAsen Dimov #define CONFIG_SYS_AT91_SLOW_CLOCK 32768 /* slow clock xtal */ 34b5d289fcSAsen Dimov #define CONFIG_SYS_HZ 1000 35510f794cSAsen Dimov #define CONFIG_SYS_TEXT_BASE 0x73f00000 36b5d289fcSAsen Dimov 37b5d289fcSAsen Dimov #define CONFIG_ARCH_CPU_INIT 38b5d289fcSAsen Dimov 39b5d289fcSAsen Dimov #define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ 40b5d289fcSAsen Dimov #define CONFIG_SETUP_MEMORY_TAGS 1 41b5d289fcSAsen Dimov #define CONFIG_INITRD_TAG 1 42b5d289fcSAsen Dimov 43b5d289fcSAsen Dimov #define CONFIG_SKIP_LOWLEVEL_INIT 44c4df2149SAsen Dimov #define CONFIG_BOARD_EARLY_INIT_F 45b5d289fcSAsen Dimov 46b5d289fcSAsen Dimov /* 47b5d289fcSAsen Dimov * Hardware drivers 48b5d289fcSAsen Dimov */ 49b5d289fcSAsen Dimov #define CONFIG_AT91_GPIO 1 50b5d289fcSAsen Dimov #define CONFIG_ATMEL_USART 1 51eb6e608bSAsen Dimov #define CONFIG_USART_BASE ATMEL_BASE_DBGU 52eb6e608bSAsen Dimov #define CONFIG_USART_ID ATMEL_ID_SYS 53b5d289fcSAsen Dimov 54b5d289fcSAsen Dimov #define CONFIG_SYS_USE_NANDFLASH 1 55b5d289fcSAsen Dimov 56b5d289fcSAsen Dimov /* LED */ 57b5d289fcSAsen Dimov #define CONFIG_AT91_LED 58b5d289fcSAsen Dimov #define CONFIG_RED_LED AT91_PIO_PORTD, 31 /* this is the user1 led */ 59b5d289fcSAsen Dimov #define CONFIG_GREEN_LED AT91_PIO_PORTD, 0 /* this is the user2 led */ 60b5d289fcSAsen Dimov 61b5d289fcSAsen Dimov #define CONFIG_BOOTDELAY 3 62b5d289fcSAsen Dimov 63b5d289fcSAsen Dimov /* 64b5d289fcSAsen Dimov * BOOTP options 65b5d289fcSAsen Dimov */ 66b5d289fcSAsen Dimov #define CONFIG_BOOTP_BOOTFILESIZE 1 67b5d289fcSAsen Dimov #define CONFIG_BOOTP_BOOTPATH 1 68b5d289fcSAsen Dimov #define CONFIG_BOOTP_GATEWAY 1 69b5d289fcSAsen Dimov #define CONFIG_BOOTP_HOSTNAME 1 70b5d289fcSAsen Dimov 71b5d289fcSAsen Dimov /* 72b5d289fcSAsen Dimov * Command line configuration. 73b5d289fcSAsen Dimov */ 74b5d289fcSAsen Dimov #include <config_cmd_default.h> 75b5d289fcSAsen Dimov #undef CONFIG_CMD_FPGA 76b5d289fcSAsen Dimov #undef CONFIG_CMD_IMLS 77b5d289fcSAsen Dimov 7837ee3cccSAsen Dimov #define CONFIG_CMD_CACHE 79b5d289fcSAsen Dimov #define CONFIG_CMD_PING 1 80b5d289fcSAsen Dimov #define CONFIG_CMD_DHCP 1 81b5d289fcSAsen Dimov #define CONFIG_CMD_NAND 1 82b5d289fcSAsen Dimov #define CONFIG_CMD_USB 1 83b5d289fcSAsen Dimov 84b5d289fcSAsen Dimov #define CONFIG_CMD_JFFS2 1 85b5d289fcSAsen Dimov #define CONFIG_JFFS2_CMDLINE 1 86b5d289fcSAsen Dimov #define CONFIG_JFFS2_NAND 1 87b5d289fcSAsen Dimov #define CONFIG_JFFS2_DEV "nand0" /* NAND dev jffs2 lives on */ 88b5d289fcSAsen Dimov #define CONFIG_JFFS2_PART_OFFSET 0 /* start of jffs2 partition */ 89b5d289fcSAsen Dimov #define CONFIG_JFFS2_PART_SIZE (256 * 1024 * 1024) /* partition */ 90b5d289fcSAsen Dimov 91b5d289fcSAsen Dimov /* SDRAM */ 92b5d289fcSAsen Dimov #define CONFIG_NR_DRAM_BANKS 1 93b5d289fcSAsen Dimov #define PHYS_SDRAM 0x70000000 94b5d289fcSAsen Dimov #define PHYS_SDRAM_SIZE 0x08000000 /* 128 megs */ 95b5d289fcSAsen Dimov 96b5d289fcSAsen Dimov /* NOR flash, not available */ 97b5d289fcSAsen Dimov #define CONFIG_SYS_NO_FLASH 1 98b5d289fcSAsen Dimov #undef CONFIG_CMD_FLASH 99b5d289fcSAsen Dimov 100b5d289fcSAsen Dimov /* NAND flash */ 101b5d289fcSAsen Dimov #ifdef CONFIG_CMD_NAND 102b5d289fcSAsen Dimov #define CONFIG_NAND_ATMEL 103b5d289fcSAsen Dimov #define CONFIG_SYS_MAX_NAND_DEVICE 1 104b5d289fcSAsen Dimov #define CONFIG_SYS_NAND_BASE 0x40000000 105b5d289fcSAsen Dimov #define CONFIG_SYS_NAND_DBW_8 1 106b5d289fcSAsen Dimov /* our ALE is AD21 */ 107b5d289fcSAsen Dimov #define CONFIG_SYS_NAND_MASK_ALE (1 << 21) 108b5d289fcSAsen Dimov /* our CLE is AD22 */ 109b5d289fcSAsen Dimov #define CONFIG_SYS_NAND_MASK_CLE (1 << 22) 110b5d289fcSAsen Dimov #define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIO_PORTC, 14 111b5d289fcSAsen Dimov #define CONFIG_SYS_NAND_READY_PIN AT91_PIO_PORTD, 3 112b5d289fcSAsen Dimov 113b5d289fcSAsen Dimov #endif 114b5d289fcSAsen Dimov 115b5d289fcSAsen Dimov /* Ethernet */ 116b5d289fcSAsen Dimov #define CONFIG_MACB 1 117b5d289fcSAsen Dimov #define CONFIG_RMII 1 118b5d289fcSAsen Dimov #define CONFIG_NET_RETRY_COUNT 20 119b5d289fcSAsen Dimov #define CONFIG_RESET_PHY_R 1 120b5d289fcSAsen Dimov 121b5d289fcSAsen Dimov /* USB */ 122b5d289fcSAsen Dimov #define CONFIG_USB_ATMEL 123*dcd2f1a0SBo Shen #define CONFIG_USB_ATMEL_CLK_SEL_UPLL 124b5d289fcSAsen Dimov #define CONFIG_USB_OHCI_NEW 1 125b5d289fcSAsen Dimov #define CONFIG_DOS_PARTITION 1 126b5d289fcSAsen Dimov #define CONFIG_SYS_USB_OHCI_CPU_INIT 1 127b5d289fcSAsen Dimov #define CONFIG_SYS_USB_OHCI_REGS_BASE 0x00700000 /* _UHP_OHCI_BASE */ 128b5d289fcSAsen Dimov #define CONFIG_SYS_USB_OHCI_SLOT_NAME "at91sam9g45" 129b5d289fcSAsen Dimov #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2 130b5d289fcSAsen Dimov #define CONFIG_USB_STORAGE 1 131b5d289fcSAsen Dimov 132b5d289fcSAsen Dimov /* board specific(not enough SRAM) */ 133b5d289fcSAsen Dimov #define CONFIG_AT91SAM9G45_LCD_BASE PHYS_SDRAM + 0xE00000 134b5d289fcSAsen Dimov 135b5d289fcSAsen Dimov #define CONFIG_SYS_LOAD_ADDR PHYS_SDRAM + 0x2000000 /* load addr */ 136b5d289fcSAsen Dimov 137b5d289fcSAsen Dimov #define CONFIG_SYS_MEMTEST_START PHYS_SDRAM 138b5d289fcSAsen Dimov #define CONFIG_SYS_MEMTEST_END CONFIG_AT91SAM9G45_LCD_BASE 139b5d289fcSAsen Dimov 140b5d289fcSAsen Dimov /* bootstrap + u-boot + env + linux in nandflash */ 141b5d289fcSAsen Dimov #define CONFIG_ENV_IS_IN_NAND 1 142b5d289fcSAsen Dimov #define CONFIG_ENV_OFFSET 0x60000 143b5d289fcSAsen Dimov #define CONFIG_ENV_OFFSET_REDUND 0x80000 144b5d289fcSAsen Dimov #define CONFIG_ENV_SIZE 0x20000 /* 1 sector = 128 kB */ 145b5d289fcSAsen Dimov #define CONFIG_BOOTCOMMAND "nand read 0x72000000 0x200000 0x200000; bootm" 146b5d289fcSAsen Dimov #define CONFIG_BOOTARGS "fbcon=rotate:3 console=tty0 " \ 147b5d289fcSAsen Dimov "console=ttyS0,115200 " \ 148b5d289fcSAsen Dimov "root=/dev/mtdblock4 " \ 149b5d289fcSAsen Dimov "mtdparts=atmel_nand:128k(bootstrap)ro," \ 150b5d289fcSAsen Dimov "256k(uboot)ro,1664k(env)," \ 151b5d289fcSAsen Dimov "2M(linux)ro,-(root) rw " \ 152b5d289fcSAsen Dimov "rootfstype=jffs2" 153b5d289fcSAsen Dimov 154b5d289fcSAsen Dimov #define CONFIG_BAUDRATE 115200 155b5d289fcSAsen Dimov 156b5d289fcSAsen Dimov #define CONFIG_SYS_PROMPT "U-Boot> " 157b5d289fcSAsen Dimov #define CONFIG_SYS_CBSIZE 256 158b5d289fcSAsen Dimov #define CONFIG_SYS_MAXARGS 16 159b5d289fcSAsen Dimov #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ 160b5d289fcSAsen Dimov sizeof(CONFIG_SYS_PROMPT) + 16) 161b5d289fcSAsen Dimov #define CONFIG_SYS_LONGHELP 1 162b5d289fcSAsen Dimov #define CONFIG_CMDLINE_EDITING 1 163b5d289fcSAsen Dimov #define CONFIG_AUTO_COMPLETE 164b5d289fcSAsen Dimov #define CONFIG_SYS_HUSH_PARSER 165b5d289fcSAsen Dimov 166b5d289fcSAsen Dimov /* 167b5d289fcSAsen Dimov * Size of malloc() pool 168b5d289fcSAsen Dimov */ 169b5d289fcSAsen Dimov #define CONFIG_SYS_MALLOC_LEN ROUND(3 * CONFIG_ENV_SIZE + 128*1024,\ 170b5d289fcSAsen Dimov 0x1000) 171b5d289fcSAsen Dimov 172510f794cSAsen Dimov #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM 173510f794cSAsen Dimov #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x1000 - \ 174510f794cSAsen Dimov GENERATED_GBL_DATA_SIZE) 175510f794cSAsen Dimov 176b5d289fcSAsen Dimov #endif 177