1b5d289fcSAsen Dimov /* 2b5d289fcSAsen Dimov * (C) Copyright 2010 3b5d289fcSAsen Dimov * Ilko Iliev <iliev@ronetix.at> 4b5d289fcSAsen Dimov * Asen Dimov <dimov@ronetix.at> 5b5d289fcSAsen Dimov * Ronetix GmbH <www.ronetix.at> 6b5d289fcSAsen Dimov * 7b5d289fcSAsen Dimov * (C) Copyright 2007-2008 8b5d289fcSAsen Dimov * Stelian Pop <stelian.pop@leadtechdesign.com> 9b5d289fcSAsen Dimov * Lead Tech Design <www.leadtechdesign.com> 10b5d289fcSAsen Dimov * 11b5d289fcSAsen Dimov * Configuation settings for the PM9G45 board. 12b5d289fcSAsen Dimov * 13b5d289fcSAsen Dimov * See file CREDITS for list of people who contributed to this 14b5d289fcSAsen Dimov * project. 15b5d289fcSAsen Dimov * 16b5d289fcSAsen Dimov * This program is free software; you can redistribute it and/or 17b5d289fcSAsen Dimov * modify it under the terms of the GNU General Public License as 18b5d289fcSAsen Dimov * published by the Free Software Foundation; either version 2 of 19b5d289fcSAsen Dimov * the License, or (at your option) any later version. 20b5d289fcSAsen Dimov * 21b5d289fcSAsen Dimov * This program is distributed in the hope that it will be useful, 22b5d289fcSAsen Dimov * but WITHOUT ANY WARRANTY; without even the implied warranty of 23b5d289fcSAsen Dimov * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 24b5d289fcSAsen Dimov * GNU General Public License for more details. 25b5d289fcSAsen Dimov * 26b5d289fcSAsen Dimov * You should have received a copy of the GNU General Public License 27b5d289fcSAsen Dimov * along with this program; if not, write to the Free Software 28b5d289fcSAsen Dimov * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 29b5d289fcSAsen Dimov * MA 02111-1307 USA 30b5d289fcSAsen Dimov */ 31b5d289fcSAsen Dimov 32b5d289fcSAsen Dimov #ifndef __CONFIG_H 33b5d289fcSAsen Dimov #define __CONFIG_H 34b5d289fcSAsen Dimov 35b5d289fcSAsen Dimov #define CONFIG_ARM926EJS 1 /* This is an ARM926EJS Core */ 36b5d289fcSAsen Dimov #define CONFIG_PM9G45 1 /* It's an Ronetix PM9G45 */ 37b5d289fcSAsen Dimov #define CONFIG_AT91SAM9G45 1 /* It's an Atmel AT91SAM9G45 SoC */ 38b5d289fcSAsen Dimov 39b5d289fcSAsen Dimov /* ARM asynchronous clock */ 40b5d289fcSAsen Dimov #define CONFIG_SYS_AT91_MAIN_CLOCK 12000000 /* from 12 MHz crystal */ 41b5d289fcSAsen Dimov #define CONFIG_SYS_HZ 1000 42*510f794cSAsen Dimov #define CONFIG_SYS_TEXT_BASE 0x73f00000 43*510f794cSAsen Dimov #define CONFIG_AT91FAMILY 44b5d289fcSAsen Dimov 45b5d289fcSAsen Dimov #define CONFIG_ARCH_CPU_INIT 46b5d289fcSAsen Dimov 47b5d289fcSAsen Dimov #define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ 48b5d289fcSAsen Dimov #define CONFIG_SETUP_MEMORY_TAGS 1 49b5d289fcSAsen Dimov #define CONFIG_INITRD_TAG 1 50b5d289fcSAsen Dimov 51b5d289fcSAsen Dimov #define CONFIG_SKIP_LOWLEVEL_INIT 52b5d289fcSAsen Dimov 53b5d289fcSAsen Dimov /* 54b5d289fcSAsen Dimov * Hardware drivers 55b5d289fcSAsen Dimov */ 56b5d289fcSAsen Dimov #define CONFIG_AT91_GPIO 1 57b5d289fcSAsen Dimov #define CONFIG_ATMEL_USART 1 58b5d289fcSAsen Dimov #define CONFIG_USART3 1 /* USART 3 is DBGU */ 59b5d289fcSAsen Dimov 60b5d289fcSAsen Dimov #define CONFIG_SYS_USE_NANDFLASH 1 61b5d289fcSAsen Dimov 62b5d289fcSAsen Dimov /* LED */ 63b5d289fcSAsen Dimov #define CONFIG_AT91_LED 64b5d289fcSAsen Dimov #define CONFIG_RED_LED AT91_PIO_PORTD, 31 /* this is the user1 led */ 65b5d289fcSAsen Dimov #define CONFIG_GREEN_LED AT91_PIO_PORTD, 0 /* this is the user2 led */ 66b5d289fcSAsen Dimov 67b5d289fcSAsen Dimov #define CONFIG_BOOTDELAY 3 68b5d289fcSAsen Dimov 69b5d289fcSAsen Dimov /* 70b5d289fcSAsen Dimov * BOOTP options 71b5d289fcSAsen Dimov */ 72b5d289fcSAsen Dimov #define CONFIG_BOOTP_BOOTFILESIZE 1 73b5d289fcSAsen Dimov #define CONFIG_BOOTP_BOOTPATH 1 74b5d289fcSAsen Dimov #define CONFIG_BOOTP_GATEWAY 1 75b5d289fcSAsen Dimov #define CONFIG_BOOTP_HOSTNAME 1 76b5d289fcSAsen Dimov 77b5d289fcSAsen Dimov /* 78b5d289fcSAsen Dimov * Command line configuration. 79b5d289fcSAsen Dimov */ 80b5d289fcSAsen Dimov #include <config_cmd_default.h> 81b5d289fcSAsen Dimov #undef CONFIG_CMD_FPGA 82b5d289fcSAsen Dimov #undef CONFIG_CMD_IMLS 83b5d289fcSAsen Dimov 84b5d289fcSAsen Dimov #define CONFIG_CMD_PING 1 85b5d289fcSAsen Dimov #define CONFIG_CMD_DHCP 1 86b5d289fcSAsen Dimov #define CONFIG_CMD_NAND 1 87b5d289fcSAsen Dimov #define CONFIG_CMD_USB 1 88b5d289fcSAsen Dimov 89b5d289fcSAsen Dimov #define CONFIG_CMD_JFFS2 1 90b5d289fcSAsen Dimov #define CONFIG_JFFS2_CMDLINE 1 91b5d289fcSAsen Dimov #define CONFIG_JFFS2_NAND 1 92b5d289fcSAsen Dimov #define CONFIG_JFFS2_DEV "nand0" /* NAND dev jffs2 lives on */ 93b5d289fcSAsen Dimov #define CONFIG_JFFS2_PART_OFFSET 0 /* start of jffs2 partition */ 94b5d289fcSAsen Dimov #define CONFIG_JFFS2_PART_SIZE (256 * 1024 * 1024) /* partition */ 95b5d289fcSAsen Dimov 96b5d289fcSAsen Dimov /* SDRAM */ 97b5d289fcSAsen Dimov #define CONFIG_NR_DRAM_BANKS 1 98b5d289fcSAsen Dimov #define PHYS_SDRAM 0x70000000 99b5d289fcSAsen Dimov #define PHYS_SDRAM_SIZE 0x08000000 /* 128 megs */ 100b5d289fcSAsen Dimov 101b5d289fcSAsen Dimov /* NOR flash, not available */ 102b5d289fcSAsen Dimov #define CONFIG_SYS_NO_FLASH 1 103b5d289fcSAsen Dimov #undef CONFIG_CMD_FLASH 104b5d289fcSAsen Dimov 105b5d289fcSAsen Dimov /* NAND flash */ 106b5d289fcSAsen Dimov #ifdef CONFIG_CMD_NAND 107b5d289fcSAsen Dimov #define CONFIG_NAND_MAX_CHIPS 1 108b5d289fcSAsen Dimov #define CONFIG_NAND_ATMEL 109b5d289fcSAsen Dimov #define CONFIG_SYS_MAX_NAND_DEVICE 1 110b5d289fcSAsen Dimov #define CONFIG_SYS_NAND_BASE 0x40000000 111b5d289fcSAsen Dimov #define CONFIG_SYS_NAND_DBW_8 1 112b5d289fcSAsen Dimov /* our ALE is AD21 */ 113b5d289fcSAsen Dimov #define CONFIG_SYS_NAND_MASK_ALE (1 << 21) 114b5d289fcSAsen Dimov /* our CLE is AD22 */ 115b5d289fcSAsen Dimov #define CONFIG_SYS_NAND_MASK_CLE (1 << 22) 116b5d289fcSAsen Dimov #define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIO_PORTC, 14 117b5d289fcSAsen Dimov #define CONFIG_SYS_NAND_READY_PIN AT91_PIO_PORTD, 3 118b5d289fcSAsen Dimov 119b5d289fcSAsen Dimov #endif 120b5d289fcSAsen Dimov 121b5d289fcSAsen Dimov /* Ethernet */ 122b5d289fcSAsen Dimov #define CONFIG_MACB 1 123b5d289fcSAsen Dimov #define CONFIG_RMII 1 124b5d289fcSAsen Dimov #define CONFIG_NET_MULTI 1 125b5d289fcSAsen Dimov #define CONFIG_NET_RETRY_COUNT 20 126b5d289fcSAsen Dimov #define CONFIG_RESET_PHY_R 1 127b5d289fcSAsen Dimov 128b5d289fcSAsen Dimov /* USB */ 129b5d289fcSAsen Dimov #define CONFIG_USB_ATMEL 130b5d289fcSAsen Dimov #define CONFIG_USB_OHCI_NEW 1 131b5d289fcSAsen Dimov #define CONFIG_DOS_PARTITION 1 132b5d289fcSAsen Dimov #define CONFIG_SYS_USB_OHCI_CPU_INIT 1 133b5d289fcSAsen Dimov #define CONFIG_SYS_USB_OHCI_REGS_BASE 0x00700000 /* _UHP_OHCI_BASE */ 134b5d289fcSAsen Dimov #define CONFIG_SYS_USB_OHCI_SLOT_NAME "at91sam9g45" 135b5d289fcSAsen Dimov #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2 136b5d289fcSAsen Dimov #define CONFIG_USB_STORAGE 1 137b5d289fcSAsen Dimov 138b5d289fcSAsen Dimov /* board specific(not enough SRAM) */ 139b5d289fcSAsen Dimov #define CONFIG_AT91SAM9G45_LCD_BASE PHYS_SDRAM + 0xE00000 140b5d289fcSAsen Dimov 141b5d289fcSAsen Dimov #define CONFIG_SYS_LOAD_ADDR PHYS_SDRAM + 0x2000000 /* load addr */ 142b5d289fcSAsen Dimov 143b5d289fcSAsen Dimov #define CONFIG_SYS_MEMTEST_START PHYS_SDRAM 144b5d289fcSAsen Dimov #define CONFIG_SYS_MEMTEST_END CONFIG_AT91SAM9G45_LCD_BASE 145b5d289fcSAsen Dimov 146b5d289fcSAsen Dimov /* bootstrap + u-boot + env + linux in nandflash */ 147b5d289fcSAsen Dimov #define CONFIG_ENV_IS_IN_NAND 1 148b5d289fcSAsen Dimov #define CONFIG_ENV_OFFSET 0x60000 149b5d289fcSAsen Dimov #define CONFIG_ENV_OFFSET_REDUND 0x80000 150b5d289fcSAsen Dimov #define CONFIG_ENV_SIZE 0x20000 /* 1 sector = 128 kB */ 151b5d289fcSAsen Dimov #define CONFIG_BOOTCOMMAND "nand read 0x72000000 0x200000 0x200000; bootm" 152b5d289fcSAsen Dimov #define CONFIG_BOOTARGS "fbcon=rotate:3 console=tty0 " \ 153b5d289fcSAsen Dimov "console=ttyS0,115200 " \ 154b5d289fcSAsen Dimov "root=/dev/mtdblock4 " \ 155b5d289fcSAsen Dimov "mtdparts=atmel_nand:128k(bootstrap)ro," \ 156b5d289fcSAsen Dimov "256k(uboot)ro,1664k(env)," \ 157b5d289fcSAsen Dimov "2M(linux)ro,-(root) rw " \ 158b5d289fcSAsen Dimov "rootfstype=jffs2" 159b5d289fcSAsen Dimov 160b5d289fcSAsen Dimov #define CONFIG_BAUDRATE 115200 161b5d289fcSAsen Dimov #define CONFIG_SYS_BAUDRATE_TABLE {115200 , 19200, 38400, 57600, 9600 } 162b5d289fcSAsen Dimov 163b5d289fcSAsen Dimov #define CONFIG_SYS_PROMPT "U-Boot> " 164b5d289fcSAsen Dimov #define CONFIG_SYS_CBSIZE 256 165b5d289fcSAsen Dimov #define CONFIG_SYS_MAXARGS 16 166b5d289fcSAsen Dimov #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ 167b5d289fcSAsen Dimov sizeof(CONFIG_SYS_PROMPT) + 16) 168b5d289fcSAsen Dimov #define CONFIG_SYS_LONGHELP 1 169b5d289fcSAsen Dimov #define CONFIG_CMDLINE_EDITING 1 170b5d289fcSAsen Dimov #define CONFIG_AUTO_COMPLETE 171b5d289fcSAsen Dimov #define CONFIG_SYS_HUSH_PARSER 172b5d289fcSAsen Dimov #define CONFIG_SYS_PROMPT_HUSH_PS2 "> " 173b5d289fcSAsen Dimov 174b5d289fcSAsen Dimov /* 175b5d289fcSAsen Dimov * Size of malloc() pool 176b5d289fcSAsen Dimov */ 177b5d289fcSAsen Dimov #define CONFIG_SYS_MALLOC_LEN ROUND(3 * CONFIG_ENV_SIZE + 128*1024,\ 178b5d289fcSAsen Dimov 0x1000) 179b5d289fcSAsen Dimov 180*510f794cSAsen Dimov #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM 181*510f794cSAsen Dimov #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x1000 - \ 182*510f794cSAsen Dimov GENERATED_GBL_DATA_SIZE) 183*510f794cSAsen Dimov 184b5d289fcSAsen Dimov #define CONFIG_STACKSIZE (32*1024) /* regular stack */ 185b5d289fcSAsen Dimov 186b5d289fcSAsen Dimov #ifdef CONFIG_USE_IRQ 187b5d289fcSAsen Dimov #error CONFIG_USE_IRQ not supported 188b5d289fcSAsen Dimov #endif 189b5d289fcSAsen Dimov 190b5d289fcSAsen Dimov #endif 191