1 /* 2 * (C) Copyright 2007-2008 3 * Stelian Pop <stelian@popies.net> 4 * Lead Tech Design <www.leadtechdesign.com> 5 * Ilko Iliev <www.ronetix.at> 6 * 7 * Configuation settings for the RONETIX PM9263 board. 8 * 9 * SPDX-License-Identifier: GPL-2.0+ 10 */ 11 12 #ifndef __CONFIG_H 13 #define __CONFIG_H 14 15 /* 16 * SoC must be defined first, before hardware.h is included. 17 * In this case SoC is defined in boards.cfg. 18 */ 19 #include <asm/hardware.h> 20 21 /* ARM asynchronous clock */ 22 23 #define MASTER_PLL_DIV 6 24 #define MASTER_PLL_MUL 65 25 #define MAIN_PLL_DIV 2 /* 2 or 4 */ 26 #define CONFIG_SYS_AT91_MAIN_CLOCK 18432000 27 #define CONFIG_SYS_AT91_SLOW_CLOCK 32768 /* slow clock xtal */ 28 29 #define CONFIG_SYS_AT91_CPU_NAME "AT91SAM9263" 30 #define CONFIG_ARCH_CPU_INIT 31 32 #define CONFIG_MACH_TYPE MACH_TYPE_PM9263 33 34 /* clocks */ 35 #define CONFIG_SYS_MOR_VAL \ 36 (AT91_PMC_MOR_MOSCEN | \ 37 (255 << 8)) /* Main Oscillator Start-up Time */ 38 #define CONFIG_SYS_PLLAR_VAL \ 39 (AT91_PMC_PLLAR_29 | /* Bit 29 must be 1 when prog */ \ 40 AT91_PMC_PLLXR_OUT(3) | \ 41 AT91_PMC_PLLXR_PLLCOUNT(0x3f) | /* PLL Counter */\ 42 (2 << 28) | /* PLL Clock Frequency Range */ \ 43 ((MASTER_PLL_MUL - 1) << 16) | (MASTER_PLL_DIV)) 44 45 #if (MAIN_PLL_DIV == 2) 46 /* PCK/2 = MCK Master Clock from PLLA */ 47 #define CONFIG_SYS_MCKR1_VAL \ 48 (AT91_PMC_MCKR_CSS_SLOW | \ 49 AT91_PMC_MCKR_PRES_1 | \ 50 AT91_PMC_MCKR_MDIV_2) 51 /* PCK/2 = MCK Master Clock from PLLA */ 52 #define CONFIG_SYS_MCKR2_VAL \ 53 (AT91_PMC_MCKR_CSS_PLLA | \ 54 AT91_PMC_MCKR_PRES_1 | \ 55 AT91_PMC_MCKR_MDIV_2) 56 #else 57 /* PCK/4 = MCK Master Clock from PLLA */ 58 #define CONFIG_SYS_MCKR1_VAL \ 59 (AT91_PMC_MCKR_CSS_SLOW | \ 60 AT91_PMC_MCKR_PRES_1 | \ 61 AT91_PMC_MCKR_MDIV_4) 62 /* PCK/4 = MCK Master Clock from PLLA */ 63 #define CONFIG_SYS_MCKR2_VAL \ 64 (AT91_PMC_MCKR_CSS_PLLA | \ 65 AT91_PMC_MCKR_PRES_1 | \ 66 AT91_PMC_MCKR_MDIV_4) 67 #endif 68 /* define PDC[31:16] as DATA[31:16] */ 69 #define CONFIG_SYS_PIOD_PDR_VAL1 0xFFFF0000 70 /* no pull-up for D[31:16] */ 71 #define CONFIG_SYS_PIOD_PPUDR_VAL 0xFFFF0000 72 /* EBI0_CSA, CS1 SDRAM, CS3 NAND Flash, 3.3V memories */ 73 #define CONFIG_SYS_MATRIX_EBI0CSA_VAL \ 74 (AT91_MATRIX_CSA_DBPUC | AT91_MATRIX_CSA_VDDIOMSEL_3_3V | \ 75 AT91_MATRIX_CSA_EBI_CS1A) 76 77 /* SDRAM */ 78 /* SDRAMC_MR Mode register */ 79 #define CONFIG_SYS_SDRC_MR_VAL1 0 80 /* SDRAMC_TR - Refresh Timer register */ 81 #define CONFIG_SYS_SDRC_TR_VAL1 0x3AA 82 /* SDRAMC_CR - Configuration register*/ 83 #define CONFIG_SYS_SDRC_CR_VAL \ 84 (AT91_SDRAMC_NC_9 | \ 85 AT91_SDRAMC_NR_13 | \ 86 AT91_SDRAMC_NB_4 | \ 87 AT91_SDRAMC_CAS_2 | \ 88 AT91_SDRAMC_DBW_32 | \ 89 (2 << 8) | /* tWR - Write Recovery Delay */ \ 90 (7 << 12) | /* tRC - Row Cycle Delay */ \ 91 (2 << 16) | /* tRP - Row Precharge Delay */ \ 92 (2 << 20) | /* tRCD - Row to Column Delay */ \ 93 (5 << 24) | /* tRAS - Active to Precharge Delay */ \ 94 (8 << 28)) /* tXSR - Exit Self Refresh to Active Delay */ 95 96 /* Memory Device Register -> SDRAM */ 97 #define CONFIG_SYS_SDRC_MDR_VAL AT91_SDRAMC_MD_SDRAM 98 #define CONFIG_SYS_SDRC_MR_VAL2 AT91_SDRAMC_MODE_PRECHARGE 99 #define CONFIG_SYS_SDRAM_VAL1 0 /* SDRAM_BASE */ 100 #define CONFIG_SYS_SDRC_MR_VAL3 AT91_SDRAMC_MODE_REFRESH 101 #define CONFIG_SYS_SDRAM_VAL2 0 /* SDRAM_BASE */ 102 #define CONFIG_SYS_SDRAM_VAL3 0 /* SDRAM_BASE */ 103 #define CONFIG_SYS_SDRAM_VAL4 0 /* SDRAM_BASE */ 104 #define CONFIG_SYS_SDRAM_VAL5 0 /* SDRAM_BASE */ 105 #define CONFIG_SYS_SDRAM_VAL6 0 /* SDRAM_BASE */ 106 #define CONFIG_SYS_SDRAM_VAL7 0 /* SDRAM_BASE */ 107 #define CONFIG_SYS_SDRAM_VAL8 0 /* SDRAM_BASE */ 108 #define CONFIG_SYS_SDRAM_VAL9 0 /* SDRAM_BASE */ 109 #define CONFIG_SYS_SDRC_MR_VAL4 AT91_SDRAMC_MODE_LMR 110 #define CONFIG_SYS_SDRAM_VAL10 0 /* SDRAM_BASE */ 111 #define CONFIG_SYS_SDRC_MR_VAL5 AT91_SDRAMC_MODE_NORMAL 112 #define CONFIG_SYS_SDRAM_VAL11 0 /* SDRAM_BASE */ 113 #define CONFIG_SYS_SDRC_TR_VAL2 1200 /* SDRAM_TR */ 114 #define CONFIG_SYS_SDRAM_VAL12 0 /* SDRAM_BASE */ 115 116 /* setup SMC0, CS0 (NOR Flash) - 16-bit, 15 WS */ 117 #define CONFIG_SYS_SMC0_SETUP0_VAL \ 118 (AT91_SMC_SETUP_NWE(10) | AT91_SMC_SETUP_NCS_WR(10) | \ 119 AT91_SMC_SETUP_NRD(10) | AT91_SMC_SETUP_NCS_RD(10)) 120 #define CONFIG_SYS_SMC0_PULSE0_VAL \ 121 (AT91_SMC_PULSE_NWE(11) | AT91_SMC_PULSE_NCS_WR(11) | \ 122 AT91_SMC_PULSE_NRD(11) | AT91_SMC_PULSE_NCS_RD(11)) 123 #define CONFIG_SYS_SMC0_CYCLE0_VAL \ 124 (AT91_SMC_CYCLE_NWE(22) | AT91_SMC_CYCLE_NRD(22)) 125 #define CONFIG_SYS_SMC0_MODE0_VAL \ 126 (AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE | \ 127 AT91_SMC_MODE_DBW_16 | \ 128 AT91_SMC_MODE_TDF | \ 129 AT91_SMC_MODE_TDF_CYCLE(6)) 130 131 /* user reset enable */ 132 #define CONFIG_SYS_RSTC_RMR_VAL \ 133 (AT91_RSTC_KEY | \ 134 AT91_RSTC_CR_PROCRST | \ 135 AT91_RSTC_MR_ERSTL(1) | \ 136 AT91_RSTC_MR_ERSTL(2)) 137 138 /* Disable Watchdog */ 139 #define CONFIG_SYS_WDTC_WDMR_VAL \ 140 (AT91_WDT_MR_WDIDLEHLT | AT91_WDT_MR_WDDBGHLT | \ 141 AT91_WDT_MR_WDV(0xfff) | \ 142 AT91_WDT_MR_WDDIS | \ 143 AT91_WDT_MR_WDD(0xfff)) 144 145 #define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ 146 #define CONFIG_SETUP_MEMORY_TAGS 1 147 #define CONFIG_INITRD_TAG 1 148 149 #undef CONFIG_SKIP_LOWLEVEL_INIT 150 #define CONFIG_USER_LOWLEVEL_INIT 1 151 152 /* 153 * Hardware drivers 154 */ 155 /* LCD */ 156 #define LCD_BPP LCD_COLOR8 157 #define CONFIG_LCD_LOGO 1 158 #undef LCD_TEST_PATTERN 159 #define CONFIG_LCD_INFO 1 160 #define CONFIG_LCD_INFO_BELOW_LOGO 1 161 #define CONFIG_ATMEL_LCD 1 162 #define CONFIG_ATMEL_LCD_BGR555 1 163 164 #define CONFIG_LCD_IN_PSRAM 1 165 166 /* 167 * BOOTP options 168 */ 169 #define CONFIG_BOOTP_BOOTFILESIZE 1 170 171 /* SDRAM */ 172 #define CONFIG_NR_DRAM_BANKS 1 173 #define PHYS_SDRAM 0x20000000 174 #define PHYS_SDRAM_SIZE 0x04000000 /* 64 megs */ 175 176 /* NOR flash, if populated */ 177 #define CONFIG_SYS_FLASH_CFI 1 178 #define CONFIG_FLASH_CFI_DRIVER 1 179 #define PHYS_FLASH_1 0x10000000 180 #define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1 181 #define CONFIG_SYS_MAX_FLASH_SECT 256 182 #define CONFIG_SYS_MAX_FLASH_BANKS 1 183 184 /* NAND flash */ 185 #ifdef CONFIG_CMD_NAND 186 #define CONFIG_NAND_ATMEL 187 #define CONFIG_SYS_MAX_NAND_DEVICE 1 188 #define CONFIG_SYS_NAND_BASE 0x40000000 189 #define CONFIG_SYS_NAND_DBW_8 1 190 /* our ALE is AD21 */ 191 #define CONFIG_SYS_NAND_MASK_ALE (1 << 21) 192 /* our CLE is AD22 */ 193 #define CONFIG_SYS_NAND_MASK_CLE (1 << 22) 194 #define CONFIG_SYS_NAND_ENABLE_PIN GPIO_PIN_PD(15) 195 #define CONFIG_SYS_NAND_READY_PIN GPIO_PIN_PB(30) 196 197 #endif 198 199 #define CONFIG_JFFS2_CMDLINE 1 200 #define CONFIG_JFFS2_NAND 1 201 #define CONFIG_JFFS2_DEV "nand0" /* NAND device jffs2 lives on */ 202 #define CONFIG_JFFS2_PART_OFFSET 0 /* start of jffs2 partition */ 203 #define CONFIG_JFFS2_PART_SIZE (256 * 1024 * 1024) /* partition size*/ 204 205 /* PSRAM */ 206 #define PHYS_PSRAM 0x70000000 207 #define PHYS_PSRAM_SIZE 0x00400000 /* 4MB */ 208 /* Slave EBI1, PSRAM connected */ 209 #define CONFIG_PSRAM_SCFG (AT91_MATRIX_SCFG_ARBT_FIXED_PRIORITY | \ 210 AT91_MATRIX_SCFG_FIXED_DEFMSTR(5) | \ 211 AT91_MATRIX_SCFG_DEFMSTR_TYPE_FIXED | \ 212 AT91_MATRIX_SCFG_SLOT_CYCLE(255)) 213 214 /* Ethernet */ 215 #define CONFIG_MACB 1 216 #define CONFIG_RMII 1 217 #define CONFIG_NET_RETRY_COUNT 20 218 #define CONFIG_RESET_PHY_R 1 219 220 /* USB */ 221 #define CONFIG_USB_ATMEL 222 #define CONFIG_USB_ATMEL_CLK_SEL_PLLB 223 #define CONFIG_USB_OHCI_NEW 1 224 #define CONFIG_SYS_USB_OHCI_CPU_INIT 1 225 #define CONFIG_SYS_USB_OHCI_REGS_BASE 0x00a00000 /* AT91SAM9263_UHP_BASE */ 226 #define CONFIG_SYS_USB_OHCI_SLOT_NAME "at91sam9263" 227 #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2 228 229 #define CONFIG_SYS_LOAD_ADDR 0x22000000 /* load address */ 230 231 #define CONFIG_SYS_MEMTEST_START PHYS_SDRAM 232 #define CONFIG_SYS_MEMTEST_END 0x23e00000 233 234 #define CONFIG_SYS_USE_FLASH 1 235 #undef CONFIG_SYS_USE_DATAFLASH 236 #undef CONFIG_SYS_USE_NANDFLASH 237 238 #ifdef CONFIG_SYS_USE_DATAFLASH 239 240 /* bootstrap + u-boot + env + linux in dataflash on CS0 */ 241 #define CONFIG_ENV_OFFSET 0x4200 242 #define CONFIG_ENV_SIZE 0x4200 243 #define CONFIG_ENV_SECT_SIZE 0x210 244 #define CONFIG_ENV_SPI_MAX_HZ 15000000 245 #define CONFIG_BOOTCOMMAND "sf probe 0; " \ 246 "sf read 0x22000000 0x84000 0x294000; " \ 247 "bootm 0x22000000" 248 249 #elif defined(CONFIG_SYS_USE_NANDFLASH) /* CFG_USE_NANDFLASH */ 250 251 /* bootstrap + u-boot + env + linux in nandflash */ 252 #define CONFIG_ENV_OFFSET 0x60000 253 #define CONFIG_ENV_OFFSET_REDUND 0x80000 254 #define CONFIG_ENV_SIZE 0x20000 /* 1 sector = 128 kB */ 255 #define CONFIG_BOOTCOMMAND "nand read 0x22000000 0xA0000 0x200000; bootm" 256 257 #elif defined(CONFIG_SYS_USE_FLASH) /* CFG_USE_FLASH */ 258 259 #define CONFIG_ENV_OFFSET 0x40000 260 #define CONFIG_ENV_SECT_SIZE 0x10000 261 #define CONFIG_ENV_SIZE 0x10000 262 #define CONFIG_ENV_OVERWRITE 1 263 264 /* JFFS Partition offset set */ 265 #define CONFIG_SYS_JFFS2_FIRST_BANK 0 266 #define CONFIG_SYS_JFFS2_NUM_BANKS 1 267 268 /* 512k reserved for u-boot */ 269 #define CONFIG_SYS_JFFS2_FIRST_SECTOR 11 270 271 #define CONFIG_BOOTCOMMAND "run flashboot" 272 #define CONFIG_ROOTPATH "/ronetix/rootfs" 273 274 #define CONFIG_CON_ROT "fbcon=rotate:3 " 275 276 #define CONFIG_EXTRA_ENV_SETTINGS \ 277 "mtdids=" CONFIG_MTDIDS_DEFAULT "\0" \ 278 "mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \ 279 "partition=nand0,0\0" \ 280 "ramargs=setenv bootargs $(bootargs) $(mtdparts)\0" \ 281 "nfsargs=setenv bootargs root=/dev/nfs rw " \ 282 CONFIG_CON_ROT \ 283 "nfsroot=$(serverip):$(rootpath) $(mtdparts)\0" \ 284 "addip=setenv bootargs $(bootargs) " \ 285 "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask)"\ 286 ":$(hostname):eth0:off\0" \ 287 "ramboot=tftpboot 0x22000000 vmImage;" \ 288 "run ramargs;run addip;bootm 22000000\0" \ 289 "nfsboot=tftpboot 0x22000000 vmImage;" \ 290 "run nfsargs;run addip;bootm 22000000\0" \ 291 "flashboot=run ramargs;run addip;bootm 0x10050000\0" \ 292 "" 293 294 #else 295 #error "Undefined memory device" 296 #endif 297 298 /* 299 * Size of malloc() pool 300 */ 301 #define CONFIG_SYS_MALLOC_LEN ROUND(3 * CONFIG_ENV_SIZE + 128 * 1024, 0x1000) 302 303 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM 304 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 16 * 1024 - \ 305 GENERATED_GBL_DATA_SIZE) 306 307 #endif 308