1 /* 2 * (C) Copyright 2007-2008 3 * Stelian Pop <stelian.pop@leadtechdesign.com> 4 * Lead Tech Design <www.leadtechdesign.com> 5 * Ilko Iliev <www.ronetix.at> 6 * 7 * Configuation settings for the RONETIX PM9263 board. 8 * 9 * See file CREDITS for list of people who contributed to this 10 * project. 11 * 12 * This program is free software; you can redistribute it and/or 13 * modify it under the terms of the GNU General Public License as 14 * published by the Free Software Foundation; either version 2 of 15 * the License, or (at your option) any later version. 16 * 17 * This program is distributed in the hope that it will be useful, 18 * but WITHOUT ANY WARRANTY; without even the implied warranty of 19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 20 * GNU General Public License for more details. 21 * 22 * You should have received a copy of the GNU General Public License 23 * along with this program; if not, write to the Free Software 24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 25 * MA 02111-1307 USA 26 */ 27 28 #ifndef __CONFIG_H 29 #define __CONFIG_H 30 31 #define CONFIG_AT91_LEGACY 32 33 /* ARM asynchronous clock */ 34 #define CONFIG_DISPLAY_CPUINFO 35 #define CONFIG_DISPLAY_BOARDINFO 36 37 #define MASTER_PLL_DIV 6 38 #define MASTER_PLL_MUL 65 39 #define MAIN_PLL_DIV 2 /* 2 or 4 */ 40 #define CONFIG_SYS_AT91_MAIN_CLOCK 18432000 41 42 #define CONFIG_SYS_HZ 1000 43 44 #define CONFIG_ARM926EJS 1 /* This is an ARM926EJS Core */ 45 #define CONFIG_AT91SAM9263 1 /* It's an Atmel AT91SAM9263 SoC*/ 46 #define CONFIG_PM9263 1 /* on a Ronetix PM9263 Board */ 47 #define CONFIG_ARCH_CPU_INIT 48 #undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */ 49 50 /* clocks */ 51 #define CONFIG_SYS_MOR_VAL \ 52 (AT91_PMC_MOSCEN | \ 53 (255 << 8)) /* Main Oscillator Start-up Time */ 54 #define CONFIG_SYS_PLLAR_VAL \ 55 (AT91_PMC_PLLA_WR_ERRATA | /* Bit 29 must be 1 when prog */ \ 56 AT91_PMC_OUT | \ 57 AT91_PMC_PLLCOUNT | /* PLL Counter */ \ 58 (2 << 28) | /* PLL Clock Frequency Range */ \ 59 ((MASTER_PLL_MUL - 1) << 16) | (MASTER_PLL_DIV)) 60 61 #if (MAIN_PLL_DIV == 2) 62 /* PCK/2 = MCK Master Clock from PLLA */ 63 #define CONFIG_SYS_MCKR1_VAL \ 64 (AT91_PMC_CSS_SLOW | \ 65 AT91_PMC_PRES_1 | \ 66 AT91SAM9_PMC_MDIV_2 | \ 67 AT91_PMC_PDIV_1) 68 /* PCK/2 = MCK Master Clock from PLLA */ 69 #define CONFIG_SYS_MCKR2_VAL \ 70 (AT91_PMC_CSS_PLLA | \ 71 AT91_PMC_PRES_1 | \ 72 AT91SAM9_PMC_MDIV_2 | \ 73 AT91_PMC_PDIV_1) 74 #else 75 /* PCK/4 = MCK Master Clock from PLLA */ 76 #define CONFIG_SYS_MCKR1_VAL \ 77 (AT91_PMC_CSS_SLOW | \ 78 AT91_PMC_PRES_1 | \ 79 AT91RM9200_PMC_MDIV_3 | \ 80 AT91_PMC_PDIV_1) 81 /* PCK/4 = MCK Master Clock from PLLA */ 82 #define CONFIG_SYS_MCKR2_VAL \ 83 (AT91_PMC_CSS_PLLA | \ 84 AT91_PMC_PRES_1 | \ 85 AT91RM9200_PMC_MDIV_3 | \ 86 AT91_PMC_PDIV_1) 87 #endif 88 /* define PDC[31:16] as DATA[31:16] */ 89 #define CONFIG_SYS_PIOD_PDR_VAL1 0xFFFF0000 90 /* no pull-up for D[31:16] */ 91 #define CONFIG_SYS_PIOD_PPUDR_VAL 0xFFFF0000 92 /* EBI0_CSA, CS1 SDRAM, CS3 NAND Flash, 3.3V memories */ 93 #define CONFIG_SYS_MATRIX_EBI0CSA_VAL \ 94 (AT91_MATRIX_EBI0_DBPUC | AT91_MATRIX_EBI0_VDDIOMSEL_3_3V | \ 95 AT91_MATRIX_EBI0_CS1A_SDRAMC) 96 97 /* SDRAM */ 98 /* SDRAMC_MR Mode register */ 99 #define CONFIG_SYS_SDRC_MR_VAL1 0 100 /* SDRAMC_TR - Refresh Timer register */ 101 #define CONFIG_SYS_SDRC_TR_VAL1 0x3AA 102 /* SDRAMC_CR - Configuration register*/ 103 #define CONFIG_SYS_SDRC_CR_VAL \ 104 (AT91_SDRAMC_NC_9 | \ 105 AT91_SDRAMC_NR_13 | \ 106 AT91_SDRAMC_NB_4 | \ 107 AT91_SDRAMC_CAS_2 | \ 108 AT91_SDRAMC_DBW_32 | \ 109 (2 << 8) | /* tWR - Write Recovery Delay */ \ 110 (7 << 12) | /* tRC - Row Cycle Delay */ \ 111 (2 << 16) | /* tRP - Row Precharge Delay */ \ 112 (2 << 20) | /* tRCD - Row to Column Delay */ \ 113 (5 << 24) | /* tRAS - Active to Precharge Delay */ \ 114 (8 << 28)) /* tXSR - Exit Self Refresh to Active Delay */ 115 116 /* Memory Device Register -> SDRAM */ 117 #define CONFIG_SYS_SDRC_MDR_VAL AT91_SDRAMC_MD_SDRAM 118 #define CONFIG_SYS_SDRC_MR_VAL2 AT91_SDRAMC_MODE_PRECHARGE 119 #define CONFIG_SYS_SDRAM_VAL1 0 /* SDRAM_BASE */ 120 #define CONFIG_SYS_SDRC_MR_VAL3 AT91_SDRAMC_MODE_REFRESH 121 #define CONFIG_SYS_SDRAM_VAL2 0 /* SDRAM_BASE */ 122 #define CONFIG_SYS_SDRAM_VAL3 0 /* SDRAM_BASE */ 123 #define CONFIG_SYS_SDRAM_VAL4 0 /* SDRAM_BASE */ 124 #define CONFIG_SYS_SDRAM_VAL5 0 /* SDRAM_BASE */ 125 #define CONFIG_SYS_SDRAM_VAL6 0 /* SDRAM_BASE */ 126 #define CONFIG_SYS_SDRAM_VAL7 0 /* SDRAM_BASE */ 127 #define CONFIG_SYS_SDRAM_VAL8 0 /* SDRAM_BASE */ 128 #define CONFIG_SYS_SDRAM_VAL9 0 /* SDRAM_BASE */ 129 #define CONFIG_SYS_SDRC_MR_VAL4 AT91_SDRAMC_MODE_LMR 130 #define CONFIG_SYS_SDRAM_VAL10 0 /* SDRAM_BASE */ 131 #define CONFIG_SYS_SDRC_MR_VAL5 AT91_SDRAMC_MODE_NORMAL 132 #define CONFIG_SYS_SDRAM_VAL11 0 /* SDRAM_BASE */ 133 #define CONFIG_SYS_SDRC_TR_VAL2 1200 /* SDRAM_TR */ 134 #define CONFIG_SYS_SDRAM_VAL12 0 /* SDRAM_BASE */ 135 136 /* setup SMC0, CS0 (NOR Flash) - 16-bit, 15 WS */ 137 #define CONFIG_SYS_SMC0_SETUP0_VAL \ 138 (AT91_SMC_NWESETUP_(10) | AT91_SMC_NCS_WRSETUP_(10) | \ 139 AT91_SMC_NRDSETUP_(10) | AT91_SMC_NCS_RDSETUP_(10)) 140 #define CONFIG_SYS_SMC0_PULSE0_VAL \ 141 (AT91_SMC_NWEPULSE_(11) | AT91_SMC_NCS_WRPULSE_(11) | \ 142 AT91_SMC_NRDPULSE_(11) | AT91_SMC_NCS_RDPULSE_(11)) 143 #define CONFIG_SYS_SMC0_CYCLE0_VAL \ 144 (AT91_SMC_NWECYCLE_(22) | AT91_SMC_NRDCYCLE_(22)) 145 #define CONFIG_SYS_SMC0_MODE0_VAL \ 146 (AT91_SMC_READMODE | AT91_SMC_WRITEMODE | \ 147 AT91_SMC_DBW_16 | \ 148 AT91_SMC_TDFMODE | \ 149 AT91_SMC_TDF_(6)) 150 151 /* user reset enable */ 152 #define CONFIG_SYS_RSTC_RMR_VAL \ 153 (AT91_RSTC_KEY | \ 154 AT91_RSTC_PROCRST | \ 155 AT91_RSTC_RSTTYP_WAKEUP | \ 156 AT91_RSTC_RSTTYP_WATCHDOG) 157 158 /* Disable Watchdog */ 159 #define CONFIG_SYS_WDTC_WDMR_VAL \ 160 (AT91_WDT_WDIDLEHLT | AT91_WDT_WDDBGHLT | \ 161 AT91_WDT_WDV | \ 162 AT91_WDT_WDDIS | \ 163 AT91_WDT_WDD) 164 165 #define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ 166 #define CONFIG_SETUP_MEMORY_TAGS 1 167 #define CONFIG_INITRD_TAG 1 168 169 #undef CONFIG_SKIP_LOWLEVEL_INIT 170 #undef CONFIG_SKIP_RELOCATE_UBOOT 171 #define CONFIG_USER_LOWLEVEL_INIT 1 172 173 /* 174 * Hardware drivers 175 */ 176 #define CONFIG_AT91_GPIO 1 177 #define CONFIG_ATMEL_USART 1 178 #undef CONFIG_USART0 179 #undef CONFIG_USART1 180 #undef CONFIG_USART2 181 #define CONFIG_USART3 1 /* USART 3 is DBGU */ 182 183 /* LCD */ 184 #define CONFIG_LCD 1 185 #define LCD_BPP LCD_COLOR8 186 #define CONFIG_LCD_LOGO 1 187 #undef LCD_TEST_PATTERN 188 #define CONFIG_LCD_INFO 1 189 #define CONFIG_LCD_INFO_BELOW_LOGO 1 190 #define CONFIG_SYS_WHITE_ON_BLACK 1 191 #define CONFIG_ATMEL_LCD 1 192 #define CONFIG_ATMEL_LCD_BGR555 1 193 #define CONFIG_SYS_CONSOLE_IS_IN_ENV 1 194 195 #define CONFIG_LCD_IN_PSRAM 1 196 197 /* LED */ 198 #define CONFIG_AT91_LED 199 #define CONFIG_RED_LED AT91_PIN_PB7 /* this is the power led */ 200 #define CONFIG_GREEN_LED AT91_PIN_PB8 /* this is the user1 led */ 201 202 #define CONFIG_BOOTDELAY 3 203 204 /* 205 * BOOTP options 206 */ 207 #define CONFIG_BOOTP_BOOTFILESIZE 1 208 #define CONFIG_BOOTP_BOOTPATH 1 209 #define CONFIG_BOOTP_GATEWAY 1 210 #define CONFIG_BOOTP_HOSTNAME 1 211 212 /* 213 * Command line configuration. 214 */ 215 #include <config_cmd_default.h> 216 #undef CONFIG_CMD_BDI 217 #undef CONFIG_CMD_IMI 218 #undef CONFIG_CMD_AUTOSCRIPT 219 #undef CONFIG_CMD_FPGA 220 #undef CONFIG_CMD_LOADS 221 #undef CONFIG_CMD_IMLS 222 223 #define CONFIG_CMD_PING 1 224 #define CONFIG_CMD_DHCP 1 225 #define CONFIG_CMD_NAND 1 226 #define CONFIG_CMD_USB 1 227 228 /* SDRAM */ 229 #define CONFIG_NR_DRAM_BANKS 1 230 #define PHYS_SDRAM 0x20000000 231 #define PHYS_SDRAM_SIZE 0x04000000 /* 64 megs */ 232 233 /* DataFlash */ 234 #define CONFIG_ATMEL_DATAFLASH_SPI 235 #define CONFIG_HAS_DATAFLASH 1 236 #define CONFIG_SYS_SPI_WRITE_TOUT (5 * CONFIG_SYS_HZ) 237 #define CONFIG_SYS_MAX_DATAFLASH_BANKS 1 238 #define CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0 0xC0000000 /* CS0 */ 239 #define AT91_SPI_CLK 15000000 240 #define DATAFLASH_TCSS (0x1a << 16) 241 #define DATAFLASH_TCHS (0x1 << 24) 242 243 /* NOR flash, if populated */ 244 #define CONFIG_SYS_FLASH_CFI 1 245 #define CONFIG_FLASH_CFI_DRIVER 1 246 #define PHYS_FLASH_1 0x10000000 247 #define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1 248 #define CONFIG_SYS_MAX_FLASH_SECT 256 249 #define CONFIG_SYS_MAX_FLASH_BANKS 1 250 251 /* NAND flash */ 252 #ifdef CONFIG_CMD_NAND 253 #define CONFIG_NAND_ATMEL 254 #define CONFIG_SYS_NAND_MAX_CHIPS 1 255 #define CONFIG_SYS_MAX_NAND_DEVICE 1 256 #define CONFIG_SYS_NAND_BASE 0x40000000 257 #define CONFIG_SYS_NAND_DBW_8 1 258 /* our ALE is AD21 */ 259 #define CONFIG_SYS_NAND_MASK_ALE (1 << 21) 260 /* our CLE is AD22 */ 261 #define CONFIG_SYS_NAND_MASK_CLE (1 << 22) 262 #define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIN_PD15 263 #define CONFIG_SYS_NAND_READY_PIN AT91_PIN_PB30 264 265 #endif 266 267 #define CONFIG_CMD_JFFS2 1 268 #define CONFIG_JFFS2_CMDLINE 1 269 #define CONFIG_JFFS2_NAND 1 270 #define CONFIG_JFFS2_DEV "nand0" /* NAND device jffs2 lives on */ 271 #define CONFIG_JFFS2_PART_OFFSET 0 /* start of jffs2 partition */ 272 #define CONFIG_JFFS2_PART_SIZE (256 * 1024 * 1024) /* partition size*/ 273 274 /* PSRAM */ 275 #define PHYS_PSRAM 0x70000000 276 #define PHYS_PSRAM_SIZE 0x00400000 /* 4MB */ 277 278 /* Ethernet */ 279 #define CONFIG_MACB 1 280 #define CONFIG_RMII 1 281 #define CONFIG_NET_MULTI 1 282 #define CONFIG_NET_RETRY_COUNT 20 283 #define CONFIG_RESET_PHY_R 1 284 285 /* USB */ 286 #define CONFIG_USB_ATMEL 287 #define CONFIG_USB_OHCI_NEW 1 288 #define CONFIG_DOS_PARTITION 1 289 #define CONFIG_SYS_USB_OHCI_CPU_INIT 1 290 #define CONFIG_SYS_USB_OHCI_REGS_BASE 0x00a00000 /* AT91SAM9263_UHP_BASE */ 291 #define CONFIG_SYS_USB_OHCI_SLOT_NAME "at91sam9263" 292 #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2 293 #define CONFIG_USB_STORAGE 1 294 295 #define CONFIG_SYS_LOAD_ADDR 0x22000000 /* load address */ 296 297 #define CONFIG_SYS_MEMTEST_START PHYS_SDRAM 298 #define CONFIG_SYS_MEMTEST_END 0x23e00000 299 300 #define CONFIG_SYS_USE_FLASH 1 301 #undef CONFIG_SYS_USE_DATAFLASH 302 #undef CONFIG_SYS_USE_NANDFLASH 303 304 #ifdef CONFIG_SYS_USE_DATAFLASH 305 306 /* bootstrap + u-boot + env + linux in dataflash on CS0 */ 307 #define CONFIG_ENV_IS_IN_DATAFLASH 308 #define CFG_MONITOR_BASE (CFG_DATAFLASH_LOGIC_ADDR_CS0 + 0x8400) 309 #define CONFIG_ENV_OFFSET 0x4200 310 #define CONFIG_ENV_ADDR (CFG_DATAFLASH_LOGIC_ADDR_CS0 + CONFIG_ENV_OFFSET) 311 #define CONFIG_ENV_SIZE 0x4200 312 #define CONFIG_BOOTCOMMAND "cp.b 0xC0042000 0x22000000 0x210000; bootm" 313 #define CONFIG_BOOTARGS "console=ttyS0,115200 " \ 314 "root=/dev/mtdblock0 " \ 315 "mtdparts=atmel_nand:-(root) "\ 316 "rw rootfstype=jffs2" 317 318 #elif defined(CONFIG_SYS_USE_NANDFLASH) /* CFG_USE_NANDFLASH */ 319 320 /* bootstrap + u-boot + env + linux in nandflash */ 321 #define CONFIG_ENV_IS_IN_NAND 322 #define CONFIG_ENV_OFFSET 0x60000 323 #define CONFIG_ENV_OFFSET_REDUND 0x80000 324 #define CONFIG_ENV_SIZE 0x20000 /* 1 sector = 128 kB */ 325 #define CONFIG_BOOTCOMMAND "nand read 0x22000000 0xA0000 0x200000; bootm" 326 #define CONFIG_BOOTARGS "console=ttyS0,115200 " \ 327 "root=/dev/mtdblock5 " \ 328 "mtdparts=atmel_nand:" \ 329 "128k(bootstrap)ro," \ 330 "256k(uboot)ro," \ 331 "128k(env1)ro," \ 332 "128k(env2)ro," \ 333 "2M(linux)," \ 334 "-(root) " \ 335 "rw rootfstype=jffs2" 336 337 #elif defined(CONFIG_SYS_USE_FLASH) /* CFG_USE_FLASH */ 338 339 #define CONFIG_ENV_IS_IN_FLASH 1 340 #define CONFIG_ENV_OFFSET 0x40000 341 #define CONFIG_ENV_SECT_SIZE 0x10000 342 #define CONFIG_ENV_SIZE 0x10000 343 #define CONFIG_ENV_OVERWRITE 1 344 345 /* JFFS Partition offset set */ 346 #define CONFIG_SYS_JFFS2_FIRST_BANK 0 347 #define CONFIG_SYS_JFFS2_NUM_BANKS 1 348 349 /* 512k reserved for u-boot */ 350 #define CONFIG_SYS_JFFS2_FIRST_SECTOR 11 351 352 #define CONFIG_BOOTCOMMAND "run flashboot" 353 #define CONFIG_ROOTPATH /ronetix/rootfs 354 #define CONFIG_AUTOBOOT_PROMPT "autoboot in %d seconds\n" 355 356 #define CONFIG_CON_ROT "fbcon=rotate:3 " 357 #define CONFIG_BOOTARGS "root=/dev/mtdblock4 rootfstype=jffs2 "\ 358 CONFIG_CON_ROT 359 360 #define MTDIDS_DEFAULT "nor0=physmap-flash.0,nand0=nand" 361 #define MTDPARTS_DEFAULT \ 362 "mtdparts=physmap-flash.0:" \ 363 "256k(u-boot)ro," \ 364 "64k(u-boot-env)ro," \ 365 "1408k(kernel)," \ 366 "-(rootfs);" \ 367 "nand:-(nand)" 368 369 #define CONFIG_EXTRA_ENV_SETTINGS \ 370 "mtdids=" MTDIDS_DEFAULT "\0" \ 371 "mtdparts=" MTDPARTS_DEFAULT "\0" \ 372 "partition=nand0,0\0" \ 373 "ramargs=setenv bootargs $(bootargs) $(mtdparts)\0" \ 374 "nfsargs=setenv bootargs root=/dev/nfs rw " \ 375 CONFIG_CON_ROT \ 376 "nfsroot=$(serverip):$(rootpath) $(mtdparts)\0" \ 377 "addip=setenv bootargs $(bootargs) " \ 378 "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask)"\ 379 ":$(hostname):eth0:off\0" \ 380 "ramboot=tftpboot 0x22000000 vmImage;" \ 381 "run ramargs;run addip;bootm 22000000\0" \ 382 "nfsboot=tftpboot 0x22000000 vmImage;" \ 383 "run nfsargs;run addip;bootm 22000000\0" \ 384 "flashboot=run ramargs;run addip;bootm 0x10050000\0" \ 385 "" 386 387 #else 388 #error "Undefined memory device" 389 #endif 390 391 #define CONFIG_BAUDRATE 115200 392 #define CONFIG_SYS_BAUDRATE_TABLE {115200 , 19200, 38400, 57600, 9600 } 393 394 #define CONFIG_SYS_PROMPT "u-boot-pm9263> " 395 #define CONFIG_SYS_CBSIZE 256 396 #define CONFIG_SYS_MAXARGS 16 397 #define CONFIG_SYS_PBSIZE \ 398 (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) 399 #define CONFIG_SYS_LONGHELP 1 400 #define CONFIG_CMDLINE_EDITING 1 401 402 /* 403 * Size of malloc() pool 404 */ 405 #define CONFIG_SYS_MALLOC_LEN ROUND(3 * CONFIG_ENV_SIZE + 128 * 1024, 0x1000) 406 #define CONFIG_SYS_GBL_DATA_SIZE 128 /* 128 bytes for initial data */ 407 408 #define CONFIG_STACKSIZE (32 * 1024) /* regular stack */ 409 410 #ifdef CONFIG_USE_IRQ 411 #error CONFIG_USE_IRQ not supported 412 #endif 413 414 #endif 415