xref: /openbmc/u-boot/include/configs/pm9263.h (revision 98f705c9)
1 /*
2  * (C) Copyright 2007-2008
3  * Stelian Pop <stelian@popies.net>
4  * Lead Tech Design <www.leadtechdesign.com>
5  * Ilko Iliev <www.ronetix.at>
6  *
7  * Configuation settings for the RONETIX PM9263 board.
8  *
9  * SPDX-License-Identifier:	GPL-2.0+
10  */
11 
12 #ifndef __CONFIG_H
13 #define __CONFIG_H
14 
15 /*
16  * SoC must be defined first, before hardware.h is included.
17  * In this case SoC is defined in boards.cfg.
18  */
19 #include <asm/hardware.h>
20 
21 /* ARM asynchronous clock */
22 
23 #define MASTER_PLL_DIV		6
24 #define MASTER_PLL_MUL		65
25 #define MAIN_PLL_DIV		2	/* 2 or 4 */
26 #define CONFIG_SYS_AT91_MAIN_CLOCK	18432000
27 #define CONFIG_SYS_AT91_SLOW_CLOCK	32768		/* slow clock xtal */
28 
29 #define CONFIG_SYS_AT91_CPU_NAME	"AT91SAM9263"
30 #define CONFIG_PM9263		1	/* on a Ronetix PM9263 Board	*/
31 #define CONFIG_ARCH_CPU_INIT
32 #define CONFIG_SYS_TEXT_BASE	0
33 
34 #define CONFIG_MACH_TYPE	MACH_TYPE_PM9263
35 
36 /* clocks */
37 #define CONFIG_SYS_MOR_VAL						\
38 		(AT91_PMC_MOR_MOSCEN |					\
39 		 (255 << 8))		/* Main Oscillator Start-up Time */
40 #define CONFIG_SYS_PLLAR_VAL						\
41 		(AT91_PMC_PLLAR_29 | /* Bit 29 must be 1 when prog */ \
42 		 AT91_PMC_PLLXR_OUT(3) |				\
43 		 AT91_PMC_PLLXR_PLLCOUNT(0x3f) |	/* PLL Counter */\
44 		 (2 << 28) |		/* PLL Clock Frequency Range */	\
45 		 ((MASTER_PLL_MUL - 1) << 16) | (MASTER_PLL_DIV))
46 
47 #if (MAIN_PLL_DIV == 2)
48 /* PCK/2 = MCK Master Clock from PLLA */
49 #define	CONFIG_SYS_MCKR1_VAL		\
50 		(AT91_PMC_MCKR_CSS_SLOW |	\
51 		 AT91_PMC_MCKR_PRES_1 |	\
52 		 AT91_PMC_MCKR_MDIV_2)
53 /* PCK/2 = MCK Master Clock from PLLA */
54 #define	CONFIG_SYS_MCKR2_VAL		\
55 		(AT91_PMC_MCKR_CSS_PLLA |	\
56 		 AT91_PMC_MCKR_PRES_1 |	\
57 		 AT91_PMC_MCKR_MDIV_2)
58 #else
59 /* PCK/4 = MCK Master Clock from PLLA */
60 #define	CONFIG_SYS_MCKR1_VAL			\
61 		(AT91_PMC_MCKR_CSS_SLOW |		\
62 		 AT91_PMC_MCKR_PRES_1 |		\
63 		 AT91_PMC_MCKR_MDIV_4)
64 /* PCK/4 = MCK Master Clock from PLLA */
65 #define	CONFIG_SYS_MCKR2_VAL			\
66 		(AT91_PMC_MCKR_CSS_PLLA |		\
67 		 AT91_PMC_MCKR_PRES_1 |		\
68 		 AT91_PMC_MCKR_MDIV_4)
69 #endif
70 /* define PDC[31:16] as DATA[31:16] */
71 #define CONFIG_SYS_PIOD_PDR_VAL1	0xFFFF0000
72 /* no pull-up for D[31:16] */
73 #define CONFIG_SYS_PIOD_PPUDR_VAL	0xFFFF0000
74 /* EBI0_CSA, CS1 SDRAM, CS3 NAND Flash, 3.3V memories */
75 #define CONFIG_SYS_MATRIX_EBI0CSA_VAL					\
76 	(AT91_MATRIX_CSA_DBPUC | AT91_MATRIX_CSA_VDDIOMSEL_3_3V |	\
77 	 AT91_MATRIX_CSA_EBI_CS1A)
78 
79 /* SDRAM */
80 /* SDRAMC_MR Mode register */
81 #define CONFIG_SYS_SDRC_MR_VAL1		0
82 /* SDRAMC_TR - Refresh Timer register */
83 #define CONFIG_SYS_SDRC_TR_VAL1		0x3AA
84 /* SDRAMC_CR - Configuration register*/
85 #define CONFIG_SYS_SDRC_CR_VAL							\
86 		(AT91_SDRAMC_NC_9 |						\
87 		 AT91_SDRAMC_NR_13 |						\
88 		 AT91_SDRAMC_NB_4 |						\
89 		 AT91_SDRAMC_CAS_2 |						\
90 		 AT91_SDRAMC_DBW_32 |						\
91 		 (2 <<  8) |	/* tWR -  Write Recovery Delay */		\
92 		 (7 << 12) |	/* tRC -  Row Cycle Delay */			\
93 		 (2 << 16) |	/* tRP -  Row Precharge Delay */		\
94 		 (2 << 20) |	/* tRCD - Row to Column Delay */		\
95 		 (5 << 24) |	/* tRAS - Active to Precharge Delay */		\
96 		 (8 << 28))	/* tXSR - Exit Self Refresh to Active Delay */
97 
98 /* Memory Device Register -> SDRAM */
99 #define CONFIG_SYS_SDRC_MDR_VAL		AT91_SDRAMC_MD_SDRAM
100 #define CONFIG_SYS_SDRC_MR_VAL2		AT91_SDRAMC_MODE_PRECHARGE
101 #define CONFIG_SYS_SDRAM_VAL1		0		/* SDRAM_BASE */
102 #define CONFIG_SYS_SDRC_MR_VAL3		AT91_SDRAMC_MODE_REFRESH
103 #define CONFIG_SYS_SDRAM_VAL2		0		/* SDRAM_BASE */
104 #define CONFIG_SYS_SDRAM_VAL3		0		/* SDRAM_BASE */
105 #define CONFIG_SYS_SDRAM_VAL4		0		/* SDRAM_BASE */
106 #define CONFIG_SYS_SDRAM_VAL5		0		/* SDRAM_BASE */
107 #define CONFIG_SYS_SDRAM_VAL6		0		/* SDRAM_BASE */
108 #define CONFIG_SYS_SDRAM_VAL7		0		/* SDRAM_BASE */
109 #define CONFIG_SYS_SDRAM_VAL8		0		/* SDRAM_BASE */
110 #define CONFIG_SYS_SDRAM_VAL9		0		/* SDRAM_BASE */
111 #define CONFIG_SYS_SDRC_MR_VAL4		AT91_SDRAMC_MODE_LMR
112 #define CONFIG_SYS_SDRAM_VAL10		0		/* SDRAM_BASE */
113 #define CONFIG_SYS_SDRC_MR_VAL5		AT91_SDRAMC_MODE_NORMAL
114 #define CONFIG_SYS_SDRAM_VAL11		0		/* SDRAM_BASE */
115 #define CONFIG_SYS_SDRC_TR_VAL2		1200		/* SDRAM_TR */
116 #define CONFIG_SYS_SDRAM_VAL12		0		/* SDRAM_BASE */
117 
118 /* setup SMC0, CS0 (NOR Flash) - 16-bit, 15 WS */
119 #define CONFIG_SYS_SMC0_SETUP0_VAL					\
120 		(AT91_SMC_SETUP_NWE(10) | AT91_SMC_SETUP_NCS_WR(10) |	\
121 		 AT91_SMC_SETUP_NRD(10) | AT91_SMC_SETUP_NCS_RD(10))
122 #define CONFIG_SYS_SMC0_PULSE0_VAL					\
123 		(AT91_SMC_PULSE_NWE(11) | AT91_SMC_PULSE_NCS_WR(11) |	\
124 		 AT91_SMC_PULSE_NRD(11) | AT91_SMC_PULSE_NCS_RD(11))
125 #define CONFIG_SYS_SMC0_CYCLE0_VAL	\
126 		(AT91_SMC_CYCLE_NWE(22) | AT91_SMC_CYCLE_NRD(22))
127 #define CONFIG_SYS_SMC0_MODE0_VAL				\
128 		(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |	\
129 		 AT91_SMC_MODE_DBW_16 |				\
130 		 AT91_SMC_MODE_TDF |				\
131 		 AT91_SMC_MODE_TDF_CYCLE(6))
132 
133 /* user reset enable */
134 #define CONFIG_SYS_RSTC_RMR_VAL			\
135 		(AT91_RSTC_KEY |		\
136 		AT91_RSTC_CR_PROCRST |		\
137 		AT91_RSTC_MR_ERSTL(1) |	\
138 		AT91_RSTC_MR_ERSTL(2))
139 
140 /* Disable Watchdog */
141 #define CONFIG_SYS_WDTC_WDMR_VAL				\
142 		(AT91_WDT_MR_WDIDLEHLT | AT91_WDT_MR_WDDBGHLT |	\
143 		 AT91_WDT_MR_WDV(0xfff) |					\
144 		 AT91_WDT_MR_WDDIS |				\
145 		 AT91_WDT_MR_WDD(0xfff))
146 
147 #define CONFIG_CMDLINE_TAG	1	/* enable passing of ATAGs */
148 #define CONFIG_SETUP_MEMORY_TAGS 1
149 #define CONFIG_INITRD_TAG	1
150 
151 #undef CONFIG_SKIP_LOWLEVEL_INIT
152 #define CONFIG_USER_LOWLEVEL_INIT	1
153 
154 /*
155  * Hardware drivers
156  */
157 #define CONFIG_AT91_GPIO	1
158 #define CONFIG_ATMEL_USART	1
159 #define CONFIG_USART_BASE		ATMEL_BASE_DBGU
160 #define	CONFIG_USART_ID			ATMEL_ID_SYS
161 
162 /* LCD */
163 #define LCD_BPP				LCD_COLOR8
164 #define CONFIG_LCD_LOGO			1
165 #undef LCD_TEST_PATTERN
166 #define CONFIG_LCD_INFO			1
167 #define CONFIG_LCD_INFO_BELOW_LOGO	1
168 #define CONFIG_ATMEL_LCD		1
169 #define CONFIG_ATMEL_LCD_BGR555		1
170 
171 #define CONFIG_LCD_IN_PSRAM		1
172 
173 /* LED */
174 #define CONFIG_AT91_LED
175 #define CONFIG_RED_LED		GPIO_PIN_PB(7) /* this is the power led */
176 #define CONFIG_GREEN_LED	GPIO_PIN_PB(8) /* this is the user1 led */
177 
178 
179 /*
180  * BOOTP options
181  */
182 #define CONFIG_BOOTP_BOOTFILESIZE	1
183 #define CONFIG_BOOTP_BOOTPATH		1
184 #define CONFIG_BOOTP_GATEWAY		1
185 #define CONFIG_BOOTP_HOSTNAME		1
186 
187 /*
188  * Command line configuration.
189  */
190 #define CONFIG_CMD_NAND		1
191 
192 /* SDRAM */
193 #define CONFIG_NR_DRAM_BANKS	1
194 #define PHYS_SDRAM		0x20000000
195 #define PHYS_SDRAM_SIZE		0x04000000	/* 64 megs */
196 
197 /* DataFlash */
198 #define CONFIG_ATMEL_DATAFLASH_SPI
199 #define CONFIG_HAS_DATAFLASH			1
200 #define CONFIG_SYS_MAX_DATAFLASH_BANKS		1
201 #define CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0	0xC0000000	/* CS0 */
202 #define AT91_SPI_CLK				15000000
203 #define DATAFLASH_TCSS				(0x1a << 16)
204 #define DATAFLASH_TCHS				(0x1 << 24)
205 
206 /* NOR flash, if populated */
207 #define CONFIG_SYS_FLASH_CFI		1
208 #define CONFIG_FLASH_CFI_DRIVER		1
209 #define PHYS_FLASH_1			0x10000000
210 #define CONFIG_SYS_FLASH_BASE		PHYS_FLASH_1
211 #define CONFIG_SYS_MAX_FLASH_SECT	256
212 #define CONFIG_SYS_MAX_FLASH_BANKS	1
213 
214 /* NAND flash */
215 #ifdef CONFIG_CMD_NAND
216 #define CONFIG_NAND_ATMEL
217 #define CONFIG_SYS_MAX_NAND_DEVICE	1
218 #define CONFIG_SYS_NAND_BASE		0x40000000
219 #define CONFIG_SYS_NAND_DBW_8		1
220 /* our ALE is AD21 */
221 #define CONFIG_SYS_NAND_MASK_ALE	(1 << 21)
222 /* our CLE is AD22 */
223 #define CONFIG_SYS_NAND_MASK_CLE	(1 << 22)
224 #define CONFIG_SYS_NAND_ENABLE_PIN	GPIO_PIN_PD(15)
225 #define CONFIG_SYS_NAND_READY_PIN	GPIO_PIN_PB(30)
226 
227 #endif
228 
229 #define CONFIG_JFFS2_CMDLINE		1
230 #define CONFIG_JFFS2_NAND		1
231 #define CONFIG_JFFS2_DEV		"nand0" /* NAND device jffs2 lives on */
232 #define CONFIG_JFFS2_PART_OFFSET	0	/* start of jffs2 partition */
233 #define CONFIG_JFFS2_PART_SIZE		(256 * 1024 * 1024) /* partition size*/
234 
235 /* PSRAM */
236 #define	PHYS_PSRAM			0x70000000
237 #define	PHYS_PSRAM_SIZE			0x00400000	/* 4MB */
238 /* Slave EBI1, PSRAM connected */
239 #define CONFIG_PSRAM_SCFG		(AT91_MATRIX_SCFG_ARBT_FIXED_PRIORITY	| \
240 					 AT91_MATRIX_SCFG_FIXED_DEFMSTR(5)	| \
241 					 AT91_MATRIX_SCFG_DEFMSTR_TYPE_FIXED	| \
242 					 AT91_MATRIX_SCFG_SLOT_CYCLE(255))
243 
244 /* Ethernet */
245 #define CONFIG_MACB			1
246 #define CONFIG_RMII			1
247 #define CONFIG_NET_RETRY_COUNT		20
248 #define CONFIG_RESET_PHY_R		1
249 
250 /* USB */
251 #define CONFIG_USB_ATMEL
252 #define CONFIG_USB_ATMEL_CLK_SEL_PLLB
253 #define CONFIG_USB_OHCI_NEW			1
254 #define CONFIG_SYS_USB_OHCI_CPU_INIT		1
255 #define CONFIG_SYS_USB_OHCI_REGS_BASE		0x00a00000	/* AT91SAM9263_UHP_BASE */
256 #define CONFIG_SYS_USB_OHCI_SLOT_NAME		"at91sam9263"
257 #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS	2
258 
259 #define CONFIG_SYS_LOAD_ADDR			0x22000000	/* load address */
260 
261 #define CONFIG_SYS_MEMTEST_START		PHYS_SDRAM
262 #define CONFIG_SYS_MEMTEST_END			0x23e00000
263 
264 #define CONFIG_SYS_USE_FLASH	1
265 #undef CONFIG_SYS_USE_DATAFLASH
266 #undef CONFIG_SYS_USE_NANDFLASH
267 
268 #ifdef CONFIG_SYS_USE_DATAFLASH
269 
270 /* bootstrap + u-boot + env + linux in dataflash on CS0 */
271 #define CONFIG_ENV_IS_IN_DATAFLASH
272 #define CFG_MONITOR_BASE	(CFG_DATAFLASH_LOGIC_ADDR_CS0 + 0x8400)
273 #define CONFIG_ENV_OFFSET	0x4200
274 #define CONFIG_ENV_ADDR		(CFG_DATAFLASH_LOGIC_ADDR_CS0 + CONFIG_ENV_OFFSET)
275 #define CONFIG_ENV_SIZE		0x4200
276 #define CONFIG_BOOTCOMMAND	"cp.b 0xC0042000 0x22000000 0x210000; bootm"
277 #define CONFIG_BOOTARGS		"console=ttyS0,115200 " \
278 				"root=/dev/mtdblock0 " \
279 				"mtdparts=atmel_nand:-(root) "\
280 				"rw rootfstype=jffs2"
281 
282 #elif defined(CONFIG_SYS_USE_NANDFLASH) /* CFG_USE_NANDFLASH */
283 
284 /* bootstrap + u-boot + env + linux in nandflash */
285 #define CONFIG_ENV_IS_IN_NAND
286 #define CONFIG_ENV_OFFSET		0x60000
287 #define CONFIG_ENV_OFFSET_REDUND	0x80000
288 #define CONFIG_ENV_SIZE		0x20000		/* 1 sector = 128 kB */
289 #define CONFIG_BOOTCOMMAND	"nand read 0x22000000 0xA0000 0x200000; bootm"
290 #define CONFIG_BOOTARGS		"console=ttyS0,115200 "		\
291 				"root=/dev/mtdblock5 "		\
292 				"mtdparts=atmel_nand:"		\
293 					"128k(bootstrap)ro,"	\
294 					"256k(uboot)ro,"	\
295 					"128k(env1)ro,"		\
296 					"128k(env2)ro,"		\
297 					"2M(linux),"		\
298 					"-(root) "		\
299 				"rw rootfstype=jffs2"
300 
301 #elif defined(CONFIG_SYS_USE_FLASH) /* CFG_USE_FLASH */
302 
303 #define CONFIG_ENV_IS_IN_FLASH	1
304 #define CONFIG_ENV_OFFSET	0x40000
305 #define CONFIG_ENV_SECT_SIZE	0x10000
306 #define	CONFIG_ENV_SIZE		0x10000
307 #define CONFIG_ENV_OVERWRITE	1
308 
309 /* JFFS Partition offset set */
310 #define CONFIG_SYS_JFFS2_FIRST_BANK	0
311 #define CONFIG_SYS_JFFS2_NUM_BANKS	1
312 
313 /* 512k reserved for u-boot */
314 #define CONFIG_SYS_JFFS2_FIRST_SECTOR	11
315 
316 #define CONFIG_BOOTCOMMAND		"run flashboot"
317 #define CONFIG_ROOTPATH			"/ronetix/rootfs"
318 
319 #define CONFIG_CON_ROT			"fbcon=rotate:3 "
320 #define CONFIG_BOOTARGS			"root=/dev/mtdblock4 rootfstype=jffs2 "\
321 					CONFIG_CON_ROT
322 
323 #define MTDIDS_DEFAULT			"nor0=physmap-flash.0,nand0=nand"
324 #define MTDPARTS_DEFAULT		\
325 	"mtdparts=physmap-flash.0:"	\
326 		"256k(u-boot)ro,"	\
327 		"64k(u-boot-env)ro,"	\
328 		"1408k(kernel),"	\
329 		"-(rootfs);"		\
330 	"nand:-(nand)"
331 
332 #define CONFIG_EXTRA_ENV_SETTINGS				\
333 	"mtdids=" MTDIDS_DEFAULT "\0"				\
334 	"mtdparts=" MTDPARTS_DEFAULT "\0"			\
335 	"partition=nand0,0\0"					\
336 	"ramargs=setenv bootargs $(bootargs) $(mtdparts)\0"	\
337 	"nfsargs=setenv bootargs root=/dev/nfs rw "		\
338 		CONFIG_CON_ROT					\
339 		"nfsroot=$(serverip):$(rootpath) $(mtdparts)\0"	\
340 	"addip=setenv bootargs $(bootargs) "			\
341 		"ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask)"\
342 		":$(hostname):eth0:off\0"			\
343 	"ramboot=tftpboot 0x22000000 vmImage;"			\
344 		"run ramargs;run addip;bootm 22000000\0"	\
345 	"nfsboot=tftpboot 0x22000000 vmImage;"			\
346 		"run nfsargs;run addip;bootm 22000000\0"	\
347 	"flashboot=run ramargs;run addip;bootm 0x10050000\0"	\
348 	""
349 
350 #else
351 #error "Undefined memory device"
352 #endif
353 
354 #define CONFIG_SYS_CBSIZE		256
355 #define CONFIG_SYS_MAXARGS		16
356 #define CONFIG_SYS_PBSIZE		\
357 		(CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
358 #define CONFIG_SYS_LONGHELP		1
359 #define CONFIG_CMDLINE_EDITING		1
360 
361 /*
362  * Size of malloc() pool
363  */
364 #define CONFIG_SYS_MALLOC_LEN	ROUND(3 * CONFIG_ENV_SIZE + 128 * 1024, 0x1000)
365 
366 #define CONFIG_SYS_SDRAM_BASE	PHYS_SDRAM
367 #define CONFIG_SYS_INIT_SP_ADDR	(CONFIG_SYS_SDRAM_BASE + 0x1000 - \
368 				GENERATED_GBL_DATA_SIZE)
369 
370 #endif
371