1 /* 2 * (C) Copyright 2007-2008 3 * Stelian Pop <stelian@popies.net> 4 * Lead Tech Design <www.leadtechdesign.com> 5 * Ilko Iliev <www.ronetix.at> 6 * 7 * Configuation settings for the RONETIX PM9263 board. 8 * 9 * SPDX-License-Identifier: GPL-2.0+ 10 */ 11 12 #ifndef __CONFIG_H 13 #define __CONFIG_H 14 15 /* 16 * SoC must be defined first, before hardware.h is included. 17 * In this case SoC is defined in boards.cfg. 18 */ 19 #include <asm/hardware.h> 20 21 /* ARM asynchronous clock */ 22 23 #define MASTER_PLL_DIV 6 24 #define MASTER_PLL_MUL 65 25 #define MAIN_PLL_DIV 2 /* 2 or 4 */ 26 #define CONFIG_SYS_AT91_MAIN_CLOCK 18432000 27 #define CONFIG_SYS_AT91_SLOW_CLOCK 32768 /* slow clock xtal */ 28 29 #define CONFIG_SYS_AT91_CPU_NAME "AT91SAM9263" 30 #define CONFIG_PM9263 1 /* on a Ronetix PM9263 Board */ 31 #define CONFIG_ARCH_CPU_INIT 32 #define CONFIG_SYS_TEXT_BASE 0 33 34 #define MACH_TYPE_PM9263 1475 35 #define CONFIG_MACH_TYPE MACH_TYPE_PM9263 36 37 /* clocks */ 38 #define CONFIG_SYS_MOR_VAL \ 39 (AT91_PMC_MOR_MOSCEN | \ 40 (255 << 8)) /* Main Oscillator Start-up Time */ 41 #define CONFIG_SYS_PLLAR_VAL \ 42 (AT91_PMC_PLLAR_29 | /* Bit 29 must be 1 when prog */ \ 43 AT91_PMC_PLLXR_OUT(3) | \ 44 AT91_PMC_PLLXR_PLLCOUNT(0x3f) | /* PLL Counter */\ 45 (2 << 28) | /* PLL Clock Frequency Range */ \ 46 ((MASTER_PLL_MUL - 1) << 16) | (MASTER_PLL_DIV)) 47 48 #if (MAIN_PLL_DIV == 2) 49 /* PCK/2 = MCK Master Clock from PLLA */ 50 #define CONFIG_SYS_MCKR1_VAL \ 51 (AT91_PMC_MCKR_CSS_SLOW | \ 52 AT91_PMC_MCKR_PRES_1 | \ 53 AT91_PMC_MCKR_MDIV_2) 54 /* PCK/2 = MCK Master Clock from PLLA */ 55 #define CONFIG_SYS_MCKR2_VAL \ 56 (AT91_PMC_MCKR_CSS_PLLA | \ 57 AT91_PMC_MCKR_PRES_1 | \ 58 AT91_PMC_MCKR_MDIV_2) 59 #else 60 /* PCK/4 = MCK Master Clock from PLLA */ 61 #define CONFIG_SYS_MCKR1_VAL \ 62 (AT91_PMC_MCKR_CSS_SLOW | \ 63 AT91_PMC_MCKR_PRES_1 | \ 64 AT91_PMC_MCKR_MDIV_4) 65 /* PCK/4 = MCK Master Clock from PLLA */ 66 #define CONFIG_SYS_MCKR2_VAL \ 67 (AT91_PMC_MCKR_CSS_PLLA | \ 68 AT91_PMC_MCKR_PRES_1 | \ 69 AT91_PMC_MCKR_MDIV_4) 70 #endif 71 /* define PDC[31:16] as DATA[31:16] */ 72 #define CONFIG_SYS_PIOD_PDR_VAL1 0xFFFF0000 73 /* no pull-up for D[31:16] */ 74 #define CONFIG_SYS_PIOD_PPUDR_VAL 0xFFFF0000 75 /* EBI0_CSA, CS1 SDRAM, CS3 NAND Flash, 3.3V memories */ 76 #define CONFIG_SYS_MATRIX_EBI0CSA_VAL \ 77 (AT91_MATRIX_CSA_DBPUC | AT91_MATRIX_CSA_VDDIOMSEL_3_3V | \ 78 AT91_MATRIX_CSA_EBI_CS1A) 79 80 /* SDRAM */ 81 /* SDRAMC_MR Mode register */ 82 #define CONFIG_SYS_SDRC_MR_VAL1 0 83 /* SDRAMC_TR - Refresh Timer register */ 84 #define CONFIG_SYS_SDRC_TR_VAL1 0x3AA 85 /* SDRAMC_CR - Configuration register*/ 86 #define CONFIG_SYS_SDRC_CR_VAL \ 87 (AT91_SDRAMC_NC_9 | \ 88 AT91_SDRAMC_NR_13 | \ 89 AT91_SDRAMC_NB_4 | \ 90 AT91_SDRAMC_CAS_2 | \ 91 AT91_SDRAMC_DBW_32 | \ 92 (2 << 8) | /* tWR - Write Recovery Delay */ \ 93 (7 << 12) | /* tRC - Row Cycle Delay */ \ 94 (2 << 16) | /* tRP - Row Precharge Delay */ \ 95 (2 << 20) | /* tRCD - Row to Column Delay */ \ 96 (5 << 24) | /* tRAS - Active to Precharge Delay */ \ 97 (8 << 28)) /* tXSR - Exit Self Refresh to Active Delay */ 98 99 /* Memory Device Register -> SDRAM */ 100 #define CONFIG_SYS_SDRC_MDR_VAL AT91_SDRAMC_MD_SDRAM 101 #define CONFIG_SYS_SDRC_MR_VAL2 AT91_SDRAMC_MODE_PRECHARGE 102 #define CONFIG_SYS_SDRAM_VAL1 0 /* SDRAM_BASE */ 103 #define CONFIG_SYS_SDRC_MR_VAL3 AT91_SDRAMC_MODE_REFRESH 104 #define CONFIG_SYS_SDRAM_VAL2 0 /* SDRAM_BASE */ 105 #define CONFIG_SYS_SDRAM_VAL3 0 /* SDRAM_BASE */ 106 #define CONFIG_SYS_SDRAM_VAL4 0 /* SDRAM_BASE */ 107 #define CONFIG_SYS_SDRAM_VAL5 0 /* SDRAM_BASE */ 108 #define CONFIG_SYS_SDRAM_VAL6 0 /* SDRAM_BASE */ 109 #define CONFIG_SYS_SDRAM_VAL7 0 /* SDRAM_BASE */ 110 #define CONFIG_SYS_SDRAM_VAL8 0 /* SDRAM_BASE */ 111 #define CONFIG_SYS_SDRAM_VAL9 0 /* SDRAM_BASE */ 112 #define CONFIG_SYS_SDRC_MR_VAL4 AT91_SDRAMC_MODE_LMR 113 #define CONFIG_SYS_SDRAM_VAL10 0 /* SDRAM_BASE */ 114 #define CONFIG_SYS_SDRC_MR_VAL5 AT91_SDRAMC_MODE_NORMAL 115 #define CONFIG_SYS_SDRAM_VAL11 0 /* SDRAM_BASE */ 116 #define CONFIG_SYS_SDRC_TR_VAL2 1200 /* SDRAM_TR */ 117 #define CONFIG_SYS_SDRAM_VAL12 0 /* SDRAM_BASE */ 118 119 /* setup SMC0, CS0 (NOR Flash) - 16-bit, 15 WS */ 120 #define CONFIG_SYS_SMC0_SETUP0_VAL \ 121 (AT91_SMC_SETUP_NWE(10) | AT91_SMC_SETUP_NCS_WR(10) | \ 122 AT91_SMC_SETUP_NRD(10) | AT91_SMC_SETUP_NCS_RD(10)) 123 #define CONFIG_SYS_SMC0_PULSE0_VAL \ 124 (AT91_SMC_PULSE_NWE(11) | AT91_SMC_PULSE_NCS_WR(11) | \ 125 AT91_SMC_PULSE_NRD(11) | AT91_SMC_PULSE_NCS_RD(11)) 126 #define CONFIG_SYS_SMC0_CYCLE0_VAL \ 127 (AT91_SMC_CYCLE_NWE(22) | AT91_SMC_CYCLE_NRD(22)) 128 #define CONFIG_SYS_SMC0_MODE0_VAL \ 129 (AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE | \ 130 AT91_SMC_MODE_DBW_16 | \ 131 AT91_SMC_MODE_TDF | \ 132 AT91_SMC_MODE_TDF_CYCLE(6)) 133 134 /* user reset enable */ 135 #define CONFIG_SYS_RSTC_RMR_VAL \ 136 (AT91_RSTC_KEY | \ 137 AT91_RSTC_CR_PROCRST | \ 138 AT91_RSTC_MR_ERSTL(1) | \ 139 AT91_RSTC_MR_ERSTL(2)) 140 141 /* Disable Watchdog */ 142 #define CONFIG_SYS_WDTC_WDMR_VAL \ 143 (AT91_WDT_MR_WDIDLEHLT | AT91_WDT_MR_WDDBGHLT | \ 144 AT91_WDT_MR_WDV(0xfff) | \ 145 AT91_WDT_MR_WDDIS | \ 146 AT91_WDT_MR_WDD(0xfff)) 147 148 #define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ 149 #define CONFIG_SETUP_MEMORY_TAGS 1 150 #define CONFIG_INITRD_TAG 1 151 152 #undef CONFIG_SKIP_LOWLEVEL_INIT 153 #define CONFIG_USER_LOWLEVEL_INIT 1 154 #define CONFIG_BOARD_EARLY_INIT_F 155 156 /* 157 * Hardware drivers 158 */ 159 #define CONFIG_AT91_GPIO 1 160 #define CONFIG_ATMEL_USART 1 161 #define CONFIG_USART_BASE ATMEL_BASE_DBGU 162 #define CONFIG_USART_ID ATMEL_ID_SYS 163 164 /* LCD */ 165 #define LCD_BPP LCD_COLOR8 166 #define CONFIG_LCD_LOGO 1 167 #undef LCD_TEST_PATTERN 168 #define CONFIG_LCD_INFO 1 169 #define CONFIG_LCD_INFO_BELOW_LOGO 1 170 #define CONFIG_SYS_WHITE_ON_BLACK 1 171 #define CONFIG_ATMEL_LCD 1 172 #define CONFIG_ATMEL_LCD_BGR555 1 173 174 #define CONFIG_LCD_IN_PSRAM 1 175 176 /* LED */ 177 #define CONFIG_AT91_LED 178 #define CONFIG_RED_LED GPIO_PIN_PB(7) /* this is the power led */ 179 #define CONFIG_GREEN_LED GPIO_PIN_PB(8) /* this is the user1 led */ 180 181 182 /* 183 * BOOTP options 184 */ 185 #define CONFIG_BOOTP_BOOTFILESIZE 1 186 #define CONFIG_BOOTP_BOOTPATH 1 187 #define CONFIG_BOOTP_GATEWAY 1 188 #define CONFIG_BOOTP_HOSTNAME 1 189 190 /* 191 * Command line configuration. 192 */ 193 #define CONFIG_CMD_NAND 1 194 195 /* SDRAM */ 196 #define CONFIG_NR_DRAM_BANKS 1 197 #define PHYS_SDRAM 0x20000000 198 #define PHYS_SDRAM_SIZE 0x04000000 /* 64 megs */ 199 200 /* DataFlash */ 201 #define CONFIG_ATMEL_DATAFLASH_SPI 202 #define CONFIG_HAS_DATAFLASH 1 203 #define CONFIG_SYS_MAX_DATAFLASH_BANKS 1 204 #define CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0 0xC0000000 /* CS0 */ 205 #define AT91_SPI_CLK 15000000 206 #define DATAFLASH_TCSS (0x1a << 16) 207 #define DATAFLASH_TCHS (0x1 << 24) 208 209 /* NOR flash, if populated */ 210 #define CONFIG_SYS_FLASH_CFI 1 211 #define CONFIG_FLASH_CFI_DRIVER 1 212 #define PHYS_FLASH_1 0x10000000 213 #define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1 214 #define CONFIG_SYS_MAX_FLASH_SECT 256 215 #define CONFIG_SYS_MAX_FLASH_BANKS 1 216 217 /* NAND flash */ 218 #ifdef CONFIG_CMD_NAND 219 #define CONFIG_NAND_ATMEL 220 #define CONFIG_SYS_MAX_NAND_DEVICE 1 221 #define CONFIG_SYS_NAND_BASE 0x40000000 222 #define CONFIG_SYS_NAND_DBW_8 1 223 /* our ALE is AD21 */ 224 #define CONFIG_SYS_NAND_MASK_ALE (1 << 21) 225 /* our CLE is AD22 */ 226 #define CONFIG_SYS_NAND_MASK_CLE (1 << 22) 227 #define CONFIG_SYS_NAND_ENABLE_PIN GPIO_PIN_PD(15) 228 #define CONFIG_SYS_NAND_READY_PIN GPIO_PIN_PB(30) 229 230 #endif 231 232 #define CONFIG_CMD_JFFS2 1 233 #define CONFIG_JFFS2_CMDLINE 1 234 #define CONFIG_JFFS2_NAND 1 235 #define CONFIG_JFFS2_DEV "nand0" /* NAND device jffs2 lives on */ 236 #define CONFIG_JFFS2_PART_OFFSET 0 /* start of jffs2 partition */ 237 #define CONFIG_JFFS2_PART_SIZE (256 * 1024 * 1024) /* partition size*/ 238 239 /* PSRAM */ 240 #define PHYS_PSRAM 0x70000000 241 #define PHYS_PSRAM_SIZE 0x00400000 /* 4MB */ 242 /* Slave EBI1, PSRAM connected */ 243 #define CONFIG_PSRAM_SCFG (AT91_MATRIX_SCFG_ARBT_FIXED_PRIORITY | \ 244 AT91_MATRIX_SCFG_FIXED_DEFMSTR(5) | \ 245 AT91_MATRIX_SCFG_DEFMSTR_TYPE_FIXED | \ 246 AT91_MATRIX_SCFG_SLOT_CYCLE(255)) 247 248 /* Ethernet */ 249 #define CONFIG_MACB 1 250 #define CONFIG_RMII 1 251 #define CONFIG_NET_RETRY_COUNT 20 252 #define CONFIG_RESET_PHY_R 1 253 254 /* USB */ 255 #define CONFIG_USB_ATMEL 256 #define CONFIG_USB_ATMEL_CLK_SEL_PLLB 257 #define CONFIG_USB_OHCI_NEW 1 258 #define CONFIG_DOS_PARTITION 1 259 #define CONFIG_SYS_USB_OHCI_CPU_INIT 1 260 #define CONFIG_SYS_USB_OHCI_REGS_BASE 0x00a00000 /* AT91SAM9263_UHP_BASE */ 261 #define CONFIG_SYS_USB_OHCI_SLOT_NAME "at91sam9263" 262 #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2 263 264 #define CONFIG_SYS_LOAD_ADDR 0x22000000 /* load address */ 265 266 #define CONFIG_SYS_MEMTEST_START PHYS_SDRAM 267 #define CONFIG_SYS_MEMTEST_END 0x23e00000 268 269 #define CONFIG_SYS_USE_FLASH 1 270 #undef CONFIG_SYS_USE_DATAFLASH 271 #undef CONFIG_SYS_USE_NANDFLASH 272 273 #ifdef CONFIG_SYS_USE_DATAFLASH 274 275 /* bootstrap + u-boot + env + linux in dataflash on CS0 */ 276 #define CONFIG_ENV_IS_IN_DATAFLASH 277 #define CFG_MONITOR_BASE (CFG_DATAFLASH_LOGIC_ADDR_CS0 + 0x8400) 278 #define CONFIG_ENV_OFFSET 0x4200 279 #define CONFIG_ENV_ADDR (CFG_DATAFLASH_LOGIC_ADDR_CS0 + CONFIG_ENV_OFFSET) 280 #define CONFIG_ENV_SIZE 0x4200 281 #define CONFIG_BOOTCOMMAND "cp.b 0xC0042000 0x22000000 0x210000; bootm" 282 #define CONFIG_BOOTARGS "console=ttyS0,115200 " \ 283 "root=/dev/mtdblock0 " \ 284 "mtdparts=atmel_nand:-(root) "\ 285 "rw rootfstype=jffs2" 286 287 #elif defined(CONFIG_SYS_USE_NANDFLASH) /* CFG_USE_NANDFLASH */ 288 289 /* bootstrap + u-boot + env + linux in nandflash */ 290 #define CONFIG_ENV_IS_IN_NAND 291 #define CONFIG_ENV_OFFSET 0x60000 292 #define CONFIG_ENV_OFFSET_REDUND 0x80000 293 #define CONFIG_ENV_SIZE 0x20000 /* 1 sector = 128 kB */ 294 #define CONFIG_BOOTCOMMAND "nand read 0x22000000 0xA0000 0x200000; bootm" 295 #define CONFIG_BOOTARGS "console=ttyS0,115200 " \ 296 "root=/dev/mtdblock5 " \ 297 "mtdparts=atmel_nand:" \ 298 "128k(bootstrap)ro," \ 299 "256k(uboot)ro," \ 300 "128k(env1)ro," \ 301 "128k(env2)ro," \ 302 "2M(linux)," \ 303 "-(root) " \ 304 "rw rootfstype=jffs2" 305 306 #elif defined(CONFIG_SYS_USE_FLASH) /* CFG_USE_FLASH */ 307 308 #define CONFIG_ENV_IS_IN_FLASH 1 309 #define CONFIG_ENV_OFFSET 0x40000 310 #define CONFIG_ENV_SECT_SIZE 0x10000 311 #define CONFIG_ENV_SIZE 0x10000 312 #define CONFIG_ENV_OVERWRITE 1 313 314 /* JFFS Partition offset set */ 315 #define CONFIG_SYS_JFFS2_FIRST_BANK 0 316 #define CONFIG_SYS_JFFS2_NUM_BANKS 1 317 318 /* 512k reserved for u-boot */ 319 #define CONFIG_SYS_JFFS2_FIRST_SECTOR 11 320 321 #define CONFIG_BOOTCOMMAND "run flashboot" 322 #define CONFIG_ROOTPATH "/ronetix/rootfs" 323 324 #define CONFIG_CON_ROT "fbcon=rotate:3 " 325 #define CONFIG_BOOTARGS "root=/dev/mtdblock4 rootfstype=jffs2 "\ 326 CONFIG_CON_ROT 327 328 #define MTDIDS_DEFAULT "nor0=physmap-flash.0,nand0=nand" 329 #define MTDPARTS_DEFAULT \ 330 "mtdparts=physmap-flash.0:" \ 331 "256k(u-boot)ro," \ 332 "64k(u-boot-env)ro," \ 333 "1408k(kernel)," \ 334 "-(rootfs);" \ 335 "nand:-(nand)" 336 337 #define CONFIG_EXTRA_ENV_SETTINGS \ 338 "mtdids=" MTDIDS_DEFAULT "\0" \ 339 "mtdparts=" MTDPARTS_DEFAULT "\0" \ 340 "partition=nand0,0\0" \ 341 "ramargs=setenv bootargs $(bootargs) $(mtdparts)\0" \ 342 "nfsargs=setenv bootargs root=/dev/nfs rw " \ 343 CONFIG_CON_ROT \ 344 "nfsroot=$(serverip):$(rootpath) $(mtdparts)\0" \ 345 "addip=setenv bootargs $(bootargs) " \ 346 "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask)"\ 347 ":$(hostname):eth0:off\0" \ 348 "ramboot=tftpboot 0x22000000 vmImage;" \ 349 "run ramargs;run addip;bootm 22000000\0" \ 350 "nfsboot=tftpboot 0x22000000 vmImage;" \ 351 "run nfsargs;run addip;bootm 22000000\0" \ 352 "flashboot=run ramargs;run addip;bootm 0x10050000\0" \ 353 "" 354 355 #else 356 #error "Undefined memory device" 357 #endif 358 359 #define CONFIG_BAUDRATE 115200 360 361 #define CONFIG_SYS_CBSIZE 256 362 #define CONFIG_SYS_MAXARGS 16 363 #define CONFIG_SYS_PBSIZE \ 364 (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) 365 #define CONFIG_SYS_LONGHELP 1 366 #define CONFIG_CMDLINE_EDITING 1 367 368 /* 369 * Size of malloc() pool 370 */ 371 #define CONFIG_SYS_MALLOC_LEN ROUND(3 * CONFIG_ENV_SIZE + 128 * 1024, 0x1000) 372 373 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM 374 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x1000 - \ 375 GENERATED_GBL_DATA_SIZE) 376 377 #endif 378