1 /* 2 * (C) Copyright 2007-2008 3 * Stelian Pop <stelian@popies.net> 4 * Lead Tech Design <www.leadtechdesign.com> 5 * Ilko Iliev <www.ronetix.at> 6 * 7 * Configuation settings for the RONETIX PM9263 board. 8 * 9 * SPDX-License-Identifier: GPL-2.0+ 10 */ 11 12 #ifndef __CONFIG_H 13 #define __CONFIG_H 14 15 /* 16 * SoC must be defined first, before hardware.h is included. 17 * In this case SoC is defined in boards.cfg. 18 */ 19 #include <asm/hardware.h> 20 21 22 /* ARM asynchronous clock */ 23 #define CONFIG_DISPLAY_CPUINFO 24 #define CONFIG_DISPLAY_BOARDINFO 25 26 #define MASTER_PLL_DIV 6 27 #define MASTER_PLL_MUL 65 28 #define MAIN_PLL_DIV 2 /* 2 or 4 */ 29 #define CONFIG_SYS_AT91_MAIN_CLOCK 18432000 30 #define CONFIG_SYS_AT91_SLOW_CLOCK 32768 /* slow clock xtal */ 31 32 #define CONFIG_SYS_AT91_CPU_NAME "AT91SAM9263" 33 #define CONFIG_PM9263 1 /* on a Ronetix PM9263 Board */ 34 #define CONFIG_ARCH_CPU_INIT 35 #define CONFIG_SYS_TEXT_BASE 0 36 37 #define MACH_TYPE_PM9263 1475 38 #define CONFIG_MACH_TYPE MACH_TYPE_PM9263 39 40 /* clocks */ 41 #define CONFIG_SYS_MOR_VAL \ 42 (AT91_PMC_MOR_MOSCEN | \ 43 (255 << 8)) /* Main Oscillator Start-up Time */ 44 #define CONFIG_SYS_PLLAR_VAL \ 45 (AT91_PMC_PLLAR_29 | /* Bit 29 must be 1 when prog */ \ 46 AT91_PMC_PLLXR_OUT(3) | \ 47 AT91_PMC_PLLXR_PLLCOUNT(0x3f) | /* PLL Counter */\ 48 (2 << 28) | /* PLL Clock Frequency Range */ \ 49 ((MASTER_PLL_MUL - 1) << 16) | (MASTER_PLL_DIV)) 50 51 #if (MAIN_PLL_DIV == 2) 52 /* PCK/2 = MCK Master Clock from PLLA */ 53 #define CONFIG_SYS_MCKR1_VAL \ 54 (AT91_PMC_MCKR_CSS_SLOW | \ 55 AT91_PMC_MCKR_PRES_1 | \ 56 AT91_PMC_MCKR_MDIV_2) 57 /* PCK/2 = MCK Master Clock from PLLA */ 58 #define CONFIG_SYS_MCKR2_VAL \ 59 (AT91_PMC_MCKR_CSS_PLLA | \ 60 AT91_PMC_MCKR_PRES_1 | \ 61 AT91_PMC_MCKR_MDIV_2) 62 #else 63 /* PCK/4 = MCK Master Clock from PLLA */ 64 #define CONFIG_SYS_MCKR1_VAL \ 65 (AT91_PMC_MCKR_CSS_SLOW | \ 66 AT91_PMC_MCKR_PRES_1 | \ 67 AT91_PMC_MCKR_MDIV_4) 68 /* PCK/4 = MCK Master Clock from PLLA */ 69 #define CONFIG_SYS_MCKR2_VAL \ 70 (AT91_PMC_MCKR_CSS_PLLA | \ 71 AT91_PMC_MCKR_PRES_1 | \ 72 AT91_PMC_MCKR_MDIV_4) 73 #endif 74 /* define PDC[31:16] as DATA[31:16] */ 75 #define CONFIG_SYS_PIOD_PDR_VAL1 0xFFFF0000 76 /* no pull-up for D[31:16] */ 77 #define CONFIG_SYS_PIOD_PPUDR_VAL 0xFFFF0000 78 /* EBI0_CSA, CS1 SDRAM, CS3 NAND Flash, 3.3V memories */ 79 #define CONFIG_SYS_MATRIX_EBI0CSA_VAL \ 80 (AT91_MATRIX_CSA_DBPUC | AT91_MATRIX_CSA_VDDIOMSEL_3_3V | \ 81 AT91_MATRIX_CSA_EBI_CS1A) 82 83 /* SDRAM */ 84 /* SDRAMC_MR Mode register */ 85 #define CONFIG_SYS_SDRC_MR_VAL1 0 86 /* SDRAMC_TR - Refresh Timer register */ 87 #define CONFIG_SYS_SDRC_TR_VAL1 0x3AA 88 /* SDRAMC_CR - Configuration register*/ 89 #define CONFIG_SYS_SDRC_CR_VAL \ 90 (AT91_SDRAMC_NC_9 | \ 91 AT91_SDRAMC_NR_13 | \ 92 AT91_SDRAMC_NB_4 | \ 93 AT91_SDRAMC_CAS_2 | \ 94 AT91_SDRAMC_DBW_32 | \ 95 (2 << 8) | /* tWR - Write Recovery Delay */ \ 96 (7 << 12) | /* tRC - Row Cycle Delay */ \ 97 (2 << 16) | /* tRP - Row Precharge Delay */ \ 98 (2 << 20) | /* tRCD - Row to Column Delay */ \ 99 (5 << 24) | /* tRAS - Active to Precharge Delay */ \ 100 (8 << 28)) /* tXSR - Exit Self Refresh to Active Delay */ 101 102 /* Memory Device Register -> SDRAM */ 103 #define CONFIG_SYS_SDRC_MDR_VAL AT91_SDRAMC_MD_SDRAM 104 #define CONFIG_SYS_SDRC_MR_VAL2 AT91_SDRAMC_MODE_PRECHARGE 105 #define CONFIG_SYS_SDRAM_VAL1 0 /* SDRAM_BASE */ 106 #define CONFIG_SYS_SDRC_MR_VAL3 AT91_SDRAMC_MODE_REFRESH 107 #define CONFIG_SYS_SDRAM_VAL2 0 /* SDRAM_BASE */ 108 #define CONFIG_SYS_SDRAM_VAL3 0 /* SDRAM_BASE */ 109 #define CONFIG_SYS_SDRAM_VAL4 0 /* SDRAM_BASE */ 110 #define CONFIG_SYS_SDRAM_VAL5 0 /* SDRAM_BASE */ 111 #define CONFIG_SYS_SDRAM_VAL6 0 /* SDRAM_BASE */ 112 #define CONFIG_SYS_SDRAM_VAL7 0 /* SDRAM_BASE */ 113 #define CONFIG_SYS_SDRAM_VAL8 0 /* SDRAM_BASE */ 114 #define CONFIG_SYS_SDRAM_VAL9 0 /* SDRAM_BASE */ 115 #define CONFIG_SYS_SDRC_MR_VAL4 AT91_SDRAMC_MODE_LMR 116 #define CONFIG_SYS_SDRAM_VAL10 0 /* SDRAM_BASE */ 117 #define CONFIG_SYS_SDRC_MR_VAL5 AT91_SDRAMC_MODE_NORMAL 118 #define CONFIG_SYS_SDRAM_VAL11 0 /* SDRAM_BASE */ 119 #define CONFIG_SYS_SDRC_TR_VAL2 1200 /* SDRAM_TR */ 120 #define CONFIG_SYS_SDRAM_VAL12 0 /* SDRAM_BASE */ 121 122 /* setup SMC0, CS0 (NOR Flash) - 16-bit, 15 WS */ 123 #define CONFIG_SYS_SMC0_SETUP0_VAL \ 124 (AT91_SMC_SETUP_NWE(10) | AT91_SMC_SETUP_NCS_WR(10) | \ 125 AT91_SMC_SETUP_NRD(10) | AT91_SMC_SETUP_NCS_RD(10)) 126 #define CONFIG_SYS_SMC0_PULSE0_VAL \ 127 (AT91_SMC_PULSE_NWE(11) | AT91_SMC_PULSE_NCS_WR(11) | \ 128 AT91_SMC_PULSE_NRD(11) | AT91_SMC_PULSE_NCS_RD(11)) 129 #define CONFIG_SYS_SMC0_CYCLE0_VAL \ 130 (AT91_SMC_CYCLE_NWE(22) | AT91_SMC_CYCLE_NRD(22)) 131 #define CONFIG_SYS_SMC0_MODE0_VAL \ 132 (AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE | \ 133 AT91_SMC_MODE_DBW_16 | \ 134 AT91_SMC_MODE_TDF | \ 135 AT91_SMC_MODE_TDF_CYCLE(6)) 136 137 /* user reset enable */ 138 #define CONFIG_SYS_RSTC_RMR_VAL \ 139 (AT91_RSTC_KEY | \ 140 AT91_RSTC_CR_PROCRST | \ 141 AT91_RSTC_MR_ERSTL(1) | \ 142 AT91_RSTC_MR_ERSTL(2)) 143 144 /* Disable Watchdog */ 145 #define CONFIG_SYS_WDTC_WDMR_VAL \ 146 (AT91_WDT_MR_WDIDLEHLT | AT91_WDT_MR_WDDBGHLT | \ 147 AT91_WDT_MR_WDV(0xfff) | \ 148 AT91_WDT_MR_WDDIS | \ 149 AT91_WDT_MR_WDD(0xfff)) 150 151 #define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ 152 #define CONFIG_SETUP_MEMORY_TAGS 1 153 #define CONFIG_INITRD_TAG 1 154 155 #undef CONFIG_SKIP_LOWLEVEL_INIT 156 #define CONFIG_USER_LOWLEVEL_INIT 1 157 #define CONFIG_BOARD_EARLY_INIT_F 158 159 /* 160 * Hardware drivers 161 */ 162 #define CONFIG_AT91_GPIO 1 163 #define CONFIG_ATMEL_USART 1 164 #define CONFIG_USART_BASE ATMEL_BASE_DBGU 165 #define CONFIG_USART_ID ATMEL_ID_SYS 166 167 /* LCD */ 168 #define CONFIG_LCD 1 169 #define LCD_BPP LCD_COLOR8 170 #define CONFIG_LCD_LOGO 1 171 #undef LCD_TEST_PATTERN 172 #define CONFIG_LCD_INFO 1 173 #define CONFIG_LCD_INFO_BELOW_LOGO 1 174 #define CONFIG_SYS_WHITE_ON_BLACK 1 175 #define CONFIG_ATMEL_LCD 1 176 #define CONFIG_ATMEL_LCD_BGR555 1 177 #define CONFIG_SYS_CONSOLE_IS_IN_ENV 1 178 179 #define CONFIG_LCD_IN_PSRAM 1 180 181 /* LED */ 182 #define CONFIG_AT91_LED 183 #define CONFIG_RED_LED GPIO_PIN_PB(7) /* this is the power led */ 184 #define CONFIG_GREEN_LED GPIO_PIN_PB(8) /* this is the user1 led */ 185 186 #define CONFIG_BOOTDELAY 3 187 188 /* 189 * BOOTP options 190 */ 191 #define CONFIG_BOOTP_BOOTFILESIZE 1 192 #define CONFIG_BOOTP_BOOTPATH 1 193 #define CONFIG_BOOTP_GATEWAY 1 194 #define CONFIG_BOOTP_HOSTNAME 1 195 196 /* 197 * Command line configuration. 198 */ 199 #define CONFIG_CMD_CACHE 200 #define CONFIG_CMD_PING 1 201 #define CONFIG_CMD_DHCP 1 202 #define CONFIG_CMD_NAND 1 203 #define CONFIG_CMD_USB 1 204 205 /* SDRAM */ 206 #define CONFIG_NR_DRAM_BANKS 1 207 #define PHYS_SDRAM 0x20000000 208 #define PHYS_SDRAM_SIZE 0x04000000 /* 64 megs */ 209 210 /* DataFlash */ 211 #define CONFIG_ATMEL_DATAFLASH_SPI 212 #define CONFIG_HAS_DATAFLASH 1 213 #define CONFIG_SYS_MAX_DATAFLASH_BANKS 1 214 #define CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0 0xC0000000 /* CS0 */ 215 #define AT91_SPI_CLK 15000000 216 #define DATAFLASH_TCSS (0x1a << 16) 217 #define DATAFLASH_TCHS (0x1 << 24) 218 219 /* NOR flash, if populated */ 220 #define CONFIG_SYS_FLASH_CFI 1 221 #define CONFIG_FLASH_CFI_DRIVER 1 222 #define PHYS_FLASH_1 0x10000000 223 #define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1 224 #define CONFIG_SYS_MAX_FLASH_SECT 256 225 #define CONFIG_SYS_MAX_FLASH_BANKS 1 226 227 /* NAND flash */ 228 #ifdef CONFIG_CMD_NAND 229 #define CONFIG_NAND_ATMEL 230 #define CONFIG_SYS_MAX_NAND_DEVICE 1 231 #define CONFIG_SYS_NAND_BASE 0x40000000 232 #define CONFIG_SYS_NAND_DBW_8 1 233 /* our ALE is AD21 */ 234 #define CONFIG_SYS_NAND_MASK_ALE (1 << 21) 235 /* our CLE is AD22 */ 236 #define CONFIG_SYS_NAND_MASK_CLE (1 << 22) 237 #define CONFIG_SYS_NAND_ENABLE_PIN GPIO_PIN_PD(15) 238 #define CONFIG_SYS_NAND_READY_PIN GPIO_PIN_PB(30) 239 240 #endif 241 242 #define CONFIG_CMD_JFFS2 1 243 #define CONFIG_JFFS2_CMDLINE 1 244 #define CONFIG_JFFS2_NAND 1 245 #define CONFIG_JFFS2_DEV "nand0" /* NAND device jffs2 lives on */ 246 #define CONFIG_JFFS2_PART_OFFSET 0 /* start of jffs2 partition */ 247 #define CONFIG_JFFS2_PART_SIZE (256 * 1024 * 1024) /* partition size*/ 248 249 /* PSRAM */ 250 #define PHYS_PSRAM 0x70000000 251 #define PHYS_PSRAM_SIZE 0x00400000 /* 4MB */ 252 /* Slave EBI1, PSRAM connected */ 253 #define CONFIG_PSRAM_SCFG (AT91_MATRIX_SCFG_ARBT_FIXED_PRIORITY | \ 254 AT91_MATRIX_SCFG_FIXED_DEFMSTR(5) | \ 255 AT91_MATRIX_SCFG_DEFMSTR_TYPE_FIXED | \ 256 AT91_MATRIX_SCFG_SLOT_CYCLE(255)) 257 258 /* Ethernet */ 259 #define CONFIG_MACB 1 260 #define CONFIG_RMII 1 261 #define CONFIG_NET_RETRY_COUNT 20 262 #define CONFIG_RESET_PHY_R 1 263 264 /* USB */ 265 #define CONFIG_USB_ATMEL 266 #define CONFIG_USB_ATMEL_CLK_SEL_PLLB 267 #define CONFIG_USB_OHCI_NEW 1 268 #define CONFIG_DOS_PARTITION 1 269 #define CONFIG_SYS_USB_OHCI_CPU_INIT 1 270 #define CONFIG_SYS_USB_OHCI_REGS_BASE 0x00a00000 /* AT91SAM9263_UHP_BASE */ 271 #define CONFIG_SYS_USB_OHCI_SLOT_NAME "at91sam9263" 272 #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2 273 #define CONFIG_USB_STORAGE 1 274 275 #define CONFIG_SYS_LOAD_ADDR 0x22000000 /* load address */ 276 277 #define CONFIG_SYS_MEMTEST_START PHYS_SDRAM 278 #define CONFIG_SYS_MEMTEST_END 0x23e00000 279 280 #define CONFIG_SYS_USE_FLASH 1 281 #undef CONFIG_SYS_USE_DATAFLASH 282 #undef CONFIG_SYS_USE_NANDFLASH 283 284 #ifdef CONFIG_SYS_USE_DATAFLASH 285 286 /* bootstrap + u-boot + env + linux in dataflash on CS0 */ 287 #define CONFIG_ENV_IS_IN_DATAFLASH 288 #define CFG_MONITOR_BASE (CFG_DATAFLASH_LOGIC_ADDR_CS0 + 0x8400) 289 #define CONFIG_ENV_OFFSET 0x4200 290 #define CONFIG_ENV_ADDR (CFG_DATAFLASH_LOGIC_ADDR_CS0 + CONFIG_ENV_OFFSET) 291 #define CONFIG_ENV_SIZE 0x4200 292 #define CONFIG_BOOTCOMMAND "cp.b 0xC0042000 0x22000000 0x210000; bootm" 293 #define CONFIG_BOOTARGS "console=ttyS0,115200 " \ 294 "root=/dev/mtdblock0 " \ 295 "mtdparts=atmel_nand:-(root) "\ 296 "rw rootfstype=jffs2" 297 298 #elif defined(CONFIG_SYS_USE_NANDFLASH) /* CFG_USE_NANDFLASH */ 299 300 /* bootstrap + u-boot + env + linux in nandflash */ 301 #define CONFIG_ENV_IS_IN_NAND 302 #define CONFIG_ENV_OFFSET 0x60000 303 #define CONFIG_ENV_OFFSET_REDUND 0x80000 304 #define CONFIG_ENV_SIZE 0x20000 /* 1 sector = 128 kB */ 305 #define CONFIG_BOOTCOMMAND "nand read 0x22000000 0xA0000 0x200000; bootm" 306 #define CONFIG_BOOTARGS "console=ttyS0,115200 " \ 307 "root=/dev/mtdblock5 " \ 308 "mtdparts=atmel_nand:" \ 309 "128k(bootstrap)ro," \ 310 "256k(uboot)ro," \ 311 "128k(env1)ro," \ 312 "128k(env2)ro," \ 313 "2M(linux)," \ 314 "-(root) " \ 315 "rw rootfstype=jffs2" 316 317 #elif defined(CONFIG_SYS_USE_FLASH) /* CFG_USE_FLASH */ 318 319 #define CONFIG_ENV_IS_IN_FLASH 1 320 #define CONFIG_ENV_OFFSET 0x40000 321 #define CONFIG_ENV_SECT_SIZE 0x10000 322 #define CONFIG_ENV_SIZE 0x10000 323 #define CONFIG_ENV_OVERWRITE 1 324 325 /* JFFS Partition offset set */ 326 #define CONFIG_SYS_JFFS2_FIRST_BANK 0 327 #define CONFIG_SYS_JFFS2_NUM_BANKS 1 328 329 /* 512k reserved for u-boot */ 330 #define CONFIG_SYS_JFFS2_FIRST_SECTOR 11 331 332 #define CONFIG_BOOTCOMMAND "run flashboot" 333 #define CONFIG_ROOTPATH "/ronetix/rootfs" 334 335 #define CONFIG_CON_ROT "fbcon=rotate:3 " 336 #define CONFIG_BOOTARGS "root=/dev/mtdblock4 rootfstype=jffs2 "\ 337 CONFIG_CON_ROT 338 339 #define MTDIDS_DEFAULT "nor0=physmap-flash.0,nand0=nand" 340 #define MTDPARTS_DEFAULT \ 341 "mtdparts=physmap-flash.0:" \ 342 "256k(u-boot)ro," \ 343 "64k(u-boot-env)ro," \ 344 "1408k(kernel)," \ 345 "-(rootfs);" \ 346 "nand:-(nand)" 347 348 #define CONFIG_EXTRA_ENV_SETTINGS \ 349 "mtdids=" MTDIDS_DEFAULT "\0" \ 350 "mtdparts=" MTDPARTS_DEFAULT "\0" \ 351 "partition=nand0,0\0" \ 352 "ramargs=setenv bootargs $(bootargs) $(mtdparts)\0" \ 353 "nfsargs=setenv bootargs root=/dev/nfs rw " \ 354 CONFIG_CON_ROT \ 355 "nfsroot=$(serverip):$(rootpath) $(mtdparts)\0" \ 356 "addip=setenv bootargs $(bootargs) " \ 357 "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask)"\ 358 ":$(hostname):eth0:off\0" \ 359 "ramboot=tftpboot 0x22000000 vmImage;" \ 360 "run ramargs;run addip;bootm 22000000\0" \ 361 "nfsboot=tftpboot 0x22000000 vmImage;" \ 362 "run nfsargs;run addip;bootm 22000000\0" \ 363 "flashboot=run ramargs;run addip;bootm 0x10050000\0" \ 364 "" 365 366 #else 367 #error "Undefined memory device" 368 #endif 369 370 #define CONFIG_BAUDRATE 115200 371 372 #define CONFIG_SYS_CBSIZE 256 373 #define CONFIG_SYS_MAXARGS 16 374 #define CONFIG_SYS_PBSIZE \ 375 (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) 376 #define CONFIG_SYS_LONGHELP 1 377 #define CONFIG_CMDLINE_EDITING 1 378 379 /* 380 * Size of malloc() pool 381 */ 382 #define CONFIG_SYS_MALLOC_LEN ROUND(3 * CONFIG_ENV_SIZE + 128 * 1024, 0x1000) 383 384 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM 385 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x1000 - \ 386 GENERATED_GBL_DATA_SIZE) 387 388 #endif 389