1 /* 2 * (C) Copyright 2007-2008 3 * Stelian Pop <stelian@popies.net> 4 * Lead Tech Design <www.leadtechdesign.com> 5 * Ilko Iliev <www.ronetix.at> 6 * 7 * Configuation settings for the RONETIX PM9263 board. 8 * 9 * See file CREDITS for list of people who contributed to this 10 * project. 11 * 12 * This program is free software; you can redistribute it and/or 13 * modify it under the terms of the GNU General Public License as 14 * published by the Free Software Foundation; either version 2 of 15 * the License, or (at your option) any later version. 16 * 17 * This program is distributed in the hope that it will be useful, 18 * but WITHOUT ANY WARRANTY; without even the implied warranty of 19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 20 * GNU General Public License for more details. 21 * 22 * You should have received a copy of the GNU General Public License 23 * along with this program; if not, write to the Free Software 24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 25 * MA 02111-1307 USA 26 */ 27 28 #ifndef __CONFIG_H 29 #define __CONFIG_H 30 31 /* 32 * SoC must be defined first, before hardware.h is included. 33 * In this case SoC is defined in boards.cfg. 34 */ 35 #include <asm/hardware.h> 36 37 /* ARM asynchronous clock */ 38 #define CONFIG_DISPLAY_CPUINFO 39 #define CONFIG_DISPLAY_BOARDINFO 40 41 #define MASTER_PLL_DIV 6 42 #define MASTER_PLL_MUL 65 43 #define MAIN_PLL_DIV 2 /* 2 or 4 */ 44 #define CONFIG_SYS_AT91_MAIN_CLOCK 18432000 45 #define CONFIG_SYS_AT91_SLOW_CLOCK 32768 /* slow clock xtal */ 46 47 #define CONFIG_SYS_HZ 1000 48 49 #define CONFIG_SYS_AT91_CPU_NAME "AT91SAM9263" 50 #define CONFIG_PM9263 1 /* on a Ronetix PM9263 Board */ 51 #define CONFIG_ARCH_CPU_INIT 52 #undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */ 53 #define CONFIG_SYS_TEXT_BASE 0 54 55 #define MACH_TYPE_PM9263 1475 56 #define CONFIG_MACH_TYPE MACH_TYPE_PM9263 57 58 /* clocks */ 59 #define CONFIG_SYS_MOR_VAL \ 60 (AT91_PMC_MOR_MOSCEN | \ 61 (255 << 8)) /* Main Oscillator Start-up Time */ 62 #define CONFIG_SYS_PLLAR_VAL \ 63 (AT91_PMC_PLLAR_29 | /* Bit 29 must be 1 when prog */ \ 64 AT91_PMC_PLLXR_OUT(3) | \ 65 AT91_PMC_PLLXR_PLLCOUNT(0x3f) | /* PLL Counter */\ 66 (2 << 28) | /* PLL Clock Frequency Range */ \ 67 ((MASTER_PLL_MUL - 1) << 16) | (MASTER_PLL_DIV)) 68 69 #if (MAIN_PLL_DIV == 2) 70 /* PCK/2 = MCK Master Clock from PLLA */ 71 #define CONFIG_SYS_MCKR1_VAL \ 72 (AT91_PMC_MCKR_CSS_SLOW | \ 73 AT91_PMC_MCKR_PRES_1 | \ 74 AT91_PMC_MCKR_MDIV_2) 75 /* PCK/2 = MCK Master Clock from PLLA */ 76 #define CONFIG_SYS_MCKR2_VAL \ 77 (AT91_PMC_MCKR_CSS_PLLA | \ 78 AT91_PMC_MCKR_PRES_1 | \ 79 AT91_PMC_MCKR_MDIV_2) 80 #else 81 /* PCK/4 = MCK Master Clock from PLLA */ 82 #define CONFIG_SYS_MCKR1_VAL \ 83 (AT91_PMC_MCKR_CSS_SLOW | \ 84 AT91_PMC_MCKR_PRES_1 | \ 85 AT91_PMC_MCKR_MDIV_4) 86 /* PCK/4 = MCK Master Clock from PLLA */ 87 #define CONFIG_SYS_MCKR2_VAL \ 88 (AT91_PMC_MCKR_CSS_PLLA | \ 89 AT91_PMC_MCKR_PRES_1 | \ 90 AT91_PMC_MCKR_MDIV_4) 91 #endif 92 /* define PDC[31:16] as DATA[31:16] */ 93 #define CONFIG_SYS_PIOD_PDR_VAL1 0xFFFF0000 94 /* no pull-up for D[31:16] */ 95 #define CONFIG_SYS_PIOD_PPUDR_VAL 0xFFFF0000 96 /* EBI0_CSA, CS1 SDRAM, CS3 NAND Flash, 3.3V memories */ 97 #define CONFIG_SYS_MATRIX_EBI0CSA_VAL \ 98 (AT91_MATRIX_CSA_DBPUC | AT91_MATRIX_CSA_VDDIOMSEL_3_3V | \ 99 AT91_MATRIX_CSA_EBI_CS1A) 100 101 /* SDRAM */ 102 /* SDRAMC_MR Mode register */ 103 #define CONFIG_SYS_SDRC_MR_VAL1 0 104 /* SDRAMC_TR - Refresh Timer register */ 105 #define CONFIG_SYS_SDRC_TR_VAL1 0x3AA 106 /* SDRAMC_CR - Configuration register*/ 107 #define CONFIG_SYS_SDRC_CR_VAL \ 108 (AT91_SDRAMC_NC_9 | \ 109 AT91_SDRAMC_NR_13 | \ 110 AT91_SDRAMC_NB_4 | \ 111 AT91_SDRAMC_CAS_2 | \ 112 AT91_SDRAMC_DBW_32 | \ 113 (2 << 8) | /* tWR - Write Recovery Delay */ \ 114 (7 << 12) | /* tRC - Row Cycle Delay */ \ 115 (2 << 16) | /* tRP - Row Precharge Delay */ \ 116 (2 << 20) | /* tRCD - Row to Column Delay */ \ 117 (5 << 24) | /* tRAS - Active to Precharge Delay */ \ 118 (8 << 28)) /* tXSR - Exit Self Refresh to Active Delay */ 119 120 /* Memory Device Register -> SDRAM */ 121 #define CONFIG_SYS_SDRC_MDR_VAL AT91_SDRAMC_MD_SDRAM 122 #define CONFIG_SYS_SDRC_MR_VAL2 AT91_SDRAMC_MODE_PRECHARGE 123 #define CONFIG_SYS_SDRAM_VAL1 0 /* SDRAM_BASE */ 124 #define CONFIG_SYS_SDRC_MR_VAL3 AT91_SDRAMC_MODE_REFRESH 125 #define CONFIG_SYS_SDRAM_VAL2 0 /* SDRAM_BASE */ 126 #define CONFIG_SYS_SDRAM_VAL3 0 /* SDRAM_BASE */ 127 #define CONFIG_SYS_SDRAM_VAL4 0 /* SDRAM_BASE */ 128 #define CONFIG_SYS_SDRAM_VAL5 0 /* SDRAM_BASE */ 129 #define CONFIG_SYS_SDRAM_VAL6 0 /* SDRAM_BASE */ 130 #define CONFIG_SYS_SDRAM_VAL7 0 /* SDRAM_BASE */ 131 #define CONFIG_SYS_SDRAM_VAL8 0 /* SDRAM_BASE */ 132 #define CONFIG_SYS_SDRAM_VAL9 0 /* SDRAM_BASE */ 133 #define CONFIG_SYS_SDRC_MR_VAL4 AT91_SDRAMC_MODE_LMR 134 #define CONFIG_SYS_SDRAM_VAL10 0 /* SDRAM_BASE */ 135 #define CONFIG_SYS_SDRC_MR_VAL5 AT91_SDRAMC_MODE_NORMAL 136 #define CONFIG_SYS_SDRAM_VAL11 0 /* SDRAM_BASE */ 137 #define CONFIG_SYS_SDRC_TR_VAL2 1200 /* SDRAM_TR */ 138 #define CONFIG_SYS_SDRAM_VAL12 0 /* SDRAM_BASE */ 139 140 /* setup SMC0, CS0 (NOR Flash) - 16-bit, 15 WS */ 141 #define CONFIG_SYS_SMC0_SETUP0_VAL \ 142 (AT91_SMC_SETUP_NWE(10) | AT91_SMC_SETUP_NCS_WR(10) | \ 143 AT91_SMC_SETUP_NRD(10) | AT91_SMC_SETUP_NCS_RD(10)) 144 #define CONFIG_SYS_SMC0_PULSE0_VAL \ 145 (AT91_SMC_PULSE_NWE(11) | AT91_SMC_PULSE_NCS_WR(11) | \ 146 AT91_SMC_PULSE_NRD(11) | AT91_SMC_PULSE_NCS_RD(11)) 147 #define CONFIG_SYS_SMC0_CYCLE0_VAL \ 148 (AT91_SMC_CYCLE_NWE(22) | AT91_SMC_CYCLE_NRD(22)) 149 #define CONFIG_SYS_SMC0_MODE0_VAL \ 150 (AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE | \ 151 AT91_SMC_MODE_DBW_16 | \ 152 AT91_SMC_MODE_TDF | \ 153 AT91_SMC_MODE_TDF_CYCLE(6)) 154 155 /* user reset enable */ 156 #define CONFIG_SYS_RSTC_RMR_VAL \ 157 (AT91_RSTC_KEY | \ 158 AT91_RSTC_CR_PROCRST | \ 159 AT91_RSTC_MR_ERSTL(1) | \ 160 AT91_RSTC_MR_ERSTL(2)) 161 162 /* Disable Watchdog */ 163 #define CONFIG_SYS_WDTC_WDMR_VAL \ 164 (AT91_WDT_MR_WDIDLEHLT | AT91_WDT_MR_WDDBGHLT | \ 165 AT91_WDT_MR_WDV(0xfff) | \ 166 AT91_WDT_MR_WDDIS | \ 167 AT91_WDT_MR_WDD(0xfff)) 168 169 #define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ 170 #define CONFIG_SETUP_MEMORY_TAGS 1 171 #define CONFIG_INITRD_TAG 1 172 173 #undef CONFIG_SKIP_LOWLEVEL_INIT 174 #define CONFIG_USER_LOWLEVEL_INIT 1 175 #define CONFIG_BOARD_EARLY_INIT_F 176 177 /* 178 * Hardware drivers 179 */ 180 #define CONFIG_AT91_GPIO 1 181 #define CONFIG_ATMEL_USART 1 182 #define CONFIG_USART_BASE ATMEL_BASE_DBGU 183 #define CONFIG_USART_ID ATMEL_ID_SYS 184 185 /* LCD */ 186 #define CONFIG_LCD 1 187 #define LCD_BPP LCD_COLOR8 188 #define CONFIG_LCD_LOGO 1 189 #undef LCD_TEST_PATTERN 190 #define CONFIG_LCD_INFO 1 191 #define CONFIG_LCD_INFO_BELOW_LOGO 1 192 #define CONFIG_SYS_WHITE_ON_BLACK 1 193 #define CONFIG_ATMEL_LCD 1 194 #define CONFIG_ATMEL_LCD_BGR555 1 195 #define CONFIG_SYS_CONSOLE_IS_IN_ENV 1 196 197 #define CONFIG_LCD_IN_PSRAM 1 198 199 /* LED */ 200 #define CONFIG_AT91_LED 201 #define CONFIG_RED_LED AT91_PIO_PORTB, 7 /* this is the power led */ 202 #define CONFIG_GREEN_LED AT91_PIO_PORTB, 8 /* this is the user1 led */ 203 204 #define CONFIG_BOOTDELAY 3 205 206 /* 207 * BOOTP options 208 */ 209 #define CONFIG_BOOTP_BOOTFILESIZE 1 210 #define CONFIG_BOOTP_BOOTPATH 1 211 #define CONFIG_BOOTP_GATEWAY 1 212 #define CONFIG_BOOTP_HOSTNAME 1 213 214 /* 215 * Command line configuration. 216 */ 217 #include <config_cmd_default.h> 218 #undef CONFIG_CMD_BDI 219 #undef CONFIG_CMD_IMI 220 #undef CONFIG_CMD_FPGA 221 #undef CONFIG_CMD_LOADS 222 #undef CONFIG_CMD_IMLS 223 224 #define CONFIG_CMD_CACHE 225 #define CONFIG_CMD_PING 1 226 #define CONFIG_CMD_DHCP 1 227 #define CONFIG_CMD_NAND 1 228 #define CONFIG_CMD_USB 1 229 230 /* SDRAM */ 231 #define CONFIG_NR_DRAM_BANKS 1 232 #define PHYS_SDRAM 0x20000000 233 #define PHYS_SDRAM_SIZE 0x04000000 /* 64 megs */ 234 235 /* DataFlash */ 236 #define CONFIG_ATMEL_DATAFLASH_SPI 237 #define CONFIG_HAS_DATAFLASH 1 238 #define CONFIG_SYS_SPI_WRITE_TOUT (5 * CONFIG_SYS_HZ) 239 #define CONFIG_SYS_MAX_DATAFLASH_BANKS 1 240 #define CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0 0xC0000000 /* CS0 */ 241 #define AT91_SPI_CLK 15000000 242 #define DATAFLASH_TCSS (0x1a << 16) 243 #define DATAFLASH_TCHS (0x1 << 24) 244 245 /* NOR flash, if populated */ 246 #define CONFIG_SYS_FLASH_CFI 1 247 #define CONFIG_FLASH_CFI_DRIVER 1 248 #define PHYS_FLASH_1 0x10000000 249 #define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1 250 #define CONFIG_SYS_MAX_FLASH_SECT 256 251 #define CONFIG_SYS_MAX_FLASH_BANKS 1 252 253 /* NAND flash */ 254 #ifdef CONFIG_CMD_NAND 255 #define CONFIG_NAND_ATMEL 256 #define CONFIG_SYS_MAX_NAND_DEVICE 1 257 #define CONFIG_SYS_NAND_BASE 0x40000000 258 #define CONFIG_SYS_NAND_DBW_8 1 259 /* our ALE is AD21 */ 260 #define CONFIG_SYS_NAND_MASK_ALE (1 << 21) 261 /* our CLE is AD22 */ 262 #define CONFIG_SYS_NAND_MASK_CLE (1 << 22) 263 #define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIO_PORTD, 15 264 #define CONFIG_SYS_NAND_READY_PIN AT91_PIO_PORTB, 30 265 266 #endif 267 268 #define CONFIG_CMD_JFFS2 1 269 #define CONFIG_JFFS2_CMDLINE 1 270 #define CONFIG_JFFS2_NAND 1 271 #define CONFIG_JFFS2_DEV "nand0" /* NAND device jffs2 lives on */ 272 #define CONFIG_JFFS2_PART_OFFSET 0 /* start of jffs2 partition */ 273 #define CONFIG_JFFS2_PART_SIZE (256 * 1024 * 1024) /* partition size*/ 274 275 /* PSRAM */ 276 #define PHYS_PSRAM 0x70000000 277 #define PHYS_PSRAM_SIZE 0x00400000 /* 4MB */ 278 /* Slave EBI1, PSRAM connected */ 279 #define CONFIG_PSRAM_SCFG (AT91_MATRIX_SCFG_ARBT_FIXED_PRIORITY | \ 280 AT91_MATRIX_SCFG_FIXED_DEFMSTR(5) | \ 281 AT91_MATRIX_SCFG_DEFMSTR_TYPE_FIXED | \ 282 AT91_MATRIX_SCFG_SLOT_CYCLE(255)) 283 284 /* Ethernet */ 285 #define CONFIG_MACB 1 286 #define CONFIG_RMII 1 287 #define CONFIG_NET_RETRY_COUNT 20 288 #define CONFIG_RESET_PHY_R 1 289 290 /* USB */ 291 #define CONFIG_USB_ATMEL 292 #define CONFIG_USB_OHCI_NEW 1 293 #define CONFIG_DOS_PARTITION 1 294 #define CONFIG_SYS_USB_OHCI_CPU_INIT 1 295 #define CONFIG_SYS_USB_OHCI_REGS_BASE 0x00a00000 /* AT91SAM9263_UHP_BASE */ 296 #define CONFIG_SYS_USB_OHCI_SLOT_NAME "at91sam9263" 297 #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2 298 #define CONFIG_USB_STORAGE 1 299 300 #define CONFIG_SYS_LOAD_ADDR 0x22000000 /* load address */ 301 302 #define CONFIG_SYS_MEMTEST_START PHYS_SDRAM 303 #define CONFIG_SYS_MEMTEST_END 0x23e00000 304 305 #define CONFIG_SYS_USE_FLASH 1 306 #undef CONFIG_SYS_USE_DATAFLASH 307 #undef CONFIG_SYS_USE_NANDFLASH 308 309 #ifdef CONFIG_SYS_USE_DATAFLASH 310 311 /* bootstrap + u-boot + env + linux in dataflash on CS0 */ 312 #define CONFIG_ENV_IS_IN_DATAFLASH 313 #define CFG_MONITOR_BASE (CFG_DATAFLASH_LOGIC_ADDR_CS0 + 0x8400) 314 #define CONFIG_ENV_OFFSET 0x4200 315 #define CONFIG_ENV_ADDR (CFG_DATAFLASH_LOGIC_ADDR_CS0 + CONFIG_ENV_OFFSET) 316 #define CONFIG_ENV_SIZE 0x4200 317 #define CONFIG_BOOTCOMMAND "cp.b 0xC0042000 0x22000000 0x210000; bootm" 318 #define CONFIG_BOOTARGS "console=ttyS0,115200 " \ 319 "root=/dev/mtdblock0 " \ 320 "mtdparts=atmel_nand:-(root) "\ 321 "rw rootfstype=jffs2" 322 323 #elif defined(CONFIG_SYS_USE_NANDFLASH) /* CFG_USE_NANDFLASH */ 324 325 /* bootstrap + u-boot + env + linux in nandflash */ 326 #define CONFIG_ENV_IS_IN_NAND 327 #define CONFIG_ENV_OFFSET 0x60000 328 #define CONFIG_ENV_OFFSET_REDUND 0x80000 329 #define CONFIG_ENV_SIZE 0x20000 /* 1 sector = 128 kB */ 330 #define CONFIG_BOOTCOMMAND "nand read 0x22000000 0xA0000 0x200000; bootm" 331 #define CONFIG_BOOTARGS "console=ttyS0,115200 " \ 332 "root=/dev/mtdblock5 " \ 333 "mtdparts=atmel_nand:" \ 334 "128k(bootstrap)ro," \ 335 "256k(uboot)ro," \ 336 "128k(env1)ro," \ 337 "128k(env2)ro," \ 338 "2M(linux)," \ 339 "-(root) " \ 340 "rw rootfstype=jffs2" 341 342 #elif defined(CONFIG_SYS_USE_FLASH) /* CFG_USE_FLASH */ 343 344 #define CONFIG_ENV_IS_IN_FLASH 1 345 #define CONFIG_ENV_OFFSET 0x40000 346 #define CONFIG_ENV_SECT_SIZE 0x10000 347 #define CONFIG_ENV_SIZE 0x10000 348 #define CONFIG_ENV_OVERWRITE 1 349 350 /* JFFS Partition offset set */ 351 #define CONFIG_SYS_JFFS2_FIRST_BANK 0 352 #define CONFIG_SYS_JFFS2_NUM_BANKS 1 353 354 /* 512k reserved for u-boot */ 355 #define CONFIG_SYS_JFFS2_FIRST_SECTOR 11 356 357 #define CONFIG_BOOTCOMMAND "run flashboot" 358 #define CONFIG_ROOTPATH "/ronetix/rootfs" 359 #define CONFIG_AUTOBOOT_PROMPT "autoboot in %d seconds\n" 360 361 #define CONFIG_CON_ROT "fbcon=rotate:3 " 362 #define CONFIG_BOOTARGS "root=/dev/mtdblock4 rootfstype=jffs2 "\ 363 CONFIG_CON_ROT 364 365 #define MTDIDS_DEFAULT "nor0=physmap-flash.0,nand0=nand" 366 #define MTDPARTS_DEFAULT \ 367 "mtdparts=physmap-flash.0:" \ 368 "256k(u-boot)ro," \ 369 "64k(u-boot-env)ro," \ 370 "1408k(kernel)," \ 371 "-(rootfs);" \ 372 "nand:-(nand)" 373 374 #define CONFIG_EXTRA_ENV_SETTINGS \ 375 "mtdids=" MTDIDS_DEFAULT "\0" \ 376 "mtdparts=" MTDPARTS_DEFAULT "\0" \ 377 "partition=nand0,0\0" \ 378 "ramargs=setenv bootargs $(bootargs) $(mtdparts)\0" \ 379 "nfsargs=setenv bootargs root=/dev/nfs rw " \ 380 CONFIG_CON_ROT \ 381 "nfsroot=$(serverip):$(rootpath) $(mtdparts)\0" \ 382 "addip=setenv bootargs $(bootargs) " \ 383 "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask)"\ 384 ":$(hostname):eth0:off\0" \ 385 "ramboot=tftpboot 0x22000000 vmImage;" \ 386 "run ramargs;run addip;bootm 22000000\0" \ 387 "nfsboot=tftpboot 0x22000000 vmImage;" \ 388 "run nfsargs;run addip;bootm 22000000\0" \ 389 "flashboot=run ramargs;run addip;bootm 0x10050000\0" \ 390 "" 391 392 #else 393 #error "Undefined memory device" 394 #endif 395 396 #define CONFIG_BAUDRATE 115200 397 398 #define CONFIG_SYS_PROMPT "u-boot-pm9263> " 399 #define CONFIG_SYS_CBSIZE 256 400 #define CONFIG_SYS_MAXARGS 16 401 #define CONFIG_SYS_PBSIZE \ 402 (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) 403 #define CONFIG_SYS_LONGHELP 1 404 #define CONFIG_CMDLINE_EDITING 1 405 406 /* 407 * Size of malloc() pool 408 */ 409 #define CONFIG_SYS_MALLOC_LEN ROUND(3 * CONFIG_ENV_SIZE + 128 * 1024, 0x1000) 410 411 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM 412 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x1000 - \ 413 GENERATED_GBL_DATA_SIZE) 414 415 #define CONFIG_STACKSIZE (32 * 1024) /* regular stack */ 416 417 #ifdef CONFIG_USE_IRQ 418 #error CONFIG_USE_IRQ not supported 419 #endif 420 421 #endif 422