1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * (C) Copyright 2007-2008 4 * Stelian Pop <stelian@popies.net> 5 * Lead Tech Design <www.leadtechdesign.com> 6 * Ilko Iliev <www.ronetix.at> 7 * 8 * Configuation settings for the RONETIX PM9263 board. 9 */ 10 11 #ifndef __CONFIG_H 12 #define __CONFIG_H 13 14 /* 15 * SoC must be defined first, before hardware.h is included. 16 * In this case SoC is defined in boards.cfg. 17 */ 18 #include <asm/hardware.h> 19 20 /* ARM asynchronous clock */ 21 22 #define MASTER_PLL_DIV 6 23 #define MASTER_PLL_MUL 65 24 #define MAIN_PLL_DIV 2 /* 2 or 4 */ 25 #define CONFIG_SYS_AT91_MAIN_CLOCK 18432000 26 #define CONFIG_SYS_AT91_SLOW_CLOCK 32768 /* slow clock xtal */ 27 28 #define CONFIG_SYS_AT91_CPU_NAME "AT91SAM9263" 29 #define CONFIG_ARCH_CPU_INIT 30 31 #define CONFIG_MACH_TYPE MACH_TYPE_PM9263 32 33 /* clocks */ 34 #define CONFIG_SYS_MOR_VAL \ 35 (AT91_PMC_MOR_MOSCEN | \ 36 (255 << 8)) /* Main Oscillator Start-up Time */ 37 #define CONFIG_SYS_PLLAR_VAL \ 38 (AT91_PMC_PLLAR_29 | /* Bit 29 must be 1 when prog */ \ 39 AT91_PMC_PLLXR_OUT(3) | \ 40 AT91_PMC_PLLXR_PLLCOUNT(0x3f) | /* PLL Counter */\ 41 (2 << 28) | /* PLL Clock Frequency Range */ \ 42 ((MASTER_PLL_MUL - 1) << 16) | (MASTER_PLL_DIV)) 43 44 #if (MAIN_PLL_DIV == 2) 45 /* PCK/2 = MCK Master Clock from PLLA */ 46 #define CONFIG_SYS_MCKR1_VAL \ 47 (AT91_PMC_MCKR_CSS_SLOW | \ 48 AT91_PMC_MCKR_PRES_1 | \ 49 AT91_PMC_MCKR_MDIV_2) 50 /* PCK/2 = MCK Master Clock from PLLA */ 51 #define CONFIG_SYS_MCKR2_VAL \ 52 (AT91_PMC_MCKR_CSS_PLLA | \ 53 AT91_PMC_MCKR_PRES_1 | \ 54 AT91_PMC_MCKR_MDIV_2) 55 #else 56 /* PCK/4 = MCK Master Clock from PLLA */ 57 #define CONFIG_SYS_MCKR1_VAL \ 58 (AT91_PMC_MCKR_CSS_SLOW | \ 59 AT91_PMC_MCKR_PRES_1 | \ 60 AT91_PMC_MCKR_MDIV_4) 61 /* PCK/4 = MCK Master Clock from PLLA */ 62 #define CONFIG_SYS_MCKR2_VAL \ 63 (AT91_PMC_MCKR_CSS_PLLA | \ 64 AT91_PMC_MCKR_PRES_1 | \ 65 AT91_PMC_MCKR_MDIV_4) 66 #endif 67 /* define PDC[31:16] as DATA[31:16] */ 68 #define CONFIG_SYS_PIOD_PDR_VAL1 0xFFFF0000 69 /* no pull-up for D[31:16] */ 70 #define CONFIG_SYS_PIOD_PPUDR_VAL 0xFFFF0000 71 /* EBI0_CSA, CS1 SDRAM, CS3 NAND Flash, 3.3V memories */ 72 #define CONFIG_SYS_MATRIX_EBI0CSA_VAL \ 73 (AT91_MATRIX_CSA_DBPUC | AT91_MATRIX_CSA_VDDIOMSEL_3_3V | \ 74 AT91_MATRIX_CSA_EBI_CS1A) 75 76 /* SDRAM */ 77 /* SDRAMC_MR Mode register */ 78 #define CONFIG_SYS_SDRC_MR_VAL1 0 79 /* SDRAMC_TR - Refresh Timer register */ 80 #define CONFIG_SYS_SDRC_TR_VAL1 0x3AA 81 /* SDRAMC_CR - Configuration register*/ 82 #define CONFIG_SYS_SDRC_CR_VAL \ 83 (AT91_SDRAMC_NC_9 | \ 84 AT91_SDRAMC_NR_13 | \ 85 AT91_SDRAMC_NB_4 | \ 86 AT91_SDRAMC_CAS_2 | \ 87 AT91_SDRAMC_DBW_32 | \ 88 (2 << 8) | /* tWR - Write Recovery Delay */ \ 89 (7 << 12) | /* tRC - Row Cycle Delay */ \ 90 (2 << 16) | /* tRP - Row Precharge Delay */ \ 91 (2 << 20) | /* tRCD - Row to Column Delay */ \ 92 (5 << 24) | /* tRAS - Active to Precharge Delay */ \ 93 (8 << 28)) /* tXSR - Exit Self Refresh to Active Delay */ 94 95 /* Memory Device Register -> SDRAM */ 96 #define CONFIG_SYS_SDRC_MDR_VAL AT91_SDRAMC_MD_SDRAM 97 #define CONFIG_SYS_SDRC_MR_VAL2 AT91_SDRAMC_MODE_PRECHARGE 98 #define CONFIG_SYS_SDRAM_VAL1 0 /* SDRAM_BASE */ 99 #define CONFIG_SYS_SDRC_MR_VAL3 AT91_SDRAMC_MODE_REFRESH 100 #define CONFIG_SYS_SDRAM_VAL2 0 /* SDRAM_BASE */ 101 #define CONFIG_SYS_SDRAM_VAL3 0 /* SDRAM_BASE */ 102 #define CONFIG_SYS_SDRAM_VAL4 0 /* SDRAM_BASE */ 103 #define CONFIG_SYS_SDRAM_VAL5 0 /* SDRAM_BASE */ 104 #define CONFIG_SYS_SDRAM_VAL6 0 /* SDRAM_BASE */ 105 #define CONFIG_SYS_SDRAM_VAL7 0 /* SDRAM_BASE */ 106 #define CONFIG_SYS_SDRAM_VAL8 0 /* SDRAM_BASE */ 107 #define CONFIG_SYS_SDRAM_VAL9 0 /* SDRAM_BASE */ 108 #define CONFIG_SYS_SDRC_MR_VAL4 AT91_SDRAMC_MODE_LMR 109 #define CONFIG_SYS_SDRAM_VAL10 0 /* SDRAM_BASE */ 110 #define CONFIG_SYS_SDRC_MR_VAL5 AT91_SDRAMC_MODE_NORMAL 111 #define CONFIG_SYS_SDRAM_VAL11 0 /* SDRAM_BASE */ 112 #define CONFIG_SYS_SDRC_TR_VAL2 1200 /* SDRAM_TR */ 113 #define CONFIG_SYS_SDRAM_VAL12 0 /* SDRAM_BASE */ 114 115 /* setup SMC0, CS0 (NOR Flash) - 16-bit, 15 WS */ 116 #define CONFIG_SYS_SMC0_SETUP0_VAL \ 117 (AT91_SMC_SETUP_NWE(10) | AT91_SMC_SETUP_NCS_WR(10) | \ 118 AT91_SMC_SETUP_NRD(10) | AT91_SMC_SETUP_NCS_RD(10)) 119 #define CONFIG_SYS_SMC0_PULSE0_VAL \ 120 (AT91_SMC_PULSE_NWE(11) | AT91_SMC_PULSE_NCS_WR(11) | \ 121 AT91_SMC_PULSE_NRD(11) | AT91_SMC_PULSE_NCS_RD(11)) 122 #define CONFIG_SYS_SMC0_CYCLE0_VAL \ 123 (AT91_SMC_CYCLE_NWE(22) | AT91_SMC_CYCLE_NRD(22)) 124 #define CONFIG_SYS_SMC0_MODE0_VAL \ 125 (AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE | \ 126 AT91_SMC_MODE_DBW_16 | \ 127 AT91_SMC_MODE_TDF | \ 128 AT91_SMC_MODE_TDF_CYCLE(6)) 129 130 /* user reset enable */ 131 #define CONFIG_SYS_RSTC_RMR_VAL \ 132 (AT91_RSTC_KEY | \ 133 AT91_RSTC_CR_PROCRST | \ 134 AT91_RSTC_MR_ERSTL(1) | \ 135 AT91_RSTC_MR_ERSTL(2)) 136 137 /* Disable Watchdog */ 138 #define CONFIG_SYS_WDTC_WDMR_VAL \ 139 (AT91_WDT_MR_WDIDLEHLT | AT91_WDT_MR_WDDBGHLT | \ 140 AT91_WDT_MR_WDV(0xfff) | \ 141 AT91_WDT_MR_WDDIS | \ 142 AT91_WDT_MR_WDD(0xfff)) 143 144 #define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ 145 #define CONFIG_SETUP_MEMORY_TAGS 1 146 #define CONFIG_INITRD_TAG 1 147 148 #undef CONFIG_SKIP_LOWLEVEL_INIT 149 #define CONFIG_USER_LOWLEVEL_INIT 1 150 151 /* 152 * Hardware drivers 153 */ 154 /* LCD */ 155 #define LCD_BPP LCD_COLOR8 156 #define CONFIG_LCD_LOGO 1 157 #undef LCD_TEST_PATTERN 158 #define CONFIG_LCD_INFO 1 159 #define CONFIG_LCD_INFO_BELOW_LOGO 1 160 #define CONFIG_ATMEL_LCD 1 161 #define CONFIG_ATMEL_LCD_BGR555 1 162 163 #define CONFIG_LCD_IN_PSRAM 1 164 165 /* 166 * BOOTP options 167 */ 168 #define CONFIG_BOOTP_BOOTFILESIZE 1 169 170 /* SDRAM */ 171 #define PHYS_SDRAM 0x20000000 172 #define PHYS_SDRAM_SIZE 0x04000000 /* 64 megs */ 173 174 /* NOR flash, if populated */ 175 #define PHYS_FLASH_1 0x10000000 176 #define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1 177 #define CONFIG_SYS_MAX_FLASH_SECT 256 178 #define CONFIG_SYS_MAX_FLASH_BANKS 1 179 180 /* NAND flash */ 181 #ifdef CONFIG_CMD_NAND 182 #define CONFIG_SYS_MAX_NAND_DEVICE 1 183 #define CONFIG_SYS_NAND_BASE 0x40000000 184 #define CONFIG_SYS_NAND_DBW_8 1 185 /* our ALE is AD21 */ 186 #define CONFIG_SYS_NAND_MASK_ALE (1 << 21) 187 /* our CLE is AD22 */ 188 #define CONFIG_SYS_NAND_MASK_CLE (1 << 22) 189 #define CONFIG_SYS_NAND_ENABLE_PIN GPIO_PIN_PD(15) 190 #define CONFIG_SYS_NAND_READY_PIN GPIO_PIN_PB(30) 191 192 #endif 193 194 #define CONFIG_JFFS2_CMDLINE 1 195 #define CONFIG_JFFS2_NAND 1 196 #define CONFIG_JFFS2_DEV "nand0" /* NAND device jffs2 lives on */ 197 #define CONFIG_JFFS2_PART_OFFSET 0 /* start of jffs2 partition */ 198 #define CONFIG_JFFS2_PART_SIZE (256 * 1024 * 1024) /* partition size*/ 199 200 /* PSRAM */ 201 #define PHYS_PSRAM 0x70000000 202 #define PHYS_PSRAM_SIZE 0x00400000 /* 4MB */ 203 /* Slave EBI1, PSRAM connected */ 204 #define CONFIG_PSRAM_SCFG (AT91_MATRIX_SCFG_ARBT_FIXED_PRIORITY | \ 205 AT91_MATRIX_SCFG_FIXED_DEFMSTR(5) | \ 206 AT91_MATRIX_SCFG_DEFMSTR_TYPE_FIXED | \ 207 AT91_MATRIX_SCFG_SLOT_CYCLE(255)) 208 209 /* Ethernet */ 210 #define CONFIG_MACB 1 211 #define CONFIG_RMII 1 212 #define CONFIG_NET_RETRY_COUNT 20 213 #define CONFIG_RESET_PHY_R 1 214 215 /* USB */ 216 #define CONFIG_USB_ATMEL 217 #define CONFIG_USB_ATMEL_CLK_SEL_PLLB 218 #define CONFIG_USB_OHCI_NEW 1 219 #define CONFIG_SYS_USB_OHCI_CPU_INIT 1 220 #define CONFIG_SYS_USB_OHCI_REGS_BASE 0x00a00000 /* AT91SAM9263_UHP_BASE */ 221 #define CONFIG_SYS_USB_OHCI_SLOT_NAME "at91sam9263" 222 #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2 223 224 #define CONFIG_SYS_LOAD_ADDR 0x22000000 /* load address */ 225 226 #define CONFIG_SYS_MEMTEST_START PHYS_SDRAM 227 #define CONFIG_SYS_MEMTEST_END 0x23e00000 228 229 #define CONFIG_SYS_USE_FLASH 1 230 #undef CONFIG_SYS_USE_DATAFLASH 231 #undef CONFIG_SYS_USE_NANDFLASH 232 233 #ifdef CONFIG_SYS_USE_DATAFLASH 234 235 /* bootstrap + u-boot + env + linux in dataflash on CS0 */ 236 #define CONFIG_ENV_OFFSET 0x4200 237 #define CONFIG_ENV_SIZE 0x4200 238 #define CONFIG_ENV_SECT_SIZE 0x210 239 #define CONFIG_ENV_SPI_MAX_HZ 15000000 240 #define CONFIG_BOOTCOMMAND "sf probe 0; " \ 241 "sf read 0x22000000 0x84000 0x294000; " \ 242 "bootm 0x22000000" 243 244 #elif defined(CONFIG_SYS_USE_NANDFLASH) /* CFG_USE_NANDFLASH */ 245 246 /* bootstrap + u-boot + env + linux in nandflash */ 247 #define CONFIG_ENV_OFFSET 0x60000 248 #define CONFIG_ENV_OFFSET_REDUND 0x80000 249 #define CONFIG_ENV_SIZE 0x20000 /* 1 sector = 128 kB */ 250 #define CONFIG_BOOTCOMMAND "nand read 0x22000000 0xA0000 0x200000; bootm" 251 252 #elif defined(CONFIG_SYS_USE_FLASH) /* CFG_USE_FLASH */ 253 254 #define CONFIG_ENV_OFFSET 0x40000 255 #define CONFIG_ENV_SECT_SIZE 0x10000 256 #define CONFIG_ENV_SIZE 0x10000 257 #define CONFIG_ENV_OVERWRITE 1 258 259 /* JFFS Partition offset set */ 260 #define CONFIG_SYS_JFFS2_FIRST_BANK 0 261 #define CONFIG_SYS_JFFS2_NUM_BANKS 1 262 263 /* 512k reserved for u-boot */ 264 #define CONFIG_SYS_JFFS2_FIRST_SECTOR 11 265 266 #define CONFIG_BOOTCOMMAND "run flashboot" 267 #define CONFIG_ROOTPATH "/ronetix/rootfs" 268 269 #define CONFIG_CON_ROT "fbcon=rotate:3 " 270 271 #define CONFIG_EXTRA_ENV_SETTINGS \ 272 "mtdids=" CONFIG_MTDIDS_DEFAULT "\0" \ 273 "mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \ 274 "partition=nand0,0\0" \ 275 "ramargs=setenv bootargs $(bootargs) $(mtdparts)\0" \ 276 "nfsargs=setenv bootargs root=/dev/nfs rw " \ 277 CONFIG_CON_ROT \ 278 "nfsroot=$(serverip):$(rootpath) $(mtdparts)\0" \ 279 "addip=setenv bootargs $(bootargs) " \ 280 "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask)"\ 281 ":$(hostname):eth0:off\0" \ 282 "ramboot=tftpboot 0x22000000 vmImage;" \ 283 "run ramargs;run addip;bootm 22000000\0" \ 284 "nfsboot=tftpboot 0x22000000 vmImage;" \ 285 "run nfsargs;run addip;bootm 22000000\0" \ 286 "flashboot=run ramargs;run addip;bootm 0x10050000\0" \ 287 "" 288 289 #else 290 #error "Undefined memory device" 291 #endif 292 293 /* 294 * Size of malloc() pool 295 */ 296 #define CONFIG_SYS_MALLOC_LEN ROUND(3 * CONFIG_ENV_SIZE + 128 * 1024, 0x1000) 297 298 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM 299 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 16 * 1024 - \ 300 GENERATED_GBL_DATA_SIZE) 301 302 #endif 303