1 /* 2 * (C) Copyright 2007-2008 3 * Stelian Pop <stelian@popies.net> 4 * Lead Tech Design <www.leadtechdesign.com> 5 * Ilko Iliev <www.ronetix.at> 6 * 7 * Configuation settings for the RONETIX PM9261 board. 8 * 9 * SPDX-License-Identifier: GPL-2.0+ 10 */ 11 12 #ifndef __CONFIG_H 13 #define __CONFIG_H 14 15 /* 16 * SoC must be defined first, before hardware.h is included. 17 * In this case SoC is defined in boards.cfg. 18 */ 19 20 #include <asm/hardware.h> 21 /* ARM asynchronous clock */ 22 23 #define MASTER_PLL_DIV 15 24 #define MASTER_PLL_MUL 162 25 #define MAIN_PLL_DIV 2 26 #define CONFIG_SYS_AT91_SLOW_CLOCK 32768 /* slow clock xtal */ 27 #define CONFIG_SYS_AT91_MAIN_CLOCK 18432000 28 29 #define CONFIG_SYS_AT91_CPU_NAME "AT91SAM9261" 30 #define CONFIG_PM9261 1 /* on a Ronetix PM9261 Board */ 31 #define CONFIG_ARCH_CPU_INIT 32 #define CONFIG_SYS_TEXT_BASE 0 33 34 #define CONFIG_MACH_TYPE MACH_TYPE_PM9261 35 36 /* clocks */ 37 /* CKGR_MOR - enable main osc. */ 38 #define CONFIG_SYS_MOR_VAL \ 39 (AT91_PMC_MOR_MOSCEN | \ 40 (255 << 8)) /* Main Oscillator Start-up Time */ 41 #define CONFIG_SYS_PLLAR_VAL \ 42 (AT91_PMC_PLLAR_29 | /* Bit 29 must be 1 when prog */ \ 43 AT91_PMC_PLLXR_OUT(3) | \ 44 ((MASTER_PLL_MUL - 1) << 16) | (MASTER_PLL_DIV)) 45 46 /* PCK/2 = MCK Master Clock from PLLA */ 47 #define CONFIG_SYS_MCKR1_VAL \ 48 (AT91_PMC_MCKR_CSS_SLOW | \ 49 AT91_PMC_MCKR_PRES_1 | \ 50 AT91_PMC_MCKR_MDIV_2) 51 52 /* PCK/2 = MCK Master Clock from PLLA */ 53 #define CONFIG_SYS_MCKR2_VAL \ 54 (AT91_PMC_MCKR_CSS_PLLA | \ 55 AT91_PMC_MCKR_PRES_1 | \ 56 AT91_PMC_MCKR_MDIV_2) 57 58 /* define PDC[31:16] as DATA[31:16] */ 59 #define CONFIG_SYS_PIOC_PDR_VAL1 0xFFFF0000 60 /* no pull-up for D[31:16] */ 61 #define CONFIG_SYS_PIOC_PPUDR_VAL 0xFFFF0000 62 63 /* EBI_CSA, no pull-ups for D[15:0], CS1 SDRAM, CS3 NAND Flash */ 64 #define CONFIG_SYS_MATRIX_EBICSA_VAL \ 65 (AT91_MATRIX_CSA_DBPUC | AT91_MATRIX_CSA_EBI_CS1A) 66 67 /* SDRAM */ 68 /* SDRAMC_MR Mode register */ 69 #define CONFIG_SYS_SDRC_MR_VAL1 AT91_SDRAMC_MODE_NORMAL 70 /* SDRAMC_TR - Refresh Timer register */ 71 #define CONFIG_SYS_SDRC_TR_VAL1 0x13C 72 /* SDRAMC_CR - Configuration register*/ 73 #define CONFIG_SYS_SDRC_CR_VAL \ 74 (AT91_SDRAMC_NC_9 | \ 75 AT91_SDRAMC_NR_13 | \ 76 AT91_SDRAMC_NB_4 | \ 77 AT91_SDRAMC_CAS_3 | \ 78 AT91_SDRAMC_DBW_32 | \ 79 (1 << 8) | /* Write Recovery Delay */ \ 80 (7 << 12) | /* Row Cycle Delay */ \ 81 (3 << 16) | /* Row Precharge Delay */ \ 82 (2 << 20) | /* Row to Column Delay */ \ 83 (5 << 24) | /* Active to Precharge Delay */ \ 84 (1 << 28)) /* Exit Self Refresh to Active Delay */ 85 86 /* Memory Device Register -> SDRAM */ 87 #define CONFIG_SYS_SDRC_MDR_VAL AT91_SDRAMC_MD_SDRAM 88 #define CONFIG_SYS_SDRC_MR_VAL2 AT91_SDRAMC_MODE_PRECHARGE 89 #define CONFIG_SYS_SDRAM_VAL1 0 /* SDRAM_BASE */ 90 #define CONFIG_SYS_SDRC_MR_VAL3 AT91_SDRAMC_MODE_REFRESH 91 #define CONFIG_SYS_SDRAM_VAL2 0 /* SDRAM_BASE */ 92 #define CONFIG_SYS_SDRAM_VAL3 0 /* SDRAM_BASE */ 93 #define CONFIG_SYS_SDRAM_VAL4 0 /* SDRAM_BASE */ 94 #define CONFIG_SYS_SDRAM_VAL5 0 /* SDRAM_BASE */ 95 #define CONFIG_SYS_SDRAM_VAL6 0 /* SDRAM_BASE */ 96 #define CONFIG_SYS_SDRAM_VAL7 0 /* SDRAM_BASE */ 97 #define CONFIG_SYS_SDRAM_VAL8 0 /* SDRAM_BASE */ 98 #define CONFIG_SYS_SDRAM_VAL9 0 /* SDRAM_BASE */ 99 #define CONFIG_SYS_SDRC_MR_VAL4 AT91_SDRAMC_MODE_LMR 100 #define CONFIG_SYS_SDRAM_VAL10 0 /* SDRAM_BASE */ 101 #define CONFIG_SYS_SDRC_MR_VAL5 AT91_SDRAMC_MODE_NORMAL 102 #define CONFIG_SYS_SDRAM_VAL11 0 /* SDRAM_BASE */ 103 #define CONFIG_SYS_SDRC_TR_VAL2 1200 /* SDRAM_TR */ 104 #define CONFIG_SYS_SDRAM_VAL12 0 /* SDRAM_BASE */ 105 106 /* setup SMC0, CS0 (NOR Flash) - 16-bit, 15 WS */ 107 #define CONFIG_SYS_SMC0_SETUP0_VAL \ 108 (AT91_SMC_SETUP_NWE(10) | AT91_SMC_SETUP_NCS_WR(10) | \ 109 AT91_SMC_SETUP_NRD(10) | AT91_SMC_SETUP_NCS_RD(10)) 110 #define CONFIG_SYS_SMC0_PULSE0_VAL \ 111 (AT91_SMC_PULSE_NWE(11) | AT91_SMC_PULSE_NCS_WR(11) | \ 112 AT91_SMC_PULSE_NRD(11) | AT91_SMC_PULSE_NCS_RD(11)) 113 #define CONFIG_SYS_SMC0_CYCLE0_VAL \ 114 (AT91_SMC_CYCLE_NWE(22) | AT91_SMC_CYCLE_NRD(22)) 115 #define CONFIG_SYS_SMC0_MODE0_VAL \ 116 (AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE | \ 117 AT91_SMC_MODE_DBW_16 | \ 118 AT91_SMC_MODE_TDF | \ 119 AT91_SMC_MODE_TDF_CYCLE(6)) 120 121 /* user reset enable */ 122 #define CONFIG_SYS_RSTC_RMR_VAL \ 123 (AT91_RSTC_KEY | \ 124 AT91_RSTC_CR_PROCRST | \ 125 AT91_RSTC_MR_ERSTL(1) | \ 126 AT91_RSTC_MR_ERSTL(2)) 127 128 /* Disable Watchdog */ 129 #define CONFIG_SYS_WDTC_WDMR_VAL \ 130 (AT91_WDT_MR_WDIDLEHLT | AT91_WDT_MR_WDDBGHLT | \ 131 AT91_WDT_MR_WDV(0xfff) | \ 132 AT91_WDT_MR_WDDIS | \ 133 AT91_WDT_MR_WDD(0xfff)) 134 135 #define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ 136 #define CONFIG_SETUP_MEMORY_TAGS 1 137 #define CONFIG_INITRD_TAG 1 138 139 #undef CONFIG_SKIP_LOWLEVEL_INIT 140 141 /* 142 * Hardware drivers 143 */ 144 145 /* LCD */ 146 #define LCD_BPP LCD_COLOR8 147 #define CONFIG_LCD_LOGO 1 148 #undef LCD_TEST_PATTERN 149 #define CONFIG_LCD_INFO 1 150 #define CONFIG_LCD_INFO_BELOW_LOGO 1 151 #define CONFIG_ATMEL_LCD 1 152 #define CONFIG_ATMEL_LCD_BGR555 1 153 154 /* 155 * BOOTP options 156 */ 157 #define CONFIG_BOOTP_BOOTFILESIZE 1 158 #define CONFIG_BOOTP_BOOTPATH 1 159 #define CONFIG_BOOTP_GATEWAY 1 160 #define CONFIG_BOOTP_HOSTNAME 1 161 162 /* SDRAM */ 163 #define CONFIG_NR_DRAM_BANKS 1 164 #define PHYS_SDRAM 0x20000000 165 #define PHYS_SDRAM_SIZE 0x04000000 /* 64 megs */ 166 167 /* NAND flash */ 168 #define CONFIG_NAND_ATMEL 169 #define CONFIG_SYS_MAX_NAND_DEVICE 1 170 #define CONFIG_SYS_NAND_BASE 0x40000000 171 #define CONFIG_SYS_NAND_DBW_8 1 172 /* our ALE is AD22 */ 173 #define CONFIG_SYS_NAND_MASK_ALE (1 << 22) 174 /* our CLE is AD21 */ 175 #define CONFIG_SYS_NAND_MASK_CLE (1 << 21) 176 #define CONFIG_SYS_NAND_ENABLE_PIN GPIO_PIN_PC(14) 177 #define CONFIG_SYS_NAND_READY_PIN GPIO_PIN_PA(16) 178 179 /* NOR flash */ 180 #define CONFIG_SYS_FLASH_CFI 1 181 #define CONFIG_FLASH_CFI_DRIVER 1 182 #define PHYS_FLASH_1 0x10000000 183 #define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1 184 #define CONFIG_SYS_MAX_FLASH_SECT 256 185 #define CONFIG_SYS_MAX_FLASH_BANKS 1 186 187 /* Ethernet */ 188 #define CONFIG_DRIVER_DM9000 1 189 #define CONFIG_DM9000_BASE 0x30000000 190 #define DM9000_IO CONFIG_DM9000_BASE 191 #define DM9000_DATA (CONFIG_DM9000_BASE + 4) 192 #define CONFIG_DM9000_USE_16BIT 1 193 #define CONFIG_NET_RETRY_COUNT 20 194 #define CONFIG_RESET_PHY_R 1 195 196 /* USB */ 197 #define CONFIG_USB_ATMEL 198 #define CONFIG_USB_ATMEL_CLK_SEL_PLLB 199 #define CONFIG_USB_OHCI_NEW 1 200 #define CONFIG_SYS_USB_OHCI_CPU_INIT 1 201 #define CONFIG_SYS_USB_OHCI_REGS_BASE 0x00500000 202 #define CONFIG_SYS_USB_OHCI_SLOT_NAME "at91sam9261" 203 #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2 204 205 #define CONFIG_SYS_LOAD_ADDR 0x22000000 206 207 #define CONFIG_SYS_MEMTEST_START PHYS_SDRAM 208 #define CONFIG_SYS_MEMTEST_END 0x23e00000 209 210 #undef CONFIG_SYS_USE_DATAFLASH_CS0 211 #undef CONFIG_SYS_USE_NANDFLASH 212 #define CONFIG_SYS_USE_FLASH 1 213 214 #ifdef CONFIG_SYS_USE_DATAFLASH_CS0 215 216 /* bootstrap + u-boot + env + linux in dataflash on CS0 */ 217 #define CONFIG_ENV_OFFSET 0x4200 218 #define CONFIG_ENV_SIZE 0x4200 219 #define CONFIG_ENV_SECT_SIZE 0x210 220 #define CONFIG_ENV_SPI_MAX_HZ 15000000 221 #define CONFIG_BOOTCOMMAND "sf probe 0; " \ 222 "sf read 0x22000000 0x84000 0x210000; " \ 223 "bootm 0x22000000" 224 225 #elif defined(CONFIG_SYS_USE_NANDFLASH) /* CONFIG_SYS_USE_NANDFLASH */ 226 227 /* bootstrap + u-boot + env + linux in nandflash */ 228 #define CONFIG_ENV_OFFSET 0x60000 229 #define CONFIG_ENV_OFFSET_REDUND 0x80000 230 #define CONFIG_ENV_SIZE 0x20000 /* 1 sector = 128 kB */ 231 #define CONFIG_BOOTCOMMAND "nand read 0x22000000 0xA0000 0x200000; bootm" 232 233 #elif defined (CONFIG_SYS_USE_FLASH) 234 235 #define CONFIG_ENV_OFFSET 0x40000 236 #define CONFIG_ENV_SECT_SIZE 0x10000 237 #define CONFIG_ENV_SIZE 0x10000 238 #define CONFIG_ENV_OVERWRITE 1 239 240 /* JFFS Partition offset set */ 241 #define CONFIG_SYS_JFFS2_FIRST_BANK 0 242 #define CONFIG_SYS_JFFS2_NUM_BANKS 1 243 244 /* 512k reserved for u-boot */ 245 #define CONFIG_SYS_JFFS2_FIRST_SECTOR 11 246 247 #define CONFIG_BOOTCOMMAND "run flashboot" 248 249 #define CONFIG_CON_ROT "fbcon=rotate:3 " 250 251 #define CONFIG_EXTRA_ENV_SETTINGS \ 252 "mtdids=" CONFIG_MTDIDS_DEFAULT "\0" \ 253 "mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \ 254 "partition=nand0,0\0" \ 255 "ramargs=setenv bootargs $(bootargs) $(mtdparts)\0" \ 256 "nfsargs=setenv bootargs root=/dev/nfs rw " \ 257 CONFIG_CON_ROT \ 258 "nfsroot=$(serverip):$(rootpath) $(mtdparts)\0" \ 259 "addip=setenv bootargs $(bootargs) " \ 260 "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask)"\ 261 ":$(hostname):eth0:off\0" \ 262 "ramboot=tftpboot 0x22000000 vmImage;" \ 263 "run ramargs;run addip;bootm 22000000\0" \ 264 "nfsboot=tftpboot 0x22000000 vmImage;" \ 265 "run nfsargs;run addip;bootm 22000000\0" \ 266 "flashboot=run ramargs;run addip;bootm 0x10050000\0" \ 267 "" 268 #else 269 #error "Undefined memory device" 270 #endif 271 272 #define CONFIG_SYS_LONGHELP 1 273 #define CONFIG_CMDLINE_EDITING 1 274 275 /* 276 * Size of malloc() pool 277 */ 278 #define CONFIG_SYS_MALLOC_LEN \ 279 ROUND(3 * CONFIG_ENV_SIZE + 128 * 1024, 0x1000) 280 281 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM 282 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 16 * 1024 - \ 283 GENERATED_GBL_DATA_SIZE) 284 285 #endif 286