1 /* 2 * (C) Copyright 2007-2008 3 * Stelian Pop <stelian.pop@leadtechdesign.com> 4 * Lead Tech Design <www.leadtechdesign.com> 5 * Ilko Iliev <www.ronetix.at> 6 * 7 * Configuation settings for the RONETIX PM9261 board. 8 * 9 * See file CREDITS for list of people who contributed to this 10 * project. 11 * 12 * This program is free software; you can redistribute it and/or 13 * modify it under the terms of the GNU General Public License as 14 * published by the Free Software Foundation; either version 2 of 15 * the License, or (at your option) any later version. 16 * 17 * This program is distributed in the hope that it will be useful, 18 * but WITHOUT ANY WARRANTY; without even the implied warranty of 19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 20 * GNU General Public License for more details. 21 * 22 * You should have received a copy of the GNU General Public License 23 * along with this program; if not, write to the Free Software 24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 25 * MA 02111-1307 USA 26 */ 27 28 #ifndef __CONFIG_H 29 #define __CONFIG_H 30 31 #define CONFIG_AT91_LEGACY 32 33 /* ARM asynchronous clock */ 34 #define CONFIG_SYS_AT91_CPU_NAME "AT91SAM9261" 35 36 #define CONFIG_DISPLAY_BOARDINFO 37 38 #define MASTER_PLL_DIV 15 39 #define MASTER_PLL_MUL 162 40 #define MAIN_PLL_DIV 2 41 #define CONFIG_SYS_AT91_MAIN_CLOCK 18432000 42 43 #define CONFIG_SYS_HZ 1000 44 45 #define CONFIG_ARM926EJS 1 /* This is an ARM926EJS Core */ 46 #define CONFIG_AT91SAM9261 1 /* It's an Atmel AT91SAM9261 SoC*/ 47 #define CONFIG_PM9261 1 /* on a Ronetix PM9261 Board */ 48 #define CONFIG_ARCH_CPU_INIT 49 #undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */ 50 51 /* clocks */ 52 /* CKGR_MOR - enable main osc. */ 53 #define CONFIG_SYS_MOR_VAL \ 54 (AT91_PMC_MOSCEN | \ 55 (255 << 8)) /* Main Oscillator Start-up Time */ 56 #define CONFIG_SYS_PLLAR_VAL \ 57 (AT91_PMC_PLLA_WR_ERRATA | /* Bit 29 must be 1 when prog */ \ 58 AT91_PMC_OUT | \ 59 ((MASTER_PLL_MUL - 1) << 16) | (MASTER_PLL_DIV)) 60 61 /* PCK/2 = MCK Master Clock from PLLA */ 62 #define CONFIG_SYS_MCKR1_VAL \ 63 (AT91_PMC_CSS_SLOW | \ 64 AT91_PMC_PRES_1 | \ 65 AT91SAM9_PMC_MDIV_2 | \ 66 AT91_PMC_PDIV_1) 67 68 /* PCK/2 = MCK Master Clock from PLLA */ 69 #define CONFIG_SYS_MCKR2_VAL \ 70 (AT91_PMC_CSS_PLLA | \ 71 AT91_PMC_PRES_1 | \ 72 AT91SAM9_PMC_MDIV_2 | \ 73 AT91_PMC_PDIV_1) 74 75 /* define PDC[31:16] as DATA[31:16] */ 76 #define CONFIG_SYS_PIOC_PDR_VAL1 0xFFFF0000 77 /* no pull-up for D[31:16] */ 78 #define CONFIG_SYS_PIOC_PPUDR_VAL 0xFFFF0000 79 80 /* EBI_CSA, no pull-ups for D[15:0], CS1 SDRAM, CS3 NAND Flash */ 81 #define CONFIG_SYS_MATRIX_EBICSA_VAL \ 82 (AT91_MATRIX_DBPUC | AT91_MATRIX_CS1A_SDRAMC) 83 84 /* SDRAM */ 85 /* SDRAMC_MR Mode register */ 86 #define CONFIG_SYS_SDRC_MR_VAL1 AT91_SDRAMC_MODE_NORMAL 87 /* SDRAMC_TR - Refresh Timer register */ 88 #define CONFIG_SYS_SDRC_TR_VAL1 0x13C 89 /* SDRAMC_CR - Configuration register*/ 90 #define CONFIG_SYS_SDRC_CR_VAL \ 91 (AT91_SDRAMC_NC_9 | \ 92 AT91_SDRAMC_NR_13 | \ 93 AT91_SDRAMC_NB_4 | \ 94 AT91_SDRAMC_CAS_3 | \ 95 AT91_SDRAMC_DBW_32 | \ 96 (1 << 8) | /* Write Recovery Delay */ \ 97 (7 << 12) | /* Row Cycle Delay */ \ 98 (3 << 16) | /* Row Precharge Delay */ \ 99 (2 << 20) | /* Row to Column Delay */ \ 100 (5 << 24) | /* Active to Precharge Delay */ \ 101 (1 << 28)) /* Exit Self Refresh to Active Delay */ 102 103 /* Memory Device Register -> SDRAM */ 104 #define CONFIG_SYS_SDRC_MDR_VAL AT91_SDRAMC_MD_SDRAM 105 #define CONFIG_SYS_SDRC_MR_VAL2 AT91_SDRAMC_MODE_PRECHARGE 106 #define CONFIG_SYS_SDRAM_VAL1 0 /* SDRAM_BASE */ 107 #define CONFIG_SYS_SDRC_MR_VAL3 AT91_SDRAMC_MODE_REFRESH 108 #define CONFIG_SYS_SDRAM_VAL2 0 /* SDRAM_BASE */ 109 #define CONFIG_SYS_SDRAM_VAL3 0 /* SDRAM_BASE */ 110 #define CONFIG_SYS_SDRAM_VAL4 0 /* SDRAM_BASE */ 111 #define CONFIG_SYS_SDRAM_VAL5 0 /* SDRAM_BASE */ 112 #define CONFIG_SYS_SDRAM_VAL6 0 /* SDRAM_BASE */ 113 #define CONFIG_SYS_SDRAM_VAL7 0 /* SDRAM_BASE */ 114 #define CONFIG_SYS_SDRAM_VAL8 0 /* SDRAM_BASE */ 115 #define CONFIG_SYS_SDRAM_VAL9 0 /* SDRAM_BASE */ 116 #define CONFIG_SYS_SDRC_MR_VAL4 AT91_SDRAMC_MODE_LMR 117 #define CONFIG_SYS_SDRAM_VAL10 0 /* SDRAM_BASE */ 118 #define CONFIG_SYS_SDRC_MR_VAL5 AT91_SDRAMC_MODE_NORMAL 119 #define CONFIG_SYS_SDRAM_VAL11 0 /* SDRAM_BASE */ 120 #define CONFIG_SYS_SDRC_TR_VAL2 1200 /* SDRAM_TR */ 121 #define CONFIG_SYS_SDRAM_VAL12 0 /* SDRAM_BASE */ 122 123 /* setup SMC0, CS0 (NOR Flash) - 16-bit, 15 WS */ 124 #define CONFIG_SYS_SMC0_SETUP0_VAL \ 125 (AT91_SMC_NWESETUP_(10) | AT91_SMC_NCS_WRSETUP_(10) | \ 126 AT91_SMC_NRDSETUP_(10) | AT91_SMC_NCS_RDSETUP_(10)) 127 #define CONFIG_SYS_SMC0_PULSE0_VAL \ 128 (AT91_SMC_NWEPULSE_(11) | AT91_SMC_NCS_WRPULSE_(11) | \ 129 AT91_SMC_NRDPULSE_(11) | AT91_SMC_NCS_RDPULSE_(11)) 130 #define CONFIG_SYS_SMC0_CYCLE0_VAL \ 131 (AT91_SMC_NWECYCLE_(22) | AT91_SMC_NRDCYCLE_(22)) 132 #define CONFIG_SYS_SMC0_MODE0_VAL \ 133 (AT91_SMC_READMODE | AT91_SMC_WRITEMODE | \ 134 AT91_SMC_DBW_16 | \ 135 AT91_SMC_TDFMODE | \ 136 AT91_SMC_TDF_(6)) 137 138 /* user reset enable */ 139 #define CONFIG_SYS_RSTC_RMR_VAL \ 140 (AT91_RSTC_KEY | \ 141 AT91_RSTC_PROCRST | \ 142 AT91_RSTC_RSTTYP_WAKEUP | \ 143 AT91_RSTC_RSTTYP_WATCHDOG) 144 145 /* Disable Watchdog */ 146 #define CONFIG_SYS_WDTC_WDMR_VAL \ 147 (AT91_WDT_WDIDLEHLT | AT91_WDT_WDDBGHLT | \ 148 AT91_WDT_WDV | \ 149 AT91_WDT_WDDIS | \ 150 AT91_WDT_WDD) 151 152 #define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ 153 #define CONFIG_SETUP_MEMORY_TAGS 1 154 #define CONFIG_INITRD_TAG 1 155 156 #undef CONFIG_SKIP_LOWLEVEL_INIT 157 #undef CONFIG_SKIP_RELOCATE_UBOOT 158 159 /* 160 * Hardware drivers 161 */ 162 #define CONFIG_AT91_GPIO 1 163 #define CONFIG_ATMEL_USART 1 164 #undef CONFIG_USART0 165 #undef CONFIG_USART1 166 #undef CONFIG_USART2 167 #define CONFIG_USART3 1 /* USART 3 is DBGU */ 168 169 /* LCD */ 170 #define CONFIG_LCD 1 171 #define LCD_BPP LCD_COLOR8 172 #define CONFIG_LCD_LOGO 1 173 #undef LCD_TEST_PATTERN 174 #define CONFIG_LCD_INFO 1 175 #define CONFIG_LCD_INFO_BELOW_LOGO 1 176 #define CONFIG_SYS_WHITE_ON_BLACK 1 177 #define CONFIG_ATMEL_LCD 1 178 #define CONFIG_ATMEL_LCD_BGR555 1 179 #define CONFIG_SYS_CONSOLE_IS_IN_ENV 1 180 181 /* LED */ 182 #define CONFIG_AT91_LED 183 #define CONFIG_RED_LED AT91_PIN_PC12 184 #define CONFIG_GREEN_LED AT91_PIN_PC13 185 #define CONFIG_YELLOW_LED AT91_PIN_PC15 186 187 #define CONFIG_BOOTDELAY 3 188 189 /* 190 * BOOTP options 191 */ 192 #define CONFIG_BOOTP_BOOTFILESIZE 1 193 #define CONFIG_BOOTP_BOOTPATH 1 194 #define CONFIG_BOOTP_GATEWAY 1 195 #define CONFIG_BOOTP_HOSTNAME 1 196 197 /* 198 * Command line configuration. 199 */ 200 #include <config_cmd_default.h> 201 #undef CONFIG_CMD_BDI 202 #undef CONFIG_CMD_IMI 203 #undef CONFIG_CMD_AUTOSCRIPT 204 #undef CONFIG_CMD_FPGA 205 #undef CONFIG_CMD_LOADS 206 #undef CONFIG_CMD_IMLS 207 208 #define CONFIG_CMD_PING 1 209 #define CONFIG_CMD_DHCP 1 210 #define CONFIG_CMD_NAND 1 211 #define CONFIG_CMD_USB 1 212 213 /* SDRAM */ 214 #define CONFIG_NR_DRAM_BANKS 1 215 #define PHYS_SDRAM 0x20000000 216 #define PHYS_SDRAM_SIZE 0x04000000 /* 64 megs */ 217 218 /* DataFlash */ 219 #define CONFIG_ATMEL_DATAFLASH_SPI 220 #define CONFIG_HAS_DATAFLASH 221 #define CONFIG_SYS_SPI_WRITE_TOUT (5 * CONFIG_SYS_HZ) 222 #define CONFIG_SYS_MAX_DATAFLASH_BANKS 1 223 #define CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0 0xC0000000 /* CS0 */ 224 #define CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS3 0xD0000000 /* CS3 */ 225 #define AT91_SPI_CLK 15000000 226 #define DATAFLASH_TCSS (0x1a << 16) 227 #define DATAFLASH_TCHS (0x1 << 24) 228 229 /* NAND flash */ 230 #define CONFIG_NAND_ATMEL 231 #define NAND_MAX_CHIPS 1 232 #define CONFIG_SYS_MAX_NAND_DEVICE 1 233 #define CONFIG_SYS_NAND_BASE 0x40000000 234 #define CONFIG_SYS_NAND_DBW_8 1 235 /* our ALE is AD22 */ 236 #define CONFIG_SYS_NAND_MASK_ALE (1 << 22) 237 /* our CLE is AD21 */ 238 #define CONFIG_SYS_NAND_MASK_CLE (1 << 21) 239 #define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIN_PC14 240 #define CONFIG_SYS_NAND_READY_PIN AT91_PIN_PA16 241 242 /* NOR flash */ 243 #define CONFIG_SYS_FLASH_CFI 1 244 #define CONFIG_FLASH_CFI_DRIVER 1 245 #define PHYS_FLASH_1 0x10000000 246 #define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1 247 #define CONFIG_SYS_MAX_FLASH_SECT 256 248 #define CONFIG_SYS_MAX_FLASH_BANKS 1 249 250 /* Ethernet */ 251 #define CONFIG_DRIVER_DM9000 1 252 #define CONFIG_DM9000_BASE 0x30000000 253 #define DM9000_IO CONFIG_DM9000_BASE 254 #define DM9000_DATA (CONFIG_DM9000_BASE + 4) 255 #define CONFIG_DM9000_USE_16BIT 1 256 #define CONFIG_NET_RETRY_COUNT 20 257 #define CONFIG_RESET_PHY_R 1 258 #define CONFIG_NET_MULTI 259 260 /* USB */ 261 #define CONFIG_USB_ATMEL 262 #define CONFIG_USB_OHCI_NEW 1 263 #define CONFIG_DOS_PARTITION 1 264 #define CONFIG_SYS_USB_OHCI_CPU_INIT 1 265 #define CONFIG_SYS_USB_OHCI_REGS_BASE 0x00500000 266 #define CONFIG_SYS_USB_OHCI_SLOT_NAME "at91sam9261" 267 #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2 268 #define CONFIG_USB_STORAGE 1 269 270 #define CONFIG_SYS_LOAD_ADDR 0x22000000 271 272 #define CONFIG_SYS_MEMTEST_START PHYS_SDRAM 273 #define CONFIG_SYS_MEMTEST_END 0x23e00000 274 275 #undef CONFIG_SYS_USE_DATAFLASH_CS0 276 #undef CONFIG_SYS_USE_NANDFLASH 277 #define CONFIG_SYS_USE_FLASH 1 278 279 #ifdef CONFIG_SYS_USE_DATAFLASH_CS0 280 281 /* bootstrap + u-boot + env + linux in dataflash on CS0 */ 282 #define CONFIG_ENV_IS_IN_DATAFLASH 1 283 #define CONFIG_SYS_MONITOR_BASE \ 284 (CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0 + 0x8400) 285 #define CONFIG_ENV_OFFSET 0x4200 286 #define CONFIG_ENV_ADDR \ 287 (CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0 + CONFIG_ENV_OFFSET) 288 #define CONFIG_ENV_SIZE 0x4200 289 #define CONFIG_BOOTCOMMAND "cp.b 0xC0042000 0x22000000 0x210000; bootm" 290 #define CONFIG_BOOTARGS "console=ttyS0,115200 " \ 291 "root=/dev/mtdblock0 " \ 292 "mtdparts=atmel_nand:-(root) " \ 293 "rw rootfstype=jffs2" 294 295 #elif defined(CONFIG_SYS_USE_NANDFLASH) /* CONFIG_SYS_USE_NANDFLASH */ 296 297 /* bootstrap + u-boot + env + linux in nandflash */ 298 #define CONFIG_ENV_IS_IN_NAND 1 299 #define CONFIG_ENV_OFFSET 0x60000 300 #define CONFIG_ENV_OFFSET_REDUND 0x80000 301 #define CONFIG_ENV_SIZE 0x20000 /* 1 sector = 128 kB */ 302 #define CONFIG_BOOTCOMMAND "nand read 0x22000000 0xA0000 0x200000; bootm" 303 #define CONFIG_BOOTARGS "console=ttyS0,115200 " \ 304 "root=/dev/mtdblock5 " \ 305 "mtdparts=atmel_nand:128k(bootstrap)ro," \ 306 "256k(uboot)ro,128k(env1)ro," \ 307 "128k(env2)ro,2M(linux),-(root) " \ 308 "rw rootfstype=jffs2" 309 310 #elif defined (CONFIG_SYS_USE_FLASH) 311 312 #define CONFIG_ENV_IS_IN_FLASH 1 313 #define CONFIG_ENV_OFFSET 0x40000 314 #define CONFIG_ENV_SECT_SIZE 0x10000 315 #define CONFIG_ENV_SIZE 0x10000 316 #define CONFIG_ENV_OVERWRITE 1 317 318 /* JFFS Partition offset set */ 319 #define CONFIG_SYS_JFFS2_FIRST_BANK 0 320 #define CONFIG_SYS_JFFS2_NUM_BANKS 1 321 322 /* 512k reserved for u-boot */ 323 #define CONFIG_SYS_JFFS2_FIRST_SECTOR 11 324 325 #define CONFIG_BOOTCOMMAND "run flashboot" 326 327 #define MTDIDS_DEFAULT "nor0=physmap-flash.0,nand0=nand" 328 #define MTDPARTS_DEFAULT \ 329 "mtdparts=physmap-flash.0:" \ 330 "256k(u-boot)ro," \ 331 "64k(u-boot-env)ro," \ 332 "1408k(kernel)," \ 333 "-(rootfs);" \ 334 "nand:-(nand)" 335 336 #define CONFIG_CON_ROT "fbcon=rotate:3 " 337 #define CONFIG_BOOTARGS "root=/dev/mtdblock4 rootfstype=jffs2 " CONFIG_CON_ROT 338 339 #define CONFIG_EXTRA_ENV_SETTINGS \ 340 "mtdids=" MTDIDS_DEFAULT "\0" \ 341 "mtdparts=" MTDPARTS_DEFAULT "\0" \ 342 "partition=nand0,0\0" \ 343 "ramargs=setenv bootargs $(bootargs) $(mtdparts)\0" \ 344 "nfsargs=setenv bootargs root=/dev/nfs rw " \ 345 CONFIG_CON_ROT \ 346 "nfsroot=$(serverip):$(rootpath) $(mtdparts)\0" \ 347 "addip=setenv bootargs $(bootargs) " \ 348 "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask)"\ 349 ":$(hostname):eth0:off\0" \ 350 "ramboot=tftpboot 0x22000000 vmImage;" \ 351 "run ramargs;run addip;bootm 22000000\0" \ 352 "nfsboot=tftpboot 0x22000000 vmImage;" \ 353 "run nfsargs;run addip;bootm 22000000\0" \ 354 "flashboot=run ramargs;run addip;bootm 0x10050000\0" \ 355 "" 356 #else 357 #error "Undefined memory device" 358 #endif 359 360 #define CONFIG_BAUDRATE 115200 361 #define CONFIG_SYS_BAUDRATE_TABLE {115200 , 19200, 38400, 57600, 9600 } 362 363 #define CONFIG_SYS_PROMPT "pm9261> " 364 #define CONFIG_SYS_CBSIZE 256 365 #define CONFIG_SYS_MAXARGS 16 366 #define CONFIG_SYS_PBSIZE \ 367 (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) 368 #define CONFIG_SYS_LONGHELP 1 369 #define CONFIG_CMDLINE_EDITING 1 370 371 /* 372 * Size of malloc() pool 373 */ 374 #define CONFIG_SYS_MALLOC_LEN \ 375 ROUND(3 * CONFIG_ENV_SIZE + 128 * 1024, 0x1000) 376 #define CONFIG_SYS_GBL_DATA_SIZE 128 377 378 #define CONFIG_STACKSIZE (32 * 1024) /* regular stack */ 379 380 #ifdef CONFIG_USE_IRQ 381 #error CONFIG_USE_IRQ not supported 382 #endif 383 384 #endif 385