xref: /openbmc/u-boot/include/configs/pcm058.h (revision 014a953c)
1 /*
2  * Copyright (C) Stefano Babic <sbabic@denx.de>
3  *
4  * SPDX-License-Identifier:	GPL-2.0+
5  */
6 
7 
8 #ifndef __PCM058_CONFIG_H
9 #define __PCM058_CONFIG_H
10 
11 #include <config_distro_defaults.h>
12 
13 #ifdef CONFIG_SPL
14 #define CONFIG_SPL_SPI_LOAD
15 #define CONFIG_SYS_SPI_U_BOOT_OFFS	(64 * 1024)
16 #include "imx6_spl.h"
17 #endif
18 
19 #include "mx6_common.h"
20 
21 /* Thermal */
22 #define CONFIG_IMX_THERMAL
23 
24 /* Serial */
25 #define CONFIG_MXC_UART
26 #define CONFIG_MXC_UART_BASE	       UART2_BASE
27 #define CONSOLE_DEV		"ttymxc1"
28 
29 #define PHYS_SDRAM_SIZE		(1u * 1024 * 1024 * 1024)
30 
31 /* Early setup */
32 #define CONFIG_DISPLAY_BOARDINFO_LATE
33 
34 
35 /* Size of malloc() pool */
36 #define CONFIG_SYS_MALLOC_LEN		(8 * SZ_1M)
37 
38 /* Ethernet */
39 #define CONFIG_FEC_MXC
40 #define CONFIG_MII
41 #define IMX_FEC_BASE			ENET_BASE_ADDR
42 #define CONFIG_FEC_XCV_TYPE		RGMII
43 #define CONFIG_ETHPRIME			"FEC"
44 #define CONFIG_FEC_MXC_PHYADDR		3
45 
46 /* SPI Flash */
47 #define CONFIG_MXC_SPI
48 #define CONFIG_SF_DEFAULT_BUS		0
49 #define CONFIG_SF_DEFAULT_CS		0
50 #define CONFIG_SF_DEFAULT_SPEED		20000000
51 #define CONFIG_SF_DEFAULT_MODE		SPI_MODE_0
52 
53 /* I2C Configs */
54 #define CONFIG_SYS_I2C
55 #define CONFIG_SYS_I2C_MXC
56 #define CONFIG_SYS_I2C_MXC_I2C3		/* enable I2C bus 2 */
57 #define CONFIG_SYS_I2C_SPEED		  100000
58 
59 #ifndef CONFIG_SPL_BUILD
60 /* Enable NAND support */
61 #define CONFIG_NAND_MXS
62 #define CONFIG_SYS_MAX_NAND_DEVICE	1
63 #define CONFIG_SYS_NAND_BASE		0x40000000
64 #define CONFIG_SYS_NAND_5_ADDR_CYCLE
65 #define CONFIG_SYS_NAND_ONFI_DETECTION
66 #endif
67 
68 /* DMA stuff, needed for GPMI/MXS NAND support */
69 #define CONFIG_APBH_DMA
70 #define CONFIG_APBH_DMA_BURST
71 #define CONFIG_APBH_DMA_BURST8
72 
73 /* Filesystem support */
74 #define CONFIG_MTD_PARTITIONS
75 #define CONFIG_MTD_DEVICE
76 
77 /* Physical Memory Map */
78 #define CONFIG_NR_DRAM_BANKS           1
79 #define PHYS_SDRAM                     MMDC0_ARB_BASE_ADDR
80 
81 #define CONFIG_SYS_SDRAM_BASE          PHYS_SDRAM
82 #define CONFIG_SYS_INIT_RAM_ADDR       IRAM_BASE_ADDR
83 #define CONFIG_SYS_INIT_RAM_SIZE       IRAM_SIZE
84 
85 #define CONFIG_SYS_INIT_SP_OFFSET \
86 	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
87 #define CONFIG_SYS_INIT_SP_ADDR \
88 	(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
89 
90 /* MMC Configs */
91 #define CONFIG_SYS_FSL_ESDHC_ADDR	0
92 #define CONFIG_SYS_FSL_USDHC_NUM	1
93 
94 /* Environment organization */
95 #define CONFIG_ENV_SIZE                (16 * 1024)
96 #define CONFIG_ENV_OFFSET		(1024 * SZ_1K)
97 #define CONFIG_ENV_SECT_SIZE		(64 * SZ_1K)
98 #define CONFIG_ENV_SPI_BUS             CONFIG_SF_DEFAULT_BUS
99 #define CONFIG_ENV_SPI_CS              CONFIG_SF_DEFAULT_CS
100 #define CONFIG_ENV_SPI_MODE            CONFIG_SF_DEFAULT_MODE
101 #define CONFIG_ENV_SPI_MAX_HZ          CONFIG_SF_DEFAULT_SPEED
102 #define CONFIG_SYS_REDUNDAND_ENVIRONMENT
103 #define CONFIG_ENV_OFFSET_REDUND       (CONFIG_ENV_OFFSET + \
104 						CONFIG_ENV_SECT_SIZE)
105 #define CONFIG_ENV_SIZE_REDUND         CONFIG_ENV_SIZE
106 
107 #ifdef CONFIG_ENV_IS_IN_NAND
108 #define CONFIG_ENV_OFFSET              (0x1E0000)
109 #define CONFIG_ENV_SECT_SIZE           (128 * SZ_1K)
110 #endif
111 
112 #endif
113