1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * Copyright 2013 Freescale Semiconductor, Inc. 4 * 5 * Configuration settings for the phytec PCM-052 SoM. 6 */ 7 8 #ifndef __CONFIG_H 9 #define __CONFIG_H 10 11 #include <asm/arch/imx-regs.h> 12 13 #define CONFIG_SKIP_LOWLEVEL_INIT 14 15 /* Enable passing of ATAGs */ 16 #define CONFIG_CMDLINE_TAG 17 18 /* Size of malloc() pool */ 19 #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 2 * 1024 * 1024) 20 21 /* Allow to overwrite serial and ethaddr */ 22 #define CONFIG_ENV_OVERWRITE 23 24 /* NAND support */ 25 #define CONFIG_SYS_NAND_ONFI_DETECTION 26 27 #ifdef CONFIG_CMD_NAND 28 #define CONFIG_SYS_MAX_NAND_DEVICE 1 29 #define CONFIG_SYS_NAND_BASE NFC_BASE_ADDR 30 31 #define CONFIG_JFFS2_NAND 32 33 /* Dynamic MTD partition support */ 34 35 #endif 36 37 #define CONFIG_SYS_FSL_ESDHC_ADDR 0 38 #define CONFIG_SYS_FSL_ESDHC_NUM 1 39 40 /*#define CONFIG_ESDHC_DETECT_USE_EXTERN_IRQ1*/ 41 42 #define CONFIG_FEC_MXC 43 #define IMX_FEC_BASE ENET_BASE_ADDR 44 #define CONFIG_FEC_XCV_TYPE RMII 45 #define CONFIG_FEC_MXC_PHYADDR 0 46 47 /* QSPI Configs*/ 48 49 #ifdef CONFIG_FSL_QSPI 50 #define FSL_QSPI_FLASH_SIZE (1 << 24) 51 #define FSL_QSPI_FLASH_NUM 2 52 #define CONFIG_SYS_FSL_QSPI_LE 53 #endif 54 55 /* I2C Configs */ 56 #define CONFIG_SYS_I2C 57 #define CONFIG_SYS_I2C_MXC_I2C3 58 #define CONFIG_SYS_I2C_MXC 59 60 /* RTC (actually an RV-4162 but M41T62-compatible) */ 61 #define CONFIG_SYS_I2C_RTC_ADDR 0x68 62 #define CONFIG_SYS_RTC_BUS_NUM 2 63 64 /* EEPROM (24FC256) */ 65 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 66 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 67 #define CONFIG_SYS_I2C_EEPROM_BUS 2 68 69 70 #define CONFIG_LOADADDR 0x82000000 71 72 /* We boot from the gfxRAM area of the OCRAM. */ 73 #define CONFIG_BOARD_SIZE_LIMIT 520192 74 75 /* if no target-specific extra environment settings were defined by the 76 target, define an empty one */ 77 #ifndef PCM052_EXTRA_ENV_SETTINGS 78 #define PCM052_EXTRA_ENV_SETTINGS 79 #endif 80 81 /* if no target-specific boot command was defined by the target, 82 define an empty one */ 83 #ifndef PCM052_BOOTCOMMAND 84 #define PCM052_BOOTCOMMAND 85 #endif 86 87 /* if no target-specific extra environment settings were defined by the 88 target, define an empty one */ 89 #ifndef PCM052_NET_INIT 90 #define PCM052_NET_INIT 91 #endif 92 93 /* boot command, including the target-defined one if any */ 94 #define CONFIG_BOOTCOMMAND PCM052_BOOTCOMMAND "run bootcmd_nand" 95 96 /* Extra env settings (including the target-defined ones if any) */ 97 #define CONFIG_EXTRA_ENV_SETTINGS \ 98 PCM052_EXTRA_ENV_SETTINGS \ 99 "autoload=no\0" \ 100 "fdt_high=0xffffffff\0" \ 101 "initrd_high=0xffffffff\0" \ 102 "blimg_file=u-boot.vyb\0" \ 103 "blimg_addr=0x81000000\0" \ 104 "kernel_file=zImage\0" \ 105 "kernel_addr=0x82000000\0" \ 106 "fdt_file=zImage.dtb\0" \ 107 "fdt_addr=0x81000000\0" \ 108 "ram_file=uRamdisk\0" \ 109 "ram_addr=0x83000000\0" \ 110 "filesys=rootfs.ubifs\0" \ 111 "sys_addr=0x81000000\0" \ 112 "tftploc=/path/to/tftp/directory/\0" \ 113 "nfs_root=/path/to/nfs/root\0" \ 114 "tftptimeout=1000\0" \ 115 "tftptimeoutcountmax=1000000\0" \ 116 "mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \ 117 "bootargs_base=setenv bootargs rw " \ 118 " mem=" __stringify(CONFIG_PCM052_DDR_SIZE) "M " \ 119 "console=ttyLP1,115200n8\0" \ 120 "bootargs_sd=setenv bootargs ${bootargs} " \ 121 "root=/dev/mmcblk0p2 rootwait\0" \ 122 "bootargs_net=setenv bootargs ${bootargs} root=/dev/nfs ip=dhcp " \ 123 "nfsroot=${serverip}:${nfs_root},v3,tcp\0" \ 124 "bootargs_nand=setenv bootargs ${bootargs} " \ 125 "ubi.mtd=5 rootfstype=ubifs root=ubi0:rootfs\0" \ 126 "bootargs_ram=setenv bootargs ${bootargs} " \ 127 "root=/dev/ram rw initrd=${ram_addr}\0" \ 128 "bootargs_mtd=setenv bootargs ${bootargs} ${mtdparts}\0" \ 129 "bootcmd_sd=run bootargs_base bootargs_sd bootargs_mtd; " \ 130 "fatload mmc 0:1 ${kernel_addr} ${kernel_file}; " \ 131 "fatload mmc 0:1 ${fdt_addr} ${fdt_file}; " \ 132 "bootz ${kernel_addr} - ${fdt_addr}\0" \ 133 "bootcmd_net=run bootargs_base bootargs_net bootargs_mtd; " \ 134 "tftpboot ${kernel_addr} ${tftpdir}${kernel_file}; " \ 135 "tftpboot ${fdt_addr} ${tftpdir}${fdt_file}; " \ 136 "bootz ${kernel_addr} - ${fdt_addr}\0" \ 137 "bootcmd_nand=run bootargs_base bootargs_nand bootargs_mtd; " \ 138 "nand read ${fdt_addr} dtb; " \ 139 "nand read ${kernel_addr} kernel; " \ 140 "bootz ${kernel_addr} - ${fdt_addr}\0" \ 141 "bootcmd_ram=run bootargs_base bootargs_ram bootargs_mtd; " \ 142 "nand read ${fdt_addr} dtb; " \ 143 "nand read ${kernel_addr} kernel; " \ 144 "nand read ${ram_addr} root; " \ 145 "bootz ${kernel_addr} ${ram_addr} ${fdt_addr}\0" \ 146 "update_bootloader_from_tftp=" PCM052_NET_INIT \ 147 "if tftp ${blimg_addr} "\ 148 "${tftpdir}${blimg_file}; then " \ 149 "mtdparts default; " \ 150 "nand erase.part bootloader; " \ 151 "nand write ${blimg_addr} bootloader ${filesize}; fi\0" \ 152 "update_kernel_from_sd=if fatload mmc 0:2 ${kernel_addr} " \ 153 "${kernel_file}; " \ 154 "then mtdparts default; " \ 155 "nand erase.part kernel; " \ 156 "nand write ${kernel_addr} kernel ${filesize}; " \ 157 "if fatload mmc 0:2 ${fdt_addr} ${fdt_file}; then " \ 158 "nand erase.part dtb; " \ 159 "nand write ${fdt_addr} dtb ${filesize}; fi\0" \ 160 "update_kernel_from_tftp=" PCM052_NET_INIT \ 161 "if tftp ${fdt_addr} ${tftpdir}${fdt_file}; " \ 162 "then setenv fdtsize ${filesize}; " \ 163 "if tftp ${kernel_addr} ${tftpdir}${kernel_file}; then " \ 164 "mtdparts default; " \ 165 "nand erase.part dtb; " \ 166 "nand write ${fdt_addr} dtb ${fdtsize}; " \ 167 "nand erase.part kernel; " \ 168 "nand write ${kernel_addr} kernel ${filesize}; fi; fi\0" \ 169 "update_rootfs_from_tftp=" PCM052_NET_INIT \ 170 "if tftp ${sys_addr} ${tftpdir}${filesys}; " \ 171 "then mtdparts default; " \ 172 "nand erase.part root; " \ 173 "ubi part root; " \ 174 "ubi create rootfs; " \ 175 "ubi write ${sys_addr} rootfs ${filesize}; fi\0" \ 176 "update_ramdisk_from_tftp=" PCM052_NET_INIT \ 177 "if tftp ${ram_addr} ${tftpdir}${ram_file}; " \ 178 "then mtdparts default; " \ 179 "nand erase.part root; " \ 180 "nand write ${ram_addr} root ${filesize}; fi\0" 181 182 /* Miscellaneous configurable options */ 183 184 #define CONFIG_SYS_MEMTEST_START 0x80010000 185 #define CONFIG_SYS_MEMTEST_END 0x87C00000 186 187 #define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR 188 189 /* Physical memory map */ 190 #define PHYS_SDRAM (0x80000000) 191 #define PHYS_SDRAM_SIZE (CONFIG_PCM052_DDR_SIZE * 1024 * 1024) 192 193 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM 194 #define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR 195 #define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE 196 197 #define CONFIG_SYS_INIT_SP_OFFSET \ 198 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 199 #define CONFIG_SYS_INIT_SP_ADDR \ 200 (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) 201 202 /* environment organization */ 203 #ifdef CONFIG_ENV_IS_IN_MMC 204 #define CONFIG_ENV_SIZE (8 * 1024) 205 206 #define CONFIG_ENV_OFFSET (12 * 64 * 1024) 207 #define CONFIG_SYS_MMC_ENV_DEV 0 208 #endif 209 210 #ifdef CONFIG_ENV_IS_IN_NAND 211 #define CONFIG_ENV_SECT_SIZE (128 * 1024) 212 #define CONFIG_ENV_SIZE (8 * 1024) 213 #define CONFIG_ENV_OFFSET 0xA0000 214 #define CONFIG_ENV_SIZE_REDUND (8 * 1024) 215 #define CONFIG_ENV_OFFSET_REDUND 0xC0000 216 #endif 217 218 #endif 219