1*10a03382SStephen Warren /* 2*10a03382SStephen Warren * Copyright (c) 2013-2016, NVIDIA CORPORATION. 3*10a03382SStephen Warren * 4*10a03382SStephen Warren * SPDX-License-Identifier: GPL-2.0 5*10a03382SStephen Warren */ 6*10a03382SStephen Warren 7*10a03382SStephen Warren #ifndef _P2771_0000_H 8*10a03382SStephen Warren #define _P2771_0000_H 9*10a03382SStephen Warren 10*10a03382SStephen Warren #include <linux/sizes.h> 11*10a03382SStephen Warren 12*10a03382SStephen Warren #include "tegra186-common.h" 13*10a03382SStephen Warren 14*10a03382SStephen Warren /* High-level configuration options */ 15*10a03382SStephen Warren #define CONFIG_TEGRA_BOARD_STRING "NVIDIA P2771-0000" 16*10a03382SStephen Warren 17*10a03382SStephen Warren /* SD/MMC */ 18*10a03382SStephen Warren #define CONFIG_MMC 19*10a03382SStephen Warren #define CONFIG_GENERIC_MMC 20*10a03382SStephen Warren #define CONFIG_TEGRA_MMC 21*10a03382SStephen Warren 22*10a03382SStephen Warren /* Environment in eMMC, at the end of 2nd "boot sector" */ 23*10a03382SStephen Warren #define CONFIG_ENV_IS_IN_MMC 24*10a03382SStephen Warren #define CONFIG_SYS_MMC_ENV_DEV 0 25*10a03382SStephen Warren #define CONFIG_SYS_MMC_ENV_PART 2 26*10a03382SStephen Warren #define CONFIG_ENV_OFFSET (-CONFIG_ENV_SIZE) 27*10a03382SStephen Warren 28*10a03382SStephen Warren #include "tegra-common-post.h" 29*10a03382SStephen Warren 30*10a03382SStephen Warren /* Crystal is 38.4MHz. clk_m runs at half that rate */ 31*10a03382SStephen Warren #define COUNTER_FREQUENCY 19200000 32*10a03382SStephen Warren 33*10a03382SStephen Warren #endif 34