1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * Copyright 2013 Freescale Semiconductor, Inc. 4 */ 5 6 /* 7 * QorIQ P1 Tower boards configuration file 8 */ 9 #ifndef __CONFIG_H 10 #define __CONFIG_H 11 12 #if defined(CONFIG_TWR_P1025) 13 #define CONFIG_BOARDNAME "TWR-P1025" 14 #define CONFIG_PHY_ATHEROS 15 #define CONFIG_QE 16 #define CONFIG_SYS_LBC_LBCR 0x00080000 /* Conversion of LBC addr */ 17 #define CONFIG_SYS_LBC_LCRR 0x80000002 /* LB clock ratio reg */ 18 #endif 19 20 #ifdef CONFIG_SDCARD 21 #define CONFIG_RAMBOOT_SDCARD 22 #define CONFIG_SYS_RAMBOOT 23 #define CONFIG_RESET_VECTOR_ADDRESS 0x110bfffc 24 #endif 25 26 #ifndef CONFIG_RESET_VECTOR_ADDRESS 27 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc 28 #endif 29 30 #ifndef CONFIG_SYS_MONITOR_BASE 31 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 32 #endif 33 34 #define CONFIG_PCIE1 /* PCIE controller 1 (slot 1) */ 35 #define CONFIG_PCIE2 /* PCIE controller 2 (slot 2) */ 36 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ 37 #define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */ 38 #define CONFIG_FSL_PCIE_RESET /* need PCIe reset errata */ 39 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ 40 41 #define CONFIG_ENV_OVERWRITE 42 43 #define CONFIG_SYS_SATA_MAX_DEVICE 2 44 #define CONFIG_LBA48 45 46 #ifndef __ASSEMBLY__ 47 extern unsigned long get_board_sys_clk(unsigned long dummy); 48 #endif 49 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk(0) /*sysclk for TWR-P1025 */ 50 51 #define CONFIG_DDR_CLK_FREQ 66666666 52 53 #define CONFIG_HWCONFIG 54 /* 55 * These can be toggled for performance analysis, otherwise use default. 56 */ 57 #define CONFIG_L2_CACHE 58 #define CONFIG_BTB 59 60 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ 61 #define CONFIG_SYS_MEMTEST_END 0x1fffffff 62 63 #define CONFIG_SYS_CCSRBAR 0xffe00000 64 #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR 65 66 /* DDR Setup */ 67 68 #define CONFIG_SYS_SDRAM_SIZE_LAW LAW_SIZE_512M 69 #define CONFIG_CHIP_SELECTS_PER_CTRL 1 70 71 #define CONFIG_SYS_SDRAM_SIZE (1u << (CONFIG_SYS_SDRAM_SIZE_LAW - 19)) 72 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 73 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 74 75 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 76 77 /* Default settings for DDR3 */ 78 #define CONFIG_SYS_DDR_CS0_BNDS 0x0000001f 79 #define CONFIG_SYS_DDR_CS0_CONFIG 0x80014202 80 #define CONFIG_SYS_DDR_CS0_CONFIG_2 0x00000000 81 #define CONFIG_SYS_DDR_CS1_BNDS 0x00000000 82 #define CONFIG_SYS_DDR_CS1_CONFIG 0x00000000 83 #define CONFIG_SYS_DDR_CS1_CONFIG_2 0x00000000 84 85 #define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef 86 #define CONFIG_SYS_DDR_INIT_ADDR 0x00000000 87 #define CONFIG_SYS_DDR_INIT_EXT_ADDR 0x00000000 88 #define CONFIG_SYS_DDR_MODE_CONTROL 0x00000000 89 90 #define CONFIG_SYS_DDR_ZQ_CONTROL 0x89080600 91 #define CONFIG_SYS_DDR_WRLVL_CONTROL 0x8655a608 92 #define CONFIG_SYS_DDR_SR_CNTR 0x00000000 93 #define CONFIG_SYS_DDR_RCW_1 0x00000000 94 #define CONFIG_SYS_DDR_RCW_2 0x00000000 95 #define CONFIG_SYS_DDR_CONTROL 0xc70c0000 /* Type = DDR3 */ 96 #define CONFIG_SYS_DDR_CONTROL_2 0x04401050 97 #define CONFIG_SYS_DDR_TIMING_4 0x00220001 98 #define CONFIG_SYS_DDR_TIMING_5 0x03402400 99 100 #define CONFIG_SYS_DDR_TIMING_3 0x00020000 101 #define CONFIG_SYS_DDR_TIMING_0 0x00220004 102 #define CONFIG_SYS_DDR_TIMING_1 0x5c5b6544 103 #define CONFIG_SYS_DDR_TIMING_2 0x0fa880de 104 #define CONFIG_SYS_DDR_CLK_CTRL 0x03000000 105 #define CONFIG_SYS_DDR_MODE_1 0x80461320 106 #define CONFIG_SYS_DDR_MODE_2 0x00008000 107 #define CONFIG_SYS_DDR_INTERVAL 0x09480000 108 109 /* 110 * Memory map 111 * 112 * 0x0000_0000 0x1fff_ffff DDR Up to 512MB cacheable 113 * 0x8000_0000 0xdfff_ffff PCI Express Mem 1.5G non-cacheable(PCIe * 3) 114 * 0xffc0_0000 0xffc3_ffff PCI IO range 256k non-cacheable 115 * 116 * Localbus 117 * 0xe000_0000 0xe002_0000 SSD1289 128K non-cacheable 118 * 0xec00_0000 0xefff_ffff FLASH Up to 64M non-cacheable 119 * 120 * 0xff90_0000 0xff97_ffff L2 SRAM Up to 512K cacheable 121 * 0xffd0_0000 0xffd0_3fff init ram 16K Cacheable 122 * 0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable 123 */ 124 125 /* 126 * Local Bus Definitions 127 */ 128 #define CONFIG_SYS_MAX_FLASH_SECT 512 /* 64M */ 129 #define CONFIG_SYS_FLASH_BASE 0xec000000 130 131 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE 132 133 #define CONFIG_FLASH_BR_PRELIM (BR_PHYS_ADDR((CONFIG_SYS_FLASH_BASE_PHYS)) \ 134 | BR_PS_16 | BR_V) 135 136 #define CONFIG_FLASH_OR_PRELIM 0xfc0000b1 137 138 #define CONFIG_SYS_SSD_BASE 0xe0000000 139 #define CONFIG_SYS_SSD_BASE_PHYS CONFIG_SYS_SSD_BASE 140 #define CONFIG_SSD_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_SSD_BASE_PHYS) | \ 141 BR_PS_16 | BR_V) 142 #define CONFIG_SSD_OR_PRELIM (OR_AM_64KB | OR_GPCM_CSNT | OR_GPCM_XACS | \ 143 OR_GPCM_ACS_DIV2 | OR_GPCM_SCY | \ 144 OR_GPCM_TRLX | OR_GPCM_EHTR | OR_GPCM_EAD) 145 146 #define CONFIG_SYS_BR2_PRELIM CONFIG_SSD_BR_PRELIM 147 #define CONFIG_SYS_OR2_PRELIM CONFIG_SSD_OR_PRELIM 148 149 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS} 150 #define CONFIG_SYS_FLASH_QUIET_TEST 151 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 152 153 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ 154 155 #undef CONFIG_SYS_FLASH_CHECKSUM 156 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 157 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 158 159 #define CONFIG_FLASH_CFI_DRIVER 160 #define CONFIG_SYS_FLASH_CFI 161 #define CONFIG_SYS_FLASH_EMPTY_INFO 162 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 163 164 #define CONFIG_SYS_INIT_RAM_LOCK 165 #define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 166 /* Initial L1 address */ 167 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS CONFIG_SYS_INIT_RAM_ADDR 168 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0 169 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS 170 /* Size of used area in RAM */ 171 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 172 173 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ 174 GENERATED_GBL_DATA_SIZE) 175 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 176 177 #define CONFIG_SYS_MONITOR_LEN (768 * 1024) 178 #define CONFIG_SYS_MALLOC_LEN (1024 * 1024)/* Reserved for malloc */ 179 180 #define CONFIG_SYS_BR0_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */ 181 #define CONFIG_SYS_OR0_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */ 182 183 /* Serial Port 184 * open - index 2 185 * shorted - index 1 186 */ 187 #undef CONFIG_SERIAL_SOFTWARE_FIFO 188 #define CONFIG_SYS_NS16550_SERIAL 189 #define CONFIG_SYS_NS16550_REG_SIZE 1 190 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) 191 192 #define CONFIG_SYS_BAUDRATE_TABLE \ 193 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} 194 195 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) 196 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) 197 198 /* I2C */ 199 #define CONFIG_SYS_I2C 200 #define CONFIG_SYS_I2C_FSL /* Use FSL common I2C driver */ 201 #define CONFIG_SYS_FSL_I2C_SPEED 400000 /* I2C spd and slave address */ 202 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 203 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 204 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x52 205 206 /* 207 * I2C2 EEPROM 208 */ 209 #define CONFIG_SYS_FSL_I2C2_SPEED 400000 /* I2C spd and slave address */ 210 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F 211 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100 212 213 #define CONFIG_SYS_I2C_PCA9555_ADDR 0x23 214 215 /* enable read and write access to EEPROM */ 216 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 217 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 218 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 219 220 /* 221 * eSPI - Enhanced SPI 222 */ 223 #define CONFIG_HARD_SPI 224 225 #if defined(CONFIG_PCI) 226 /* 227 * General PCI 228 * Memory space is mapped 1-1, but I/O space must start from 0. 229 */ 230 231 /* controller 2, direct to uli, tgtid 2, Base address 9000 */ 232 #define CONFIG_SYS_PCIE2_NAME "TWR-ELEV PCIe SLOT" 233 #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000 234 #define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000 235 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000 236 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */ 237 #define CONFIG_SYS_PCIE2_IO_VIRT 0xffc10000 238 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 239 #define CONFIG_SYS_PCIE2_IO_PHYS 0xffc10000 240 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ 241 242 /* controller 1, tgtid 1, Base address a000 */ 243 #define CONFIG_SYS_PCIE1_NAME "mini PCIe SLOT" 244 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 245 #define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000 246 #define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000 247 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ 248 #define CONFIG_SYS_PCIE1_IO_VIRT 0xffc00000 249 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 250 #define CONFIG_SYS_PCIE1_IO_PHYS 0xffc00000 251 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ 252 253 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 254 #endif /* CONFIG_PCI */ 255 256 #if defined(CONFIG_TSEC_ENET) 257 258 #define CONFIG_TSEC1 259 #define CONFIG_TSEC1_NAME "eTSEC1" 260 #undef CONFIG_TSEC2 261 #undef CONFIG_TSEC2_NAME 262 #define CONFIG_TSEC3 263 #define CONFIG_TSEC3_NAME "eTSEC3" 264 265 #define TSEC1_PHY_ADDR 2 266 #define TSEC2_PHY_ADDR 0 267 #define TSEC3_PHY_ADDR 1 268 269 #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 270 #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 271 #define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 272 273 #define TSEC1_PHYIDX 0 274 #define TSEC2_PHYIDX 0 275 #define TSEC3_PHYIDX 0 276 277 #define CONFIG_ETHPRIME "eTSEC1" 278 279 #define CONFIG_HAS_ETH0 280 #define CONFIG_HAS_ETH1 281 #undef CONFIG_HAS_ETH2 282 #endif /* CONFIG_TSEC_ENET */ 283 284 #ifdef CONFIG_QE 285 /* QE microcode/firmware address */ 286 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR 287 #define CONFIG_SYS_QE_FW_ADDR 0xefec0000 288 #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 289 #endif /* CONFIG_QE */ 290 291 #ifdef CONFIG_TWR_P1025 292 /* 293 * QE UEC ethernet configuration 294 */ 295 #define CONFIG_MIIM_ADDRESS (CONFIG_SYS_CCSRBAR + 0x82120) 296 297 #undef CONFIG_UEC_ETH 298 #define CONFIG_PHY_MODE_NEED_CHANGE 299 300 #define CONFIG_UEC_ETH1 /* ETH1 */ 301 #define CONFIG_HAS_ETH0 302 303 #ifdef CONFIG_UEC_ETH1 304 #define CONFIG_SYS_UEC1_UCC_NUM 0 /* UCC1 */ 305 #define CONFIG_SYS_UEC1_RX_CLK QE_CLK12 /* CLK12 for MII */ 306 #define CONFIG_SYS_UEC1_TX_CLK QE_CLK9 /* CLK9 for MII */ 307 #define CONFIG_SYS_UEC1_ETH_TYPE FAST_ETH 308 #define CONFIG_SYS_UEC1_PHY_ADDR 0x18 /* 0x18 for MII */ 309 #define CONFIG_SYS_UEC1_INTERFACE_TYPE PHY_INTERFACE_MODE_MII 310 #define CONFIG_SYS_UEC1_INTERFACE_SPEED 100 311 #endif /* CONFIG_UEC_ETH1 */ 312 313 #define CONFIG_UEC_ETH5 /* ETH5 */ 314 #define CONFIG_HAS_ETH1 315 316 #ifdef CONFIG_UEC_ETH5 317 #define CONFIG_SYS_UEC5_UCC_NUM 4 /* UCC5 */ 318 #define CONFIG_SYS_UEC5_RX_CLK QE_CLK_NONE 319 #define CONFIG_SYS_UEC5_TX_CLK QE_CLK13 /* CLK 13 for RMII */ 320 #define CONFIG_SYS_UEC5_ETH_TYPE FAST_ETH 321 #define CONFIG_SYS_UEC5_PHY_ADDR 0x19 /* 0x19 for RMII */ 322 #define CONFIG_SYS_UEC5_INTERFACE_TYPE PHY_INTERFACE_MODE_RMII 323 #define CONFIG_SYS_UEC5_INTERFACE_SPEED 100 324 #endif /* CONFIG_UEC_ETH5 */ 325 #endif /* CONFIG_TWR-P1025 */ 326 327 /* 328 * Dynamic MTD Partition support with mtdparts 329 */ 330 #define CONFIG_FLASH_CFI_MTD 331 332 /* 333 * Environment 334 */ 335 #ifdef CONFIG_SYS_RAMBOOT 336 #ifdef CONFIG_RAMBOOT_SDCARD 337 #define CONFIG_ENV_SIZE 0x2000 338 #define CONFIG_SYS_MMC_ENV_DEV 0 339 #else 340 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) 341 #define CONFIG_ENV_SIZE 0x2000 342 #endif 343 #else 344 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) 345 #define CONFIG_ENV_SIZE 0x2000 346 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ 347 #endif 348 349 #define CONFIG_LOADS_ECHO /* echo on for serial download */ 350 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ 351 352 /* 353 * USB 354 */ 355 #define CONFIG_HAS_FSL_DR_USB 356 357 #if defined(CONFIG_HAS_FSL_DR_USB) 358 #ifdef CONFIG_USB_EHCI_HCD 359 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 360 #define CONFIG_USB_EHCI_FSL 361 #endif 362 #endif 363 364 #ifdef CONFIG_MMC 365 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR 366 #endif 367 368 #undef CONFIG_WATCHDOG /* watchdog disabled */ 369 370 /* 371 * Miscellaneous configurable options 372 */ 373 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 374 375 /* 376 * For booting Linux, the board info and command line data 377 * have to be in the first 64 MB of memory, since this is 378 * the maximum mapped by the Linux kernel during initialization. 379 */ 380 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory for Linux*/ 381 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 382 383 /* 384 * Environment Configuration 385 */ 386 #define CONFIG_HOSTNAME "unknown" 387 #define CONFIG_ROOTPATH "/opt/nfsroot" 388 #define CONFIG_BOOTFILE "uImage" 389 #define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */ 390 391 /* default location for tftp and bootm */ 392 #define CONFIG_LOADADDR 1000000 393 394 #define CONFIG_EXTRA_ENV_SETTINGS \ 395 "netdev=eth0\0" \ 396 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ 397 "loadaddr=1000000\0" \ 398 "bootfile=uImage\0" \ 399 "dtbfile=twr-p1025twr.dtb\0" \ 400 "ramdiskfile=rootfs.ext2.gz.uboot\0" \ 401 "qefirmwarefile=fsl_qe_ucode_1021_10_A.bin\0" \ 402 "tftpflash=tftpboot $loadaddr $uboot; " \ 403 "protect off " __stringify(CONFIG_SYS_TEXT_BASE) " +$filesize; " \ 404 "erase " __stringify(CONFIG_SYS_TEXT_BASE) " +$filesize; " \ 405 "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) " $filesize; " \ 406 "protect on " __stringify(CONFIG_SYS_TEXT_BASE) " +$filesize; " \ 407 "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) " $filesize\0" \ 408 "kernelflash=tftpboot $loadaddr $bootfile; " \ 409 "protect off 0xefa80000 +$filesize; " \ 410 "erase 0xefa80000 +$filesize; " \ 411 "cp.b $loadaddr 0xefa80000 $filesize; " \ 412 "protect on 0xefa80000 +$filesize; " \ 413 "cmp.b $loadaddr 0xefa80000 $filesize\0" \ 414 "dtbflash=tftpboot $loadaddr $dtbfile; " \ 415 "protect off 0xefe80000 +$filesize; " \ 416 "erase 0xefe80000 +$filesize; " \ 417 "cp.b $loadaddr 0xefe80000 $filesize; " \ 418 "protect on 0xefe80000 +$filesize; " \ 419 "cmp.b $loadaddr 0xefe80000 $filesize\0" \ 420 "ramdiskflash=tftpboot $loadaddr $ramdiskfile; " \ 421 "protect off 0xeeb80000 +$filesize; " \ 422 "erase 0xeeb80000 +$filesize; " \ 423 "cp.b $loadaddr 0xeeb80000 $filesize; " \ 424 "protect on 0xeeb80000 +$filesize; " \ 425 "cmp.b $loadaddr 0xeeb80000 $filesize\0" \ 426 "qefirmwareflash=tftpboot $loadaddr $qefirmwarefile; " \ 427 "protect off 0xefec0000 +$filesize; " \ 428 "erase 0xefec0000 +$filesize; " \ 429 "cp.b $loadaddr 0xefec0000 $filesize; " \ 430 "protect on 0xefec0000 +$filesize; " \ 431 "cmp.b $loadaddr 0xefec0000 $filesize\0" \ 432 "consoledev=ttyS0\0" \ 433 "ramdiskaddr=2000000\0" \ 434 "ramdiskfile=rootfs.ext2.gz.uboot\0" \ 435 "fdtaddr=1e00000\0" \ 436 "bdev=sda1\0" \ 437 "norbootaddr=ef080000\0" \ 438 "norfdtaddr=ef040000\0" \ 439 "ramdisk_size=120000\0" \ 440 "usbboot=setenv bootargs root=/dev/sda1 rw rootdelay=5 " \ 441 "console=$consoledev,$baudrate $othbootargs ; bootm 0xefa80000 - 0xefe80000" 442 443 #define CONFIG_NFSBOOTCOMMAND \ 444 "setenv bootargs root=/dev/nfs rw " \ 445 "nfsroot=$serverip:$rootpath " \ 446 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 447 "console=$consoledev,$baudrate $othbootargs;" \ 448 "tftp $loadaddr $bootfile&&" \ 449 "tftp $fdtaddr $fdtfile&&" \ 450 "bootm $loadaddr - $fdtaddr" 451 452 #define CONFIG_HDBOOT \ 453 "setenv bootargs root=/dev/$bdev rw rootdelay=30 " \ 454 "console=$consoledev,$baudrate $othbootargs;" \ 455 "usb start;" \ 456 "ext2load usb 0:1 $loadaddr /boot/$bootfile;" \ 457 "ext2load usb 0:1 $fdtaddr /boot/$fdtfile;" \ 458 "bootm $loadaddr - $fdtaddr" 459 460 #define CONFIG_USB_FAT_BOOT \ 461 "setenv bootargs root=/dev/ram rw " \ 462 "console=$consoledev,$baudrate $othbootargs " \ 463 "ramdisk_size=$ramdisk_size;" \ 464 "usb start;" \ 465 "fatload usb 0:2 $loadaddr $bootfile;" \ 466 "fatload usb 0:2 $fdtaddr $fdtfile;" \ 467 "fatload usb 0:2 $ramdiskaddr $ramdiskfile;" \ 468 "bootm $loadaddr $ramdiskaddr $fdtaddr" 469 470 #define CONFIG_USB_EXT2_BOOT \ 471 "setenv bootargs root=/dev/ram rw " \ 472 "console=$consoledev,$baudrate $othbootargs " \ 473 "ramdisk_size=$ramdisk_size;" \ 474 "usb start;" \ 475 "ext2load usb 0:4 $loadaddr $bootfile;" \ 476 "ext2load usb 0:4 $fdtaddr $fdtfile;" \ 477 "ext2load usb 0:4 $ramdiskaddr $ramdiskfile;" \ 478 "bootm $loadaddr $ramdiskaddr $fdtaddr" 479 480 #define CONFIG_NORBOOT \ 481 "setenv bootargs root=/dev/mtdblock3 rw " \ 482 "console=$consoledev,$baudrate rootfstype=jffs2 $othbootargs;" \ 483 "bootm $norbootaddr - $norfdtaddr" 484 485 #define CONFIG_RAMBOOTCOMMAND_TFTP \ 486 "setenv bootargs root=/dev/ram rw " \ 487 "console=$consoledev,$baudrate $othbootargs " \ 488 "ramdisk_size=$ramdisk_size;" \ 489 "tftp $ramdiskaddr $ramdiskfile;" \ 490 "tftp $loadaddr $bootfile;" \ 491 "tftp $fdtaddr $fdtfile;" \ 492 "bootm $loadaddr $ramdiskaddr $fdtaddr" 493 494 #define CONFIG_RAMBOOTCOMMAND \ 495 "setenv bootargs root=/dev/ram rw " \ 496 "console=$consoledev,$baudrate $othbootargs " \ 497 "ramdisk_size=$ramdisk_size;" \ 498 "bootm 0xefa80000 0xeeb80000 0xefe80000" 499 500 #define CONFIG_BOOTCOMMAND CONFIG_RAMBOOTCOMMAND 501 502 #endif /* __CONFIG_H */ 503