1 /* 2 * Copyright 2013 Freescale Semiconductor, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 /* 8 * QorIQ P1 Tower boards configuration file 9 */ 10 #ifndef __CONFIG_H 11 #define __CONFIG_H 12 13 #if defined(CONFIG_TWR_P1025) 14 #define CONFIG_BOARDNAME "TWR-P1025" 15 #define CONFIG_PHY_ATHEROS 16 #define CONFIG_QE 17 #define CONFIG_SYS_LBC_LBCR 0x00080000 /* Conversion of LBC addr */ 18 #define CONFIG_SYS_LBC_LCRR 0x80000002 /* LB clock ratio reg */ 19 #endif 20 21 #ifdef CONFIG_SDCARD 22 #define CONFIG_RAMBOOT_SDCARD 23 #define CONFIG_SYS_RAMBOOT 24 #define CONFIG_SYS_EXTRA_ENV_RELOC 25 #define CONFIG_SYS_TEXT_BASE 0x11000000 26 #define CONFIG_RESET_VECTOR_ADDRESS 0x110bfffc 27 #endif 28 29 #ifndef CONFIG_SYS_TEXT_BASE 30 #define CONFIG_SYS_TEXT_BASE 0xeff40000 31 #endif 32 33 #ifndef CONFIG_RESET_VECTOR_ADDRESS 34 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc 35 #endif 36 37 #ifndef CONFIG_SYS_MONITOR_BASE 38 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 39 #endif 40 41 #define CONFIG_MP 42 43 #define CONFIG_FSL_ELBC 44 #define CONFIG_PCIE1 /* PCIE controller 1 (slot 1) */ 45 #define CONFIG_PCIE2 /* PCIE controller 2 (slot 2) */ 46 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ 47 #define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */ 48 #define CONFIG_FSL_PCIE_RESET /* need PCIe reset errata */ 49 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ 50 51 #define CONFIG_TSEC_ENET /* tsec ethernet support */ 52 #define CONFIG_ENV_OVERWRITE 53 54 #define CONFIG_CMD_SATA 55 #define CONFIG_SATA_SIL3114 56 #define CONFIG_SYS_SATA_MAX_DEVICE 2 57 #define CONFIG_LIBATA 58 #define CONFIG_LBA48 59 60 #ifndef __ASSEMBLY__ 61 extern unsigned long get_board_sys_clk(unsigned long dummy); 62 #endif 63 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk(0) /*sysclk for TWR-P1025 */ 64 65 #define CONFIG_DDR_CLK_FREQ 66666666 66 67 #define CONFIG_HWCONFIG 68 /* 69 * These can be toggled for performance analysis, otherwise use default. 70 */ 71 #define CONFIG_L2_CACHE 72 #define CONFIG_BTB 73 74 #define CONFIG_BOARD_EARLY_INIT_F /* Call board_pre_init */ 75 76 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ 77 #define CONFIG_SYS_MEMTEST_END 0x1fffffff 78 #define CONFIG_PANIC_HANG /* do not reset board on panic */ 79 80 #define CONFIG_SYS_CCSRBAR 0xffe00000 81 #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR 82 83 /* DDR Setup */ 84 85 #define CONFIG_SYS_SDRAM_SIZE_LAW LAW_SIZE_512M 86 #define CONFIG_CHIP_SELECTS_PER_CTRL 1 87 88 #define CONFIG_SYS_SDRAM_SIZE (1u << (CONFIG_SYS_SDRAM_SIZE_LAW - 19)) 89 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 90 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 91 92 #define CONFIG_NUM_DDR_CONTROLLERS 1 93 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 94 95 /* Default settings for DDR3 */ 96 #define CONFIG_SYS_DDR_CS0_BNDS 0x0000001f 97 #define CONFIG_SYS_DDR_CS0_CONFIG 0x80014202 98 #define CONFIG_SYS_DDR_CS0_CONFIG_2 0x00000000 99 #define CONFIG_SYS_DDR_CS1_BNDS 0x00000000 100 #define CONFIG_SYS_DDR_CS1_CONFIG 0x00000000 101 #define CONFIG_SYS_DDR_CS1_CONFIG_2 0x00000000 102 103 #define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef 104 #define CONFIG_SYS_DDR_INIT_ADDR 0x00000000 105 #define CONFIG_SYS_DDR_INIT_EXT_ADDR 0x00000000 106 #define CONFIG_SYS_DDR_MODE_CONTROL 0x00000000 107 108 #define CONFIG_SYS_DDR_ZQ_CONTROL 0x89080600 109 #define CONFIG_SYS_DDR_WRLVL_CONTROL 0x8655a608 110 #define CONFIG_SYS_DDR_SR_CNTR 0x00000000 111 #define CONFIG_SYS_DDR_RCW_1 0x00000000 112 #define CONFIG_SYS_DDR_RCW_2 0x00000000 113 #define CONFIG_SYS_DDR_CONTROL 0xc70c0000 /* Type = DDR3 */ 114 #define CONFIG_SYS_DDR_CONTROL_2 0x04401050 115 #define CONFIG_SYS_DDR_TIMING_4 0x00220001 116 #define CONFIG_SYS_DDR_TIMING_5 0x03402400 117 118 #define CONFIG_SYS_DDR_TIMING_3 0x00020000 119 #define CONFIG_SYS_DDR_TIMING_0 0x00220004 120 #define CONFIG_SYS_DDR_TIMING_1 0x5c5b6544 121 #define CONFIG_SYS_DDR_TIMING_2 0x0fa880de 122 #define CONFIG_SYS_DDR_CLK_CTRL 0x03000000 123 #define CONFIG_SYS_DDR_MODE_1 0x80461320 124 #define CONFIG_SYS_DDR_MODE_2 0x00008000 125 #define CONFIG_SYS_DDR_INTERVAL 0x09480000 126 127 /* 128 * Memory map 129 * 130 * 0x0000_0000 0x1fff_ffff DDR Up to 512MB cacheable 131 * 0x8000_0000 0xdfff_ffff PCI Express Mem 1.5G non-cacheable(PCIe * 3) 132 * 0xffc0_0000 0xffc3_ffff PCI IO range 256k non-cacheable 133 * 134 * Localbus 135 * 0xe000_0000 0xe002_0000 SSD1289 128K non-cacheable 136 * 0xec00_0000 0xefff_ffff FLASH Up to 64M non-cacheable 137 * 138 * 0xff90_0000 0xff97_ffff L2 SRAM Up to 512K cacheable 139 * 0xffd0_0000 0xffd0_3fff init ram 16K Cacheable 140 * 0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable 141 */ 142 143 /* 144 * Local Bus Definitions 145 */ 146 #define CONFIG_SYS_MAX_FLASH_SECT 512 /* 64M */ 147 #define CONFIG_SYS_FLASH_BASE 0xec000000 148 149 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE 150 151 #define CONFIG_FLASH_BR_PRELIM (BR_PHYS_ADDR((CONFIG_SYS_FLASH_BASE_PHYS)) \ 152 | BR_PS_16 | BR_V) 153 154 #define CONFIG_FLASH_OR_PRELIM 0xfc0000b1 155 156 #define CONFIG_SYS_SSD_BASE 0xe0000000 157 #define CONFIG_SYS_SSD_BASE_PHYS CONFIG_SYS_SSD_BASE 158 #define CONFIG_SSD_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_SSD_BASE_PHYS) | \ 159 BR_PS_16 | BR_V) 160 #define CONFIG_SSD_OR_PRELIM (OR_AM_64KB | OR_GPCM_CSNT | OR_GPCM_XACS | \ 161 OR_GPCM_ACS_DIV2 | OR_GPCM_SCY | \ 162 OR_GPCM_TRLX | OR_GPCM_EHTR | OR_GPCM_EAD) 163 164 #define CONFIG_SYS_BR2_PRELIM CONFIG_SSD_BR_PRELIM 165 #define CONFIG_SYS_OR2_PRELIM CONFIG_SSD_OR_PRELIM 166 167 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS} 168 #define CONFIG_SYS_FLASH_QUIET_TEST 169 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 170 171 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ 172 173 #undef CONFIG_SYS_FLASH_CHECKSUM 174 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 175 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 176 177 #define CONFIG_FLASH_CFI_DRIVER 178 #define CONFIG_SYS_FLASH_CFI 179 #define CONFIG_SYS_FLASH_EMPTY_INFO 180 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 181 182 #define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */ 183 184 #define CONFIG_SYS_INIT_RAM_LOCK 185 #define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 186 /* Initial L1 address */ 187 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS CONFIG_SYS_INIT_RAM_ADDR 188 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0 189 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS 190 /* Size of used area in RAM */ 191 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 192 193 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ 194 GENERATED_GBL_DATA_SIZE) 195 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 196 197 #define CONFIG_SYS_MONITOR_LEN (768 * 1024) 198 #define CONFIG_SYS_MALLOC_LEN (1024 * 1024)/* Reserved for malloc */ 199 200 #define CONFIG_SYS_BR0_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */ 201 #define CONFIG_SYS_OR0_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */ 202 203 /* Serial Port 204 * open - index 2 205 * shorted - index 1 206 */ 207 #define CONFIG_CONS_INDEX 1 208 #undef CONFIG_SERIAL_SOFTWARE_FIFO 209 #define CONFIG_SYS_NS16550_SERIAL 210 #define CONFIG_SYS_NS16550_REG_SIZE 1 211 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) 212 213 #define CONFIG_SYS_BAUDRATE_TABLE \ 214 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} 215 216 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) 217 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) 218 219 /* I2C */ 220 #define CONFIG_SYS_I2C 221 #define CONFIG_SYS_I2C_FSL /* Use FSL common I2C driver */ 222 #define CONFIG_SYS_FSL_I2C_SPEED 400000 /* I2C spd and slave address */ 223 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 224 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 225 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x52 226 227 /* 228 * I2C2 EEPROM 229 */ 230 #define CONFIG_SYS_FSL_I2C2_SPEED 400000 /* I2C spd and slave address */ 231 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F 232 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100 233 234 #define CONFIG_SYS_I2C_PCA9555_ADDR 0x23 235 236 /* enable read and write access to EEPROM */ 237 #define CONFIG_CMD_EEPROM 238 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 239 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 240 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 241 242 /* 243 * eSPI - Enhanced SPI 244 */ 245 #define CONFIG_HARD_SPI 246 247 #if defined(CONFIG_PCI) 248 /* 249 * General PCI 250 * Memory space is mapped 1-1, but I/O space must start from 0. 251 */ 252 253 /* controller 2, direct to uli, tgtid 2, Base address 9000 */ 254 #define CONFIG_SYS_PCIE2_NAME "TWR-ELEV PCIe SLOT" 255 #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000 256 #define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000 257 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000 258 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */ 259 #define CONFIG_SYS_PCIE2_IO_VIRT 0xffc10000 260 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 261 #define CONFIG_SYS_PCIE2_IO_PHYS 0xffc10000 262 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ 263 264 /* controller 1, tgtid 1, Base address a000 */ 265 #define CONFIG_SYS_PCIE1_NAME "mini PCIe SLOT" 266 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 267 #define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000 268 #define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000 269 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ 270 #define CONFIG_SYS_PCIE1_IO_VIRT 0xffc00000 271 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 272 #define CONFIG_SYS_PCIE1_IO_PHYS 0xffc00000 273 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ 274 275 #define CONFIG_CMD_PCI 276 277 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 278 #define CONFIG_DOS_PARTITION 279 #endif /* CONFIG_PCI */ 280 281 #if defined(CONFIG_TSEC_ENET) 282 283 #define CONFIG_MII /* MII PHY management */ 284 #define CONFIG_TSEC1 285 #define CONFIG_TSEC1_NAME "eTSEC1" 286 #undef CONFIG_TSEC2 287 #undef CONFIG_TSEC2_NAME 288 #define CONFIG_TSEC3 289 #define CONFIG_TSEC3_NAME "eTSEC3" 290 291 #define TSEC1_PHY_ADDR 2 292 #define TSEC2_PHY_ADDR 0 293 #define TSEC3_PHY_ADDR 1 294 295 #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 296 #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 297 #define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 298 299 #define TSEC1_PHYIDX 0 300 #define TSEC2_PHYIDX 0 301 #define TSEC3_PHYIDX 0 302 303 #define CONFIG_ETHPRIME "eTSEC1" 304 305 #define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */ 306 307 #define CONFIG_HAS_ETH0 308 #define CONFIG_HAS_ETH1 309 #undef CONFIG_HAS_ETH2 310 #endif /* CONFIG_TSEC_ENET */ 311 312 #ifdef CONFIG_QE 313 /* QE microcode/firmware address */ 314 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR 315 #define CONFIG_SYS_QE_FW_ADDR 0xefec0000 316 #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 317 #endif /* CONFIG_QE */ 318 319 #ifdef CONFIG_TWR_P1025 320 /* 321 * QE UEC ethernet configuration 322 */ 323 #define CONFIG_MIIM_ADDRESS (CONFIG_SYS_CCSRBAR + 0x82120) 324 325 #undef CONFIG_UEC_ETH 326 #define CONFIG_PHY_MODE_NEED_CHANGE 327 328 #define CONFIG_UEC_ETH1 /* ETH1 */ 329 #define CONFIG_HAS_ETH0 330 331 #ifdef CONFIG_UEC_ETH1 332 #define CONFIG_SYS_UEC1_UCC_NUM 0 /* UCC1 */ 333 #define CONFIG_SYS_UEC1_RX_CLK QE_CLK12 /* CLK12 for MII */ 334 #define CONFIG_SYS_UEC1_TX_CLK QE_CLK9 /* CLK9 for MII */ 335 #define CONFIG_SYS_UEC1_ETH_TYPE FAST_ETH 336 #define CONFIG_SYS_UEC1_PHY_ADDR 0x18 /* 0x18 for MII */ 337 #define CONFIG_SYS_UEC1_INTERFACE_TYPE PHY_INTERFACE_MODE_MII 338 #define CONFIG_SYS_UEC1_INTERFACE_SPEED 100 339 #endif /* CONFIG_UEC_ETH1 */ 340 341 #define CONFIG_UEC_ETH5 /* ETH5 */ 342 #define CONFIG_HAS_ETH1 343 344 #ifdef CONFIG_UEC_ETH5 345 #define CONFIG_SYS_UEC5_UCC_NUM 4 /* UCC5 */ 346 #define CONFIG_SYS_UEC5_RX_CLK QE_CLK_NONE 347 #define CONFIG_SYS_UEC5_TX_CLK QE_CLK13 /* CLK 13 for RMII */ 348 #define CONFIG_SYS_UEC5_ETH_TYPE FAST_ETH 349 #define CONFIG_SYS_UEC5_PHY_ADDR 0x19 /* 0x19 for RMII */ 350 #define CONFIG_SYS_UEC5_INTERFACE_TYPE PHY_INTERFACE_MODE_RMII 351 #define CONFIG_SYS_UEC5_INTERFACE_SPEED 100 352 #endif /* CONFIG_UEC_ETH5 */ 353 #endif /* CONFIG_TWR-P1025 */ 354 355 /* 356 * Dynamic MTD Partition support with mtdparts 357 */ 358 #define CONFIG_MTD_DEVICE 359 #define CONFIG_MTD_PARTITIONS 360 #define CONFIG_CMD_MTDPARTS 361 #define CONFIG_FLASH_CFI_MTD 362 #define MTDIDS_DEFAULT "nor0=ec000000.nor" 363 #define MTDPARTS_DEFAULT "mtdparts=ec000000.nor:256k(vsc7385-firmware)," \ 364 "256k(dtb),5632k(kernel),57856k(fs)," \ 365 "256k(qe-ucode-firmware),1280k(u-boot)" 366 367 /* 368 * Environment 369 */ 370 #ifdef CONFIG_SYS_RAMBOOT 371 #ifdef CONFIG_RAMBOOT_SDCARD 372 #define CONFIG_ENV_IS_IN_MMC 373 #define CONFIG_ENV_SIZE 0x2000 374 #define CONFIG_SYS_MMC_ENV_DEV 0 375 #else 376 #define CONFIG_ENV_IS_NOWHERE /* Store ENV in memory only */ 377 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) 378 #define CONFIG_ENV_SIZE 0x2000 379 #endif 380 #else 381 #define CONFIG_ENV_IS_IN_FLASH 382 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) 383 #define CONFIG_ENV_SIZE 0x2000 384 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ 385 #endif 386 387 #define CONFIG_LOADS_ECHO /* echo on for serial download */ 388 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ 389 390 /* 391 * Command line configuration. 392 */ 393 #define CONFIG_CMD_IRQ 394 #define CONFIG_CMD_REGINFO 395 396 /* 397 * USB 398 */ 399 #define CONFIG_HAS_FSL_DR_USB 400 401 #if defined(CONFIG_HAS_FSL_DR_USB) 402 #define CONFIG_USB_EHCI 403 404 #ifdef CONFIG_USB_EHCI 405 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 406 #define CONFIG_USB_EHCI_FSL 407 #endif 408 #endif 409 410 #ifdef CONFIG_MMC 411 #define CONFIG_FSL_ESDHC 412 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR 413 #define CONFIG_GENERIC_MMC 414 #endif 415 416 #if defined(CONFIG_MMC) || defined(CONFIG_USB_EHCI) \ 417 || defined(CONFIG_FSL_SATA) 418 #define CONFIG_DOS_PARTITION 419 #endif 420 421 #undef CONFIG_WATCHDOG /* watchdog disabled */ 422 423 /* 424 * Miscellaneous configurable options 425 */ 426 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 427 #define CONFIG_CMDLINE_EDITING /* Command-line editing */ 428 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 429 #if defined(CONFIG_CMD_KGDB) 430 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 431 #else 432 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 433 #endif 434 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) 435 /* Print Buffer Size */ 436 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 437 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */ 438 439 /* 440 * For booting Linux, the board info and command line data 441 * have to be in the first 64 MB of memory, since this is 442 * the maximum mapped by the Linux kernel during initialization. 443 */ 444 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory for Linux*/ 445 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 446 447 /* 448 * Environment Configuration 449 */ 450 #define CONFIG_HOSTNAME unknown 451 #define CONFIG_ROOTPATH "/opt/nfsroot" 452 #define CONFIG_BOOTFILE "uImage" 453 #define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */ 454 455 /* default location for tftp and bootm */ 456 #define CONFIG_LOADADDR 1000000 457 458 #define CONFIG_BOOTARGS /* the boot command will set bootargs */ 459 460 #define CONFIG_BAUDRATE 115200 461 462 #define CONFIG_EXTRA_ENV_SETTINGS \ 463 "netdev=eth0\0" \ 464 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ 465 "loadaddr=1000000\0" \ 466 "bootfile=uImage\0" \ 467 "dtbfile=twr-p1025twr.dtb\0" \ 468 "ramdiskfile=rootfs.ext2.gz.uboot\0" \ 469 "qefirmwarefile=fsl_qe_ucode_1021_10_A.bin\0" \ 470 "tftpflash=tftpboot $loadaddr $uboot; " \ 471 "protect off " __stringify(CONFIG_SYS_TEXT_BASE) " +$filesize; " \ 472 "erase " __stringify(CONFIG_SYS_TEXT_BASE) " +$filesize; " \ 473 "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) " $filesize; " \ 474 "protect on " __stringify(CONFIG_SYS_TEXT_BASE) " +$filesize; " \ 475 "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) " $filesize\0" \ 476 "kernelflash=tftpboot $loadaddr $bootfile; " \ 477 "protect off 0xefa80000 +$filesize; " \ 478 "erase 0xefa80000 +$filesize; " \ 479 "cp.b $loadaddr 0xefa80000 $filesize; " \ 480 "protect on 0xefa80000 +$filesize; " \ 481 "cmp.b $loadaddr 0xefa80000 $filesize\0" \ 482 "dtbflash=tftpboot $loadaddr $dtbfile; " \ 483 "protect off 0xefe80000 +$filesize; " \ 484 "erase 0xefe80000 +$filesize; " \ 485 "cp.b $loadaddr 0xefe80000 $filesize; " \ 486 "protect on 0xefe80000 +$filesize; " \ 487 "cmp.b $loadaddr 0xefe80000 $filesize\0" \ 488 "ramdiskflash=tftpboot $loadaddr $ramdiskfile; " \ 489 "protect off 0xeeb80000 +$filesize; " \ 490 "erase 0xeeb80000 +$filesize; " \ 491 "cp.b $loadaddr 0xeeb80000 $filesize; " \ 492 "protect on 0xeeb80000 +$filesize; " \ 493 "cmp.b $loadaddr 0xeeb80000 $filesize\0" \ 494 "qefirmwareflash=tftpboot $loadaddr $qefirmwarefile; " \ 495 "protect off 0xefec0000 +$filesize; " \ 496 "erase 0xefec0000 +$filesize; " \ 497 "cp.b $loadaddr 0xefec0000 $filesize; " \ 498 "protect on 0xefec0000 +$filesize; " \ 499 "cmp.b $loadaddr 0xefec0000 $filesize\0" \ 500 "consoledev=ttyS0\0" \ 501 "ramdiskaddr=2000000\0" \ 502 "ramdiskfile=rootfs.ext2.gz.uboot\0" \ 503 "fdtaddr=1e00000\0" \ 504 "bdev=sda1\0" \ 505 "norbootaddr=ef080000\0" \ 506 "norfdtaddr=ef040000\0" \ 507 "ramdisk_size=120000\0" \ 508 "usbboot=setenv bootargs root=/dev/sda1 rw rootdelay=5 " \ 509 "console=$consoledev,$baudrate $othbootargs ; bootm 0xefa80000 - 0xefe80000" 510 511 #define CONFIG_NFSBOOTCOMMAND \ 512 "setenv bootargs root=/dev/nfs rw " \ 513 "nfsroot=$serverip:$rootpath " \ 514 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 515 "console=$consoledev,$baudrate $othbootargs;" \ 516 "tftp $loadaddr $bootfile&&" \ 517 "tftp $fdtaddr $fdtfile&&" \ 518 "bootm $loadaddr - $fdtaddr" 519 520 #define CONFIG_HDBOOT \ 521 "setenv bootargs root=/dev/$bdev rw rootdelay=30 " \ 522 "console=$consoledev,$baudrate $othbootargs;" \ 523 "usb start;" \ 524 "ext2load usb 0:1 $loadaddr /boot/$bootfile;" \ 525 "ext2load usb 0:1 $fdtaddr /boot/$fdtfile;" \ 526 "bootm $loadaddr - $fdtaddr" 527 528 #define CONFIG_USB_FAT_BOOT \ 529 "setenv bootargs root=/dev/ram rw " \ 530 "console=$consoledev,$baudrate $othbootargs " \ 531 "ramdisk_size=$ramdisk_size;" \ 532 "usb start;" \ 533 "fatload usb 0:2 $loadaddr $bootfile;" \ 534 "fatload usb 0:2 $fdtaddr $fdtfile;" \ 535 "fatload usb 0:2 $ramdiskaddr $ramdiskfile;" \ 536 "bootm $loadaddr $ramdiskaddr $fdtaddr" 537 538 #define CONFIG_USB_EXT2_BOOT \ 539 "setenv bootargs root=/dev/ram rw " \ 540 "console=$consoledev,$baudrate $othbootargs " \ 541 "ramdisk_size=$ramdisk_size;" \ 542 "usb start;" \ 543 "ext2load usb 0:4 $loadaddr $bootfile;" \ 544 "ext2load usb 0:4 $fdtaddr $fdtfile;" \ 545 "ext2load usb 0:4 $ramdiskaddr $ramdiskfile;" \ 546 "bootm $loadaddr $ramdiskaddr $fdtaddr" 547 548 #define CONFIG_NORBOOT \ 549 "setenv bootargs root=/dev/mtdblock3 rw " \ 550 "console=$consoledev,$baudrate rootfstype=jffs2 $othbootargs;" \ 551 "bootm $norbootaddr - $norfdtaddr" 552 553 #define CONFIG_RAMBOOTCOMMAND_TFTP \ 554 "setenv bootargs root=/dev/ram rw " \ 555 "console=$consoledev,$baudrate $othbootargs " \ 556 "ramdisk_size=$ramdisk_size;" \ 557 "tftp $ramdiskaddr $ramdiskfile;" \ 558 "tftp $loadaddr $bootfile;" \ 559 "tftp $fdtaddr $fdtfile;" \ 560 "bootm $loadaddr $ramdiskaddr $fdtaddr" 561 562 #define CONFIG_RAMBOOTCOMMAND \ 563 "setenv bootargs root=/dev/ram rw " \ 564 "console=$consoledev,$baudrate $othbootargs " \ 565 "ramdisk_size=$ramdisk_size;" \ 566 "bootm 0xefa80000 0xeeb80000 0xefe80000" 567 568 #define CONFIG_BOOTCOMMAND CONFIG_RAMBOOTCOMMAND 569 570 #endif /* __CONFIG_H */ 571