1 /* 2 * Copyright 2013 Freescale Semiconductor, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 /* 8 * QorIQ P1 Tower boards configuration file 9 */ 10 #ifndef __CONFIG_H 11 #define __CONFIG_H 12 13 #if defined(CONFIG_TWR_P1025) 14 #define CONFIG_BOARDNAME "TWR-P1025" 15 #define CONFIG_PHY_ATHEROS 16 #define CONFIG_QE 17 #define CONFIG_SYS_LBC_LBCR 0x00080000 /* Conversion of LBC addr */ 18 #define CONFIG_SYS_LBC_LCRR 0x80000002 /* LB clock ratio reg */ 19 #endif 20 21 #ifdef CONFIG_SDCARD 22 #define CONFIG_RAMBOOT_SDCARD 23 #define CONFIG_SYS_RAMBOOT 24 #define CONFIG_SYS_EXTRA_ENV_RELOC 25 #define CONFIG_SYS_TEXT_BASE 0x11000000 26 #define CONFIG_RESET_VECTOR_ADDRESS 0x110bfffc 27 #endif 28 29 #ifndef CONFIG_SYS_TEXT_BASE 30 #define CONFIG_SYS_TEXT_BASE 0xeff40000 31 #endif 32 33 #ifndef CONFIG_RESET_VECTOR_ADDRESS 34 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc 35 #endif 36 37 #ifndef CONFIG_SYS_MONITOR_BASE 38 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 39 #endif 40 41 /* High Level Configuration Options */ 42 #define CONFIG_BOOKE 43 #define CONFIG_E500 44 45 #define CONFIG_MP 46 47 #define CONFIG_FSL_ELBC 48 #define CONFIG_PCIE1 /* PCIE controller 1 (slot 1) */ 49 #define CONFIG_PCIE2 /* PCIE controller 2 (slot 2) */ 50 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ 51 #define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */ 52 #define CONFIG_FSL_PCIE_RESET /* need PCIe reset errata */ 53 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ 54 55 #define CONFIG_TSEC_ENET /* tsec ethernet support */ 56 #define CONFIG_ENV_OVERWRITE 57 58 #define CONFIG_CMD_SATA 59 #define CONFIG_SATA_SIL3114 60 #define CONFIG_SYS_SATA_MAX_DEVICE 2 61 #define CONFIG_LIBATA 62 #define CONFIG_LBA48 63 64 #ifndef __ASSEMBLY__ 65 extern unsigned long get_board_sys_clk(unsigned long dummy); 66 #endif 67 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk(0) /*sysclk for TWR-P1025 */ 68 69 #define CONFIG_DDR_CLK_FREQ 66666666 70 71 #define CONFIG_HWCONFIG 72 /* 73 * These can be toggled for performance analysis, otherwise use default. 74 */ 75 #define CONFIG_L2_CACHE 76 #define CONFIG_BTB 77 78 #define CONFIG_BOARD_EARLY_INIT_F /* Call board_pre_init */ 79 80 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ 81 #define CONFIG_SYS_MEMTEST_END 0x1fffffff 82 #define CONFIG_PANIC_HANG /* do not reset board on panic */ 83 84 #define CONFIG_SYS_CCSRBAR 0xffe00000 85 #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR 86 87 /* DDR Setup */ 88 #define CONFIG_SYS_FSL_DDR3 89 90 #define CONFIG_SYS_SDRAM_SIZE_LAW LAW_SIZE_512M 91 #define CONFIG_CHIP_SELECTS_PER_CTRL 1 92 93 #define CONFIG_SYS_SDRAM_SIZE (1u << (CONFIG_SYS_SDRAM_SIZE_LAW - 19)) 94 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 95 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 96 97 #define CONFIG_NUM_DDR_CONTROLLERS 1 98 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 99 100 /* Default settings for DDR3 */ 101 #define CONFIG_SYS_DDR_CS0_BNDS 0x0000001f 102 #define CONFIG_SYS_DDR_CS0_CONFIG 0x80014202 103 #define CONFIG_SYS_DDR_CS0_CONFIG_2 0x00000000 104 #define CONFIG_SYS_DDR_CS1_BNDS 0x00000000 105 #define CONFIG_SYS_DDR_CS1_CONFIG 0x00000000 106 #define CONFIG_SYS_DDR_CS1_CONFIG_2 0x00000000 107 108 #define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef 109 #define CONFIG_SYS_DDR_INIT_ADDR 0x00000000 110 #define CONFIG_SYS_DDR_INIT_EXT_ADDR 0x00000000 111 #define CONFIG_SYS_DDR_MODE_CONTROL 0x00000000 112 113 #define CONFIG_SYS_DDR_ZQ_CONTROL 0x89080600 114 #define CONFIG_SYS_DDR_WRLVL_CONTROL 0x8655a608 115 #define CONFIG_SYS_DDR_SR_CNTR 0x00000000 116 #define CONFIG_SYS_DDR_RCW_1 0x00000000 117 #define CONFIG_SYS_DDR_RCW_2 0x00000000 118 #define CONFIG_SYS_DDR_CONTROL 0xc70c0000 /* Type = DDR3 */ 119 #define CONFIG_SYS_DDR_CONTROL_2 0x04401050 120 #define CONFIG_SYS_DDR_TIMING_4 0x00220001 121 #define CONFIG_SYS_DDR_TIMING_5 0x03402400 122 123 #define CONFIG_SYS_DDR_TIMING_3 0x00020000 124 #define CONFIG_SYS_DDR_TIMING_0 0x00220004 125 #define CONFIG_SYS_DDR_TIMING_1 0x5c5b6544 126 #define CONFIG_SYS_DDR_TIMING_2 0x0fa880de 127 #define CONFIG_SYS_DDR_CLK_CTRL 0x03000000 128 #define CONFIG_SYS_DDR_MODE_1 0x80461320 129 #define CONFIG_SYS_DDR_MODE_2 0x00008000 130 #define CONFIG_SYS_DDR_INTERVAL 0x09480000 131 132 /* 133 * Memory map 134 * 135 * 0x0000_0000 0x1fff_ffff DDR Up to 512MB cacheable 136 * 0x8000_0000 0xdfff_ffff PCI Express Mem 1.5G non-cacheable(PCIe * 3) 137 * 0xffc0_0000 0xffc3_ffff PCI IO range 256k non-cacheable 138 * 139 * Localbus 140 * 0xe000_0000 0xe002_0000 SSD1289 128K non-cacheable 141 * 0xec00_0000 0xefff_ffff FLASH Up to 64M non-cacheable 142 * 143 * 0xff90_0000 0xff97_ffff L2 SRAM Up to 512K cacheable 144 * 0xffd0_0000 0xffd0_3fff init ram 16K Cacheable 145 * 0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable 146 */ 147 148 /* 149 * Local Bus Definitions 150 */ 151 #define CONFIG_SYS_MAX_FLASH_SECT 512 /* 64M */ 152 #define CONFIG_SYS_FLASH_BASE 0xec000000 153 154 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE 155 156 #define CONFIG_FLASH_BR_PRELIM (BR_PHYS_ADDR((CONFIG_SYS_FLASH_BASE_PHYS)) \ 157 | BR_PS_16 | BR_V) 158 159 #define CONFIG_FLASH_OR_PRELIM 0xfc0000b1 160 161 #define CONFIG_SYS_SSD_BASE 0xe0000000 162 #define CONFIG_SYS_SSD_BASE_PHYS CONFIG_SYS_SSD_BASE 163 #define CONFIG_SSD_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_SSD_BASE_PHYS) | \ 164 BR_PS_16 | BR_V) 165 #define CONFIG_SSD_OR_PRELIM (OR_AM_64KB | OR_GPCM_CSNT | OR_GPCM_XACS | \ 166 OR_GPCM_ACS_DIV2 | OR_GPCM_SCY | \ 167 OR_GPCM_TRLX | OR_GPCM_EHTR | OR_GPCM_EAD) 168 169 #define CONFIG_SYS_BR2_PRELIM CONFIG_SSD_BR_PRELIM 170 #define CONFIG_SYS_OR2_PRELIM CONFIG_SSD_OR_PRELIM 171 172 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS} 173 #define CONFIG_SYS_FLASH_QUIET_TEST 174 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 175 176 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ 177 178 #undef CONFIG_SYS_FLASH_CHECKSUM 179 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 180 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 181 182 #define CONFIG_FLASH_CFI_DRIVER 183 #define CONFIG_SYS_FLASH_CFI 184 #define CONFIG_SYS_FLASH_EMPTY_INFO 185 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 186 187 #define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */ 188 189 #define CONFIG_SYS_INIT_RAM_LOCK 190 #define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 191 /* Initial L1 address */ 192 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS CONFIG_SYS_INIT_RAM_ADDR 193 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0 194 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS 195 /* Size of used area in RAM */ 196 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 197 198 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ 199 GENERATED_GBL_DATA_SIZE) 200 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 201 202 #define CONFIG_SYS_MONITOR_LEN (768 * 1024) 203 #define CONFIG_SYS_MALLOC_LEN (1024 * 1024)/* Reserved for malloc */ 204 205 #define CONFIG_SYS_BR0_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */ 206 #define CONFIG_SYS_OR0_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */ 207 208 /* Serial Port 209 * open - index 2 210 * shorted - index 1 211 */ 212 #define CONFIG_CONS_INDEX 1 213 #undef CONFIG_SERIAL_SOFTWARE_FIFO 214 #define CONFIG_SYS_NS16550_SERIAL 215 #define CONFIG_SYS_NS16550_REG_SIZE 1 216 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) 217 218 #define CONFIG_SYS_BAUDRATE_TABLE \ 219 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} 220 221 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) 222 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) 223 224 /* I2C */ 225 #define CONFIG_SYS_I2C 226 #define CONFIG_SYS_I2C_FSL /* Use FSL common I2C driver */ 227 #define CONFIG_SYS_FSL_I2C_SPEED 400000 /* I2C spd and slave address */ 228 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 229 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 230 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x52 231 232 /* 233 * I2C2 EEPROM 234 */ 235 #define CONFIG_SYS_FSL_I2C2_SPEED 400000 /* I2C spd and slave address */ 236 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F 237 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100 238 239 #define CONFIG_SYS_I2C_PCA9555_ADDR 0x23 240 241 /* enable read and write access to EEPROM */ 242 #define CONFIG_CMD_EEPROM 243 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 244 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 245 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 246 247 /* 248 * eSPI - Enhanced SPI 249 */ 250 #define CONFIG_HARD_SPI 251 252 #if defined(CONFIG_PCI) 253 /* 254 * General PCI 255 * Memory space is mapped 1-1, but I/O space must start from 0. 256 */ 257 258 /* controller 2, direct to uli, tgtid 2, Base address 9000 */ 259 #define CONFIG_SYS_PCIE2_NAME "TWR-ELEV PCIe SLOT" 260 #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000 261 #define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000 262 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000 263 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */ 264 #define CONFIG_SYS_PCIE2_IO_VIRT 0xffc10000 265 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 266 #define CONFIG_SYS_PCIE2_IO_PHYS 0xffc10000 267 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ 268 269 /* controller 1, tgtid 1, Base address a000 */ 270 #define CONFIG_SYS_PCIE1_NAME "mini PCIe SLOT" 271 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 272 #define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000 273 #define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000 274 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ 275 #define CONFIG_SYS_PCIE1_IO_VIRT 0xffc00000 276 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 277 #define CONFIG_SYS_PCIE1_IO_PHYS 0xffc00000 278 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ 279 280 #define CONFIG_CMD_PCI 281 282 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 283 #define CONFIG_DOS_PARTITION 284 #endif /* CONFIG_PCI */ 285 286 #if defined(CONFIG_TSEC_ENET) 287 288 #define CONFIG_MII /* MII PHY management */ 289 #define CONFIG_TSEC1 290 #define CONFIG_TSEC1_NAME "eTSEC1" 291 #undef CONFIG_TSEC2 292 #undef CONFIG_TSEC2_NAME 293 #define CONFIG_TSEC3 294 #define CONFIG_TSEC3_NAME "eTSEC3" 295 296 #define TSEC1_PHY_ADDR 2 297 #define TSEC2_PHY_ADDR 0 298 #define TSEC3_PHY_ADDR 1 299 300 #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 301 #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 302 #define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 303 304 #define TSEC1_PHYIDX 0 305 #define TSEC2_PHYIDX 0 306 #define TSEC3_PHYIDX 0 307 308 #define CONFIG_ETHPRIME "eTSEC1" 309 310 #define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */ 311 312 #define CONFIG_HAS_ETH0 313 #define CONFIG_HAS_ETH1 314 #undef CONFIG_HAS_ETH2 315 #endif /* CONFIG_TSEC_ENET */ 316 317 #ifdef CONFIG_QE 318 /* QE microcode/firmware address */ 319 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR 320 #define CONFIG_SYS_QE_FW_ADDR 0xefec0000 321 #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 322 #endif /* CONFIG_QE */ 323 324 #ifdef CONFIG_TWR_P1025 325 /* 326 * QE UEC ethernet configuration 327 */ 328 #define CONFIG_MIIM_ADDRESS (CONFIG_SYS_CCSRBAR + 0x82120) 329 330 #undef CONFIG_UEC_ETH 331 #define CONFIG_PHY_MODE_NEED_CHANGE 332 333 #define CONFIG_UEC_ETH1 /* ETH1 */ 334 #define CONFIG_HAS_ETH0 335 336 #ifdef CONFIG_UEC_ETH1 337 #define CONFIG_SYS_UEC1_UCC_NUM 0 /* UCC1 */ 338 #define CONFIG_SYS_UEC1_RX_CLK QE_CLK12 /* CLK12 for MII */ 339 #define CONFIG_SYS_UEC1_TX_CLK QE_CLK9 /* CLK9 for MII */ 340 #define CONFIG_SYS_UEC1_ETH_TYPE FAST_ETH 341 #define CONFIG_SYS_UEC1_PHY_ADDR 0x18 /* 0x18 for MII */ 342 #define CONFIG_SYS_UEC1_INTERFACE_TYPE PHY_INTERFACE_MODE_MII 343 #define CONFIG_SYS_UEC1_INTERFACE_SPEED 100 344 #endif /* CONFIG_UEC_ETH1 */ 345 346 #define CONFIG_UEC_ETH5 /* ETH5 */ 347 #define CONFIG_HAS_ETH1 348 349 #ifdef CONFIG_UEC_ETH5 350 #define CONFIG_SYS_UEC5_UCC_NUM 4 /* UCC5 */ 351 #define CONFIG_SYS_UEC5_RX_CLK QE_CLK_NONE 352 #define CONFIG_SYS_UEC5_TX_CLK QE_CLK13 /* CLK 13 for RMII */ 353 #define CONFIG_SYS_UEC5_ETH_TYPE FAST_ETH 354 #define CONFIG_SYS_UEC5_PHY_ADDR 0x19 /* 0x19 for RMII */ 355 #define CONFIG_SYS_UEC5_INTERFACE_TYPE PHY_INTERFACE_MODE_RMII 356 #define CONFIG_SYS_UEC5_INTERFACE_SPEED 100 357 #endif /* CONFIG_UEC_ETH5 */ 358 #endif /* CONFIG_TWR-P1025 */ 359 360 /* 361 * Dynamic MTD Partition support with mtdparts 362 */ 363 #define CONFIG_MTD_DEVICE 364 #define CONFIG_MTD_PARTITIONS 365 #define CONFIG_CMD_MTDPARTS 366 #define CONFIG_FLASH_CFI_MTD 367 #define MTDIDS_DEFAULT "nor0=ec000000.nor" 368 #define MTDPARTS_DEFAULT "mtdparts=ec000000.nor:256k(vsc7385-firmware)," \ 369 "256k(dtb),5632k(kernel),57856k(fs)," \ 370 "256k(qe-ucode-firmware),1280k(u-boot)" 371 372 /* 373 * Environment 374 */ 375 #ifdef CONFIG_SYS_RAMBOOT 376 #ifdef CONFIG_RAMBOOT_SDCARD 377 #define CONFIG_ENV_IS_IN_MMC 378 #define CONFIG_ENV_SIZE 0x2000 379 #define CONFIG_SYS_MMC_ENV_DEV 0 380 #else 381 #define CONFIG_ENV_IS_NOWHERE /* Store ENV in memory only */ 382 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) 383 #define CONFIG_ENV_SIZE 0x2000 384 #endif 385 #else 386 #define CONFIG_ENV_IS_IN_FLASH 387 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) 388 #define CONFIG_ENV_SIZE 0x2000 389 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ 390 #endif 391 392 #define CONFIG_LOADS_ECHO /* echo on for serial download */ 393 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ 394 395 /* 396 * Command line configuration. 397 */ 398 #define CONFIG_CMD_IRQ 399 #define CONFIG_CMD_REGINFO 400 401 /* 402 * USB 403 */ 404 #define CONFIG_HAS_FSL_DR_USB 405 406 #if defined(CONFIG_HAS_FSL_DR_USB) 407 #define CONFIG_USB_EHCI 408 409 #ifdef CONFIG_USB_EHCI 410 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 411 #define CONFIG_USB_EHCI_FSL 412 #endif 413 #endif 414 415 #define CONFIG_MMC 416 417 #ifdef CONFIG_MMC 418 #define CONFIG_FSL_ESDHC 419 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR 420 #define CONFIG_GENERIC_MMC 421 #endif 422 423 #if defined(CONFIG_MMC) || defined(CONFIG_USB_EHCI) \ 424 || defined(CONFIG_FSL_SATA) 425 #define CONFIG_DOS_PARTITION 426 #endif 427 428 #undef CONFIG_WATCHDOG /* watchdog disabled */ 429 430 /* 431 * Miscellaneous configurable options 432 */ 433 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 434 #define CONFIG_CMDLINE_EDITING /* Command-line editing */ 435 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 436 #if defined(CONFIG_CMD_KGDB) 437 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 438 #else 439 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 440 #endif 441 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) 442 /* Print Buffer Size */ 443 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 444 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */ 445 446 /* 447 * For booting Linux, the board info and command line data 448 * have to be in the first 64 MB of memory, since this is 449 * the maximum mapped by the Linux kernel during initialization. 450 */ 451 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory for Linux*/ 452 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 453 454 /* 455 * Environment Configuration 456 */ 457 #define CONFIG_HOSTNAME unknown 458 #define CONFIG_ROOTPATH "/opt/nfsroot" 459 #define CONFIG_BOOTFILE "uImage" 460 #define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */ 461 462 /* default location for tftp and bootm */ 463 #define CONFIG_LOADADDR 1000000 464 465 #define CONFIG_BOOTARGS /* the boot command will set bootargs */ 466 467 #define CONFIG_BAUDRATE 115200 468 469 #define CONFIG_EXTRA_ENV_SETTINGS \ 470 "netdev=eth0\0" \ 471 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ 472 "loadaddr=1000000\0" \ 473 "bootfile=uImage\0" \ 474 "dtbfile=twr-p1025twr.dtb\0" \ 475 "ramdiskfile=rootfs.ext2.gz.uboot\0" \ 476 "qefirmwarefile=fsl_qe_ucode_1021_10_A.bin\0" \ 477 "tftpflash=tftpboot $loadaddr $uboot; " \ 478 "protect off " __stringify(CONFIG_SYS_TEXT_BASE) " +$filesize; " \ 479 "erase " __stringify(CONFIG_SYS_TEXT_BASE) " +$filesize; " \ 480 "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) " $filesize; " \ 481 "protect on " __stringify(CONFIG_SYS_TEXT_BASE) " +$filesize; " \ 482 "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) " $filesize\0" \ 483 "kernelflash=tftpboot $loadaddr $bootfile; " \ 484 "protect off 0xefa80000 +$filesize; " \ 485 "erase 0xefa80000 +$filesize; " \ 486 "cp.b $loadaddr 0xefa80000 $filesize; " \ 487 "protect on 0xefa80000 +$filesize; " \ 488 "cmp.b $loadaddr 0xefa80000 $filesize\0" \ 489 "dtbflash=tftpboot $loadaddr $dtbfile; " \ 490 "protect off 0xefe80000 +$filesize; " \ 491 "erase 0xefe80000 +$filesize; " \ 492 "cp.b $loadaddr 0xefe80000 $filesize; " \ 493 "protect on 0xefe80000 +$filesize; " \ 494 "cmp.b $loadaddr 0xefe80000 $filesize\0" \ 495 "ramdiskflash=tftpboot $loadaddr $ramdiskfile; " \ 496 "protect off 0xeeb80000 +$filesize; " \ 497 "erase 0xeeb80000 +$filesize; " \ 498 "cp.b $loadaddr 0xeeb80000 $filesize; " \ 499 "protect on 0xeeb80000 +$filesize; " \ 500 "cmp.b $loadaddr 0xeeb80000 $filesize\0" \ 501 "qefirmwareflash=tftpboot $loadaddr $qefirmwarefile; " \ 502 "protect off 0xefec0000 +$filesize; " \ 503 "erase 0xefec0000 +$filesize; " \ 504 "cp.b $loadaddr 0xefec0000 $filesize; " \ 505 "protect on 0xefec0000 +$filesize; " \ 506 "cmp.b $loadaddr 0xefec0000 $filesize\0" \ 507 "consoledev=ttyS0\0" \ 508 "ramdiskaddr=2000000\0" \ 509 "ramdiskfile=rootfs.ext2.gz.uboot\0" \ 510 "fdtaddr=1e00000\0" \ 511 "bdev=sda1\0" \ 512 "norbootaddr=ef080000\0" \ 513 "norfdtaddr=ef040000\0" \ 514 "ramdisk_size=120000\0" \ 515 "usbboot=setenv bootargs root=/dev/sda1 rw rootdelay=5 " \ 516 "console=$consoledev,$baudrate $othbootargs ; bootm 0xefa80000 - 0xefe80000" 517 518 #define CONFIG_NFSBOOTCOMMAND \ 519 "setenv bootargs root=/dev/nfs rw " \ 520 "nfsroot=$serverip:$rootpath " \ 521 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 522 "console=$consoledev,$baudrate $othbootargs;" \ 523 "tftp $loadaddr $bootfile&&" \ 524 "tftp $fdtaddr $fdtfile&&" \ 525 "bootm $loadaddr - $fdtaddr" 526 527 #define CONFIG_HDBOOT \ 528 "setenv bootargs root=/dev/$bdev rw rootdelay=30 " \ 529 "console=$consoledev,$baudrate $othbootargs;" \ 530 "usb start;" \ 531 "ext2load usb 0:1 $loadaddr /boot/$bootfile;" \ 532 "ext2load usb 0:1 $fdtaddr /boot/$fdtfile;" \ 533 "bootm $loadaddr - $fdtaddr" 534 535 #define CONFIG_USB_FAT_BOOT \ 536 "setenv bootargs root=/dev/ram rw " \ 537 "console=$consoledev,$baudrate $othbootargs " \ 538 "ramdisk_size=$ramdisk_size;" \ 539 "usb start;" \ 540 "fatload usb 0:2 $loadaddr $bootfile;" \ 541 "fatload usb 0:2 $fdtaddr $fdtfile;" \ 542 "fatload usb 0:2 $ramdiskaddr $ramdiskfile;" \ 543 "bootm $loadaddr $ramdiskaddr $fdtaddr" 544 545 #define CONFIG_USB_EXT2_BOOT \ 546 "setenv bootargs root=/dev/ram rw " \ 547 "console=$consoledev,$baudrate $othbootargs " \ 548 "ramdisk_size=$ramdisk_size;" \ 549 "usb start;" \ 550 "ext2load usb 0:4 $loadaddr $bootfile;" \ 551 "ext2load usb 0:4 $fdtaddr $fdtfile;" \ 552 "ext2load usb 0:4 $ramdiskaddr $ramdiskfile;" \ 553 "bootm $loadaddr $ramdiskaddr $fdtaddr" 554 555 #define CONFIG_NORBOOT \ 556 "setenv bootargs root=/dev/mtdblock3 rw " \ 557 "console=$consoledev,$baudrate rootfstype=jffs2 $othbootargs;" \ 558 "bootm $norbootaddr - $norfdtaddr" 559 560 #define CONFIG_RAMBOOTCOMMAND_TFTP \ 561 "setenv bootargs root=/dev/ram rw " \ 562 "console=$consoledev,$baudrate $othbootargs " \ 563 "ramdisk_size=$ramdisk_size;" \ 564 "tftp $ramdiskaddr $ramdiskfile;" \ 565 "tftp $loadaddr $bootfile;" \ 566 "tftp $fdtaddr $fdtfile;" \ 567 "bootm $loadaddr $ramdiskaddr $fdtaddr" 568 569 #define CONFIG_RAMBOOTCOMMAND \ 570 "setenv bootargs root=/dev/ram rw " \ 571 "console=$consoledev,$baudrate $othbootargs " \ 572 "ramdisk_size=$ramdisk_size;" \ 573 "bootm 0xefa80000 0xeeb80000 0xefe80000" 574 575 #define CONFIG_BOOTCOMMAND CONFIG_RAMBOOTCOMMAND 576 577 #endif /* __CONFIG_H */ 578