xref: /openbmc/u-boot/include/configs/p1_twr.h (revision b9553986)
1 /* SPDX-License-Identifier: GPL-2.0+ */
2 /*
3  * Copyright 2013 Freescale Semiconductor, Inc.
4  */
5 
6 /*
7  * QorIQ P1 Tower boards configuration file
8  */
9 #ifndef __CONFIG_H
10 #define __CONFIG_H
11 
12 #if defined(CONFIG_TWR_P1025)
13 #define CONFIG_BOARDNAME "TWR-P1025"
14 #define CONFIG_PHY_ATHEROS
15 #define CONFIG_QE
16 #define CONFIG_SYS_LBC_LBCR	0x00080000	/* Conversion of LBC addr */
17 #define CONFIG_SYS_LBC_LCRR	0x80000002	/* LB clock ratio reg */
18 #endif
19 
20 #ifdef CONFIG_SDCARD
21 #define CONFIG_RAMBOOT_SDCARD
22 #define CONFIG_SYS_RAMBOOT
23 #define CONFIG_RESET_VECTOR_ADDRESS	0x110bfffc
24 #endif
25 
26 #ifndef CONFIG_RESET_VECTOR_ADDRESS
27 #define CONFIG_RESET_VECTOR_ADDRESS	0xeffffffc
28 #endif
29 
30 #ifndef CONFIG_SYS_MONITOR_BASE
31 #define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_TEXT_BASE	/* start of monitor */
32 #endif
33 
34 #define CONFIG_PCIE1	/* PCIE controller 1 (slot 1) */
35 #define CONFIG_PCIE2	/* PCIE controller 2 (slot 2) */
36 #define CONFIG_FSL_PCI_INIT	/* Use common FSL init code */
37 #define CONFIG_PCI_INDIRECT_BRIDGE	/* indirect PCI bridge support */
38 #define CONFIG_FSL_PCIE_RESET	/* need PCIe reset errata */
39 #define CONFIG_SYS_PCI_64BIT	/* enable 64-bit PCI resources */
40 
41 #define CONFIG_ENV_OVERWRITE
42 
43 #define CONFIG_SYS_SATA_MAX_DEVICE	2
44 #define CONFIG_LBA48
45 
46 #ifndef __ASSEMBLY__
47 extern unsigned long get_board_sys_clk(unsigned long dummy);
48 #endif
49 #define CONFIG_SYS_CLK_FREQ	get_board_sys_clk(0) /*sysclk for TWR-P1025 */
50 
51 #define CONFIG_DDR_CLK_FREQ	66666666
52 
53 #define CONFIG_HWCONFIG
54 /*
55  * These can be toggled for performance analysis, otherwise use default.
56  */
57 #define CONFIG_L2_CACHE
58 #define CONFIG_BTB
59 
60 #define CONFIG_SYS_MEMTEST_START	0x00200000	/* memtest works on */
61 #define CONFIG_SYS_MEMTEST_END		0x1fffffff
62 
63 #define CONFIG_SYS_CCSRBAR		0xffe00000
64 #define CONFIG_SYS_CCSRBAR_PHYS_LOW	CONFIG_SYS_CCSRBAR
65 
66 /* DDR Setup */
67 
68 #define CONFIG_SYS_SDRAM_SIZE_LAW	LAW_SIZE_512M
69 #define CONFIG_CHIP_SELECTS_PER_CTRL	1
70 
71 #define CONFIG_SYS_SDRAM_SIZE		(1u << (CONFIG_SYS_SDRAM_SIZE_LAW - 19))
72 #define CONFIG_SYS_DDR_SDRAM_BASE	0x00000000
73 #define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_DDR_SDRAM_BASE
74 
75 #define CONFIG_DIMM_SLOTS_PER_CTLR	1
76 
77 /* Default settings for DDR3 */
78 #define CONFIG_SYS_DDR_CS0_BNDS		0x0000001f
79 #define CONFIG_SYS_DDR_CS0_CONFIG	0x80014202
80 #define CONFIG_SYS_DDR_CS0_CONFIG_2	0x00000000
81 #define CONFIG_SYS_DDR_CS1_BNDS		0x00000000
82 #define CONFIG_SYS_DDR_CS1_CONFIG	0x00000000
83 #define CONFIG_SYS_DDR_CS1_CONFIG_2	0x00000000
84 
85 #define CONFIG_SYS_DDR_DATA_INIT	0xdeadbeef
86 #define CONFIG_SYS_DDR_INIT_ADDR	0x00000000
87 #define CONFIG_SYS_DDR_INIT_EXT_ADDR	0x00000000
88 #define CONFIG_SYS_DDR_MODE_CONTROL	0x00000000
89 
90 #define CONFIG_SYS_DDR_ZQ_CONTROL	0x89080600
91 #define CONFIG_SYS_DDR_WRLVL_CONTROL	0x8655a608
92 #define CONFIG_SYS_DDR_SR_CNTR		0x00000000
93 #define CONFIG_SYS_DDR_RCW_1		0x00000000
94 #define CONFIG_SYS_DDR_RCW_2		0x00000000
95 #define CONFIG_SYS_DDR_CONTROL		0xc70c0000	/* Type = DDR3	*/
96 #define CONFIG_SYS_DDR_CONTROL_2	0x04401050
97 #define CONFIG_SYS_DDR_TIMING_4		0x00220001
98 #define CONFIG_SYS_DDR_TIMING_5		0x03402400
99 
100 #define CONFIG_SYS_DDR_TIMING_3		0x00020000
101 #define CONFIG_SYS_DDR_TIMING_0		0x00220004
102 #define CONFIG_SYS_DDR_TIMING_1		0x5c5b6544
103 #define CONFIG_SYS_DDR_TIMING_2		0x0fa880de
104 #define CONFIG_SYS_DDR_CLK_CTRL		0x03000000
105 #define CONFIG_SYS_DDR_MODE_1		0x80461320
106 #define CONFIG_SYS_DDR_MODE_2		0x00008000
107 #define CONFIG_SYS_DDR_INTERVAL		0x09480000
108 
109 /*
110  * Memory map
111  *
112  * 0x0000_0000 0x1fff_ffff	DDR		Up to 512MB cacheable
113  * 0x8000_0000 0xdfff_ffff	PCI Express Mem	1.5G non-cacheable(PCIe * 3)
114  * 0xffc0_0000 0xffc3_ffff	PCI IO range	256k non-cacheable
115  *
116  * Localbus
117  * 0xe000_0000 0xe002_0000	SSD1289		128K non-cacheable
118  * 0xec00_0000 0xefff_ffff	FLASH		Up to 64M non-cacheable
119  *
120  * 0xff90_0000 0xff97_ffff	L2 SRAM		Up to 512K cacheable
121  * 0xffd0_0000 0xffd0_3fff	init ram	16K Cacheable
122  * 0xffe0_0000 0xffef_ffff	CCSR		1M non-cacheable
123  */
124 
125 /*
126  * Local Bus Definitions
127  */
128 #define CONFIG_SYS_MAX_FLASH_SECT	512	/* 64M */
129 #define CONFIG_SYS_FLASH_BASE		0xec000000
130 
131 #define CONFIG_SYS_FLASH_BASE_PHYS	CONFIG_SYS_FLASH_BASE
132 
133 #define CONFIG_FLASH_BR_PRELIM (BR_PHYS_ADDR((CONFIG_SYS_FLASH_BASE_PHYS)) \
134 	| BR_PS_16 | BR_V)
135 
136 #define CONFIG_FLASH_OR_PRELIM	0xfc0000b1
137 
138 #define CONFIG_SYS_SSD_BASE	0xe0000000
139 #define CONFIG_SYS_SSD_BASE_PHYS	CONFIG_SYS_SSD_BASE
140 #define CONFIG_SSD_BR_PRELIM	(BR_PHYS_ADDR(CONFIG_SYS_SSD_BASE_PHYS) | \
141 					BR_PS_16 | BR_V)
142 #define CONFIG_SSD_OR_PRELIM	(OR_AM_64KB | OR_GPCM_CSNT | OR_GPCM_XACS | \
143 				 OR_GPCM_ACS_DIV2 | OR_GPCM_SCY | \
144 				 OR_GPCM_TRLX | OR_GPCM_EHTR | OR_GPCM_EAD)
145 
146 #define CONFIG_SYS_BR2_PRELIM CONFIG_SSD_BR_PRELIM
147 #define CONFIG_SYS_OR2_PRELIM CONFIG_SSD_OR_PRELIM
148 
149 #define CONFIG_SYS_FLASH_BANKS_LIST	{CONFIG_SYS_FLASH_BASE_PHYS}
150 #define CONFIG_SYS_FLASH_QUIET_TEST
151 #define CONFIG_FLASH_SHOW_PROGRESS	45	/* count down from 45/5: 9..1 */
152 
153 #define CONFIG_SYS_MAX_FLASH_BANKS	1	/* number of banks */
154 
155 #undef CONFIG_SYS_FLASH_CHECKSUM
156 #define CONFIG_SYS_FLASH_ERASE_TOUT	60000	/* Flash Erase Timeout (ms) */
157 #define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (ms) */
158 
159 #define CONFIG_SYS_FLASH_EMPTY_INFO
160 
161 #define CONFIG_SYS_INIT_RAM_LOCK
162 #define CONFIG_SYS_INIT_RAM_ADDR	0xffd00000
163 /* Initial L1 address */
164 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS	CONFIG_SYS_INIT_RAM_ADDR
165 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0
166 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS
167 /* Size of used area in RAM */
168 #define CONFIG_SYS_INIT_RAM_SIZE	0x00004000
169 
170 #define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - \
171 					GENERATED_GBL_DATA_SIZE)
172 #define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
173 
174 #define CONFIG_SYS_MONITOR_LEN	(768 * 1024)
175 #define CONFIG_SYS_MALLOC_LEN	(1024 * 1024)/* Reserved for malloc */
176 
177 #define CONFIG_SYS_BR0_PRELIM	CONFIG_FLASH_BR_PRELIM	/* NOR Base Address */
178 #define CONFIG_SYS_OR0_PRELIM	CONFIG_FLASH_OR_PRELIM	/* NOR Options */
179 
180 /* Serial Port
181  * open - index 2
182  * shorted - index 1
183  */
184 #undef CONFIG_SERIAL_SOFTWARE_FIFO
185 #define CONFIG_SYS_NS16550_SERIAL
186 #define CONFIG_SYS_NS16550_REG_SIZE	1
187 #define CONFIG_SYS_NS16550_CLK		get_bus_freq(0)
188 
189 #define CONFIG_SYS_BAUDRATE_TABLE	\
190 	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
191 
192 #define CONFIG_SYS_NS16550_COM1	(CONFIG_SYS_CCSRBAR+0x4500)
193 #define CONFIG_SYS_NS16550_COM2	(CONFIG_SYS_CCSRBAR+0x4600)
194 
195 /* I2C */
196 #define CONFIG_SYS_I2C
197 #define CONFIG_SYS_I2C_FSL			/* Use FSL common I2C driver */
198 #define CONFIG_SYS_FSL_I2C_SPEED	400000	/* I2C spd and slave address */
199 #define CONFIG_SYS_FSL_I2C_SLAVE	0x7F
200 #define CONFIG_SYS_FSL_I2C_OFFSET	0x3000
201 #define CONFIG_SYS_I2C_EEPROM_ADDR	0x52
202 
203 /*
204  * I2C2 EEPROM
205  */
206 #define CONFIG_SYS_FSL_I2C2_SPEED	400000	/* I2C spd and slave address */
207 #define CONFIG_SYS_FSL_I2C2_SLAVE	0x7F
208 #define CONFIG_SYS_FSL_I2C2_OFFSET	0x3100
209 
210 #define CONFIG_SYS_I2C_PCA9555_ADDR	0x23
211 
212 /* enable read and write access to EEPROM */
213 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
214 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
215 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
216 
217 #if defined(CONFIG_PCI)
218 /*
219  * General PCI
220  * Memory space is mapped 1-1, but I/O space must start from 0.
221  */
222 
223 /* controller 2, direct to uli, tgtid 2, Base address 9000 */
224 #define CONFIG_SYS_PCIE2_NAME		"TWR-ELEV PCIe SLOT"
225 #define CONFIG_SYS_PCIE2_MEM_VIRT	0xa0000000
226 #define CONFIG_SYS_PCIE2_MEM_BUS	0xa0000000
227 #define CONFIG_SYS_PCIE2_MEM_PHYS	0xa0000000
228 #define CONFIG_SYS_PCIE2_MEM_SIZE	0x20000000	/* 512M */
229 #define CONFIG_SYS_PCIE2_IO_VIRT	0xffc10000
230 #define CONFIG_SYS_PCIE2_IO_BUS		0x00000000
231 #define CONFIG_SYS_PCIE2_IO_PHYS	0xffc10000
232 #define CONFIG_SYS_PCIE2_IO_SIZE	0x00010000	/* 64k */
233 
234 /* controller 1, tgtid 1, Base address a000 */
235 #define CONFIG_SYS_PCIE1_NAME		"mini PCIe SLOT"
236 #define CONFIG_SYS_PCIE1_MEM_VIRT	0x80000000
237 #define CONFIG_SYS_PCIE1_MEM_BUS	0x80000000
238 #define CONFIG_SYS_PCIE1_MEM_PHYS	0x80000000
239 #define CONFIG_SYS_PCIE1_MEM_SIZE	0x20000000	/* 512M */
240 #define CONFIG_SYS_PCIE1_IO_VIRT	0xffc00000
241 #define CONFIG_SYS_PCIE1_IO_BUS		0x00000000
242 #define CONFIG_SYS_PCIE1_IO_PHYS	0xffc00000
243 #define CONFIG_SYS_PCIE1_IO_SIZE	0x00010000	/* 64k */
244 
245 #define CONFIG_PCI_SCAN_SHOW	/* show pci devices on startup */
246 #endif /* CONFIG_PCI */
247 
248 #if defined(CONFIG_TSEC_ENET)
249 
250 #define CONFIG_TSEC1
251 #define CONFIG_TSEC1_NAME	"eTSEC1"
252 #undef CONFIG_TSEC2
253 #undef CONFIG_TSEC2_NAME
254 #define CONFIG_TSEC3
255 #define CONFIG_TSEC3_NAME	"eTSEC3"
256 
257 #define TSEC1_PHY_ADDR	2
258 #define TSEC2_PHY_ADDR	0
259 #define TSEC3_PHY_ADDR	1
260 
261 #define TSEC1_FLAGS	(TSEC_GIGABIT | TSEC_REDUCED)
262 #define TSEC2_FLAGS	(TSEC_GIGABIT | TSEC_REDUCED)
263 #define TSEC3_FLAGS	(TSEC_GIGABIT | TSEC_REDUCED)
264 
265 #define TSEC1_PHYIDX	0
266 #define TSEC2_PHYIDX	0
267 #define TSEC3_PHYIDX	0
268 
269 #define CONFIG_ETHPRIME	"eTSEC1"
270 
271 #define CONFIG_HAS_ETH0
272 #define CONFIG_HAS_ETH1
273 #undef CONFIG_HAS_ETH2
274 #endif /* CONFIG_TSEC_ENET */
275 
276 #ifdef CONFIG_QE
277 /* QE microcode/firmware address */
278 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR
279 #define CONFIG_SYS_QE_FW_ADDR	0xefec0000
280 #define CONFIG_SYS_QE_FMAN_FW_LENGTH	0x10000
281 #endif /* CONFIG_QE */
282 
283 #ifdef CONFIG_TWR_P1025
284 /*
285  * QE UEC ethernet configuration
286  */
287 #define CONFIG_MIIM_ADDRESS	(CONFIG_SYS_CCSRBAR + 0x82120)
288 
289 #undef CONFIG_UEC_ETH
290 #define CONFIG_PHY_MODE_NEED_CHANGE
291 
292 #define CONFIG_UEC_ETH1	/* ETH1 */
293 #define CONFIG_HAS_ETH0
294 
295 #ifdef CONFIG_UEC_ETH1
296 #define CONFIG_SYS_UEC1_UCC_NUM	0	/* UCC1 */
297 #define CONFIG_SYS_UEC1_RX_CLK	QE_CLK12 /* CLK12 for MII */
298 #define CONFIG_SYS_UEC1_TX_CLK	QE_CLK9 /* CLK9 for MII */
299 #define CONFIG_SYS_UEC1_ETH_TYPE	FAST_ETH
300 #define CONFIG_SYS_UEC1_PHY_ADDR	0x18	/* 0x18 for MII */
301 #define CONFIG_SYS_UEC1_INTERFACE_TYPE PHY_INTERFACE_MODE_MII
302 #define CONFIG_SYS_UEC1_INTERFACE_SPEED	100
303 #endif /* CONFIG_UEC_ETH1 */
304 
305 #define CONFIG_UEC_ETH5	/* ETH5 */
306 #define CONFIG_HAS_ETH1
307 
308 #ifdef CONFIG_UEC_ETH5
309 #define CONFIG_SYS_UEC5_UCC_NUM	4	/* UCC5 */
310 #define CONFIG_SYS_UEC5_RX_CLK	QE_CLK_NONE
311 #define CONFIG_SYS_UEC5_TX_CLK	QE_CLK13 /* CLK 13 for RMII */
312 #define CONFIG_SYS_UEC5_ETH_TYPE	FAST_ETH
313 #define CONFIG_SYS_UEC5_PHY_ADDR	0x19	/* 0x19 for RMII */
314 #define CONFIG_SYS_UEC5_INTERFACE_TYPE PHY_INTERFACE_MODE_RMII
315 #define CONFIG_SYS_UEC5_INTERFACE_SPEED	100
316 #endif /* CONFIG_UEC_ETH5 */
317 #endif /* CONFIG_TWR-P1025 */
318 
319 /*
320  * Dynamic MTD Partition support with mtdparts
321  */
322 
323 /*
324  * Environment
325  */
326 #ifdef CONFIG_SYS_RAMBOOT
327 #ifdef CONFIG_RAMBOOT_SDCARD
328 #define CONFIG_ENV_SIZE		0x2000
329 #define CONFIG_SYS_MMC_ENV_DEV	0
330 #else
331 #define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE - 0x1000)
332 #define CONFIG_ENV_SIZE		0x2000
333 #endif
334 #else
335 #define CONFIG_ENV_ADDR	(CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
336 #define CONFIG_ENV_SIZE		0x2000
337 #define CONFIG_ENV_SECT_SIZE	0x20000 /* 128K (one sector) */
338 #endif
339 
340 #define CONFIG_LOADS_ECHO		/* echo on for serial download */
341 #define CONFIG_SYS_LOADS_BAUD_CHANGE	/* allow baudrate change */
342 
343 /*
344  * USB
345  */
346 #define CONFIG_HAS_FSL_DR_USB
347 
348 #if defined(CONFIG_HAS_FSL_DR_USB)
349 #ifdef CONFIG_USB_EHCI_HCD
350 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
351 #define CONFIG_USB_EHCI_FSL
352 #endif
353 #endif
354 
355 #ifdef CONFIG_MMC
356 #define CONFIG_SYS_FSL_ESDHC_ADDR	CONFIG_SYS_MPC85xx_ESDHC_ADDR
357 #endif
358 
359 #undef CONFIG_WATCHDOG	/* watchdog disabled */
360 
361 /*
362  * Miscellaneous configurable options
363  */
364 #define CONFIG_SYS_LOAD_ADDR	0x2000000	/* default load address */
365 
366 /*
367  * For booting Linux, the board info and command line data
368  * have to be in the first 64 MB of memory, since this is
369  * the maximum mapped by the Linux kernel during initialization.
370  */
371 #define CONFIG_SYS_BOOTMAPSZ	(64 << 20)	/* Initial Memory for Linux*/
372 #define CONFIG_SYS_BOOTM_LEN	(64 << 20)	/* Increase max gunzip size */
373 
374 /*
375  * Environment Configuration
376  */
377 #define CONFIG_HOSTNAME		"unknown"
378 #define CONFIG_ROOTPATH		"/opt/nfsroot"
379 #define CONFIG_BOOTFILE		"uImage"
380 #define CONFIG_UBOOTPATH	u-boot.bin /* U-Boot image on TFTP server */
381 
382 /* default location for tftp and bootm */
383 #define CONFIG_LOADADDR	1000000
384 
385 #define	CONFIG_EXTRA_ENV_SETTINGS	\
386 "netdev=eth0\0"	\
387 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0"	\
388 "loadaddr=1000000\0"	\
389 "bootfile=uImage\0"	\
390 "dtbfile=twr-p1025twr.dtb\0"	\
391 "ramdiskfile=rootfs.ext2.gz.uboot\0"	\
392 "qefirmwarefile=fsl_qe_ucode_1021_10_A.bin\0"	\
393 "tftpflash=tftpboot $loadaddr $uboot; "	\
394 	"protect off " __stringify(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
395 	"erase " __stringify(CONFIG_SYS_TEXT_BASE) " +$filesize; "	\
396 	"cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) " $filesize; " \
397 	"protect on " __stringify(CONFIG_SYS_TEXT_BASE) " +$filesize; "	\
398 	"cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) " $filesize\0" \
399 "kernelflash=tftpboot $loadaddr $bootfile; "	\
400 	"protect off 0xefa80000 +$filesize; "	\
401 	"erase 0xefa80000 +$filesize; "	\
402 	"cp.b $loadaddr 0xefa80000 $filesize; "	\
403 	"protect on 0xefa80000 +$filesize; "	\
404 	"cmp.b $loadaddr 0xefa80000 $filesize\0"	\
405 "dtbflash=tftpboot $loadaddr $dtbfile; "	\
406 	"protect off 0xefe80000 +$filesize; "	\
407 	"erase 0xefe80000 +$filesize; "	\
408 	"cp.b $loadaddr 0xefe80000 $filesize; "	\
409 	"protect on 0xefe80000 +$filesize; "	\
410 	"cmp.b $loadaddr 0xefe80000 $filesize\0"	\
411 "ramdiskflash=tftpboot $loadaddr $ramdiskfile; "	\
412 	"protect off 0xeeb80000 +$filesize; "	\
413 	"erase 0xeeb80000 +$filesize; "	\
414 	"cp.b $loadaddr 0xeeb80000 $filesize; "	\
415 	"protect on 0xeeb80000 +$filesize; "	\
416 	"cmp.b $loadaddr 0xeeb80000 $filesize\0"	\
417 "qefirmwareflash=tftpboot $loadaddr $qefirmwarefile; "	\
418 	"protect off 0xefec0000 +$filesize; "	\
419 	"erase 0xefec0000 +$filesize; "	\
420 	"cp.b $loadaddr 0xefec0000 $filesize; "	\
421 	"protect on 0xefec0000 +$filesize; "	\
422 	"cmp.b $loadaddr 0xefec0000 $filesize\0"	\
423 "consoledev=ttyS0\0"	\
424 "ramdiskaddr=2000000\0"	\
425 "ramdiskfile=rootfs.ext2.gz.uboot\0"	\
426 "fdtaddr=1e00000\0"	\
427 "bdev=sda1\0"	\
428 "norbootaddr=ef080000\0"	\
429 "norfdtaddr=ef040000\0"	\
430 "ramdisk_size=120000\0" \
431 "usbboot=setenv bootargs root=/dev/sda1 rw rootdelay=5 " \
432 "console=$consoledev,$baudrate $othbootargs ; bootm 0xefa80000 - 0xefe80000"
433 
434 #define CONFIG_NFSBOOTCOMMAND	\
435 "setenv bootargs root=/dev/nfs rw "	\
436 "nfsroot=$serverip:$rootpath "	\
437 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
438 "console=$consoledev,$baudrate $othbootargs;" \
439 "tftp $loadaddr $bootfile&&"	\
440 "tftp $fdtaddr $fdtfile&&"	\
441 "bootm $loadaddr - $fdtaddr"
442 
443 #define CONFIG_HDBOOT	\
444 "setenv bootargs root=/dev/$bdev rw rootdelay=30 "	\
445 "console=$consoledev,$baudrate $othbootargs;" \
446 "usb start;"	\
447 "ext2load usb 0:1 $loadaddr /boot/$bootfile;"	\
448 "ext2load usb 0:1 $fdtaddr /boot/$fdtfile;"	\
449 "bootm $loadaddr - $fdtaddr"
450 
451 #define CONFIG_USB_FAT_BOOT	\
452 "setenv bootargs root=/dev/ram rw "	\
453 "console=$consoledev,$baudrate $othbootargs " \
454 "ramdisk_size=$ramdisk_size;"	\
455 "usb start;"	\
456 "fatload usb 0:2 $loadaddr $bootfile;"	\
457 "fatload usb 0:2 $fdtaddr $fdtfile;"	\
458 "fatload usb 0:2 $ramdiskaddr $ramdiskfile;"	\
459 "bootm $loadaddr $ramdiskaddr $fdtaddr"
460 
461 #define CONFIG_USB_EXT2_BOOT	\
462 "setenv bootargs root=/dev/ram rw "	\
463 "console=$consoledev,$baudrate $othbootargs " \
464 "ramdisk_size=$ramdisk_size;"	\
465 "usb start;"	\
466 "ext2load usb 0:4 $loadaddr $bootfile;"	\
467 "ext2load usb 0:4 $fdtaddr $fdtfile;" \
468 "ext2load usb 0:4 $ramdiskaddr $ramdiskfile;" \
469 "bootm $loadaddr $ramdiskaddr $fdtaddr"
470 
471 #define CONFIG_NORBOOT	\
472 "setenv bootargs root=/dev/mtdblock3 rw "	\
473 "console=$consoledev,$baudrate rootfstype=jffs2 $othbootargs;"	\
474 "bootm $norbootaddr - $norfdtaddr"
475 
476 #define CONFIG_RAMBOOTCOMMAND_TFTP	\
477 "setenv bootargs root=/dev/ram rw "	\
478 "console=$consoledev,$baudrate $othbootargs " \
479 "ramdisk_size=$ramdisk_size;"	\
480 "tftp $ramdiskaddr $ramdiskfile;"	\
481 "tftp $loadaddr $bootfile;"	\
482 "tftp $fdtaddr $fdtfile;"	\
483 "bootm $loadaddr $ramdiskaddr $fdtaddr"
484 
485 #define CONFIG_RAMBOOTCOMMAND	\
486 "setenv bootargs root=/dev/ram rw "	\
487 "console=$consoledev,$baudrate $othbootargs " \
488 "ramdisk_size=$ramdisk_size;"	\
489 "bootm 0xefa80000 0xeeb80000 0xefe80000"
490 
491 #define CONFIG_BOOTCOMMAND	CONFIG_RAMBOOTCOMMAND
492 
493 #endif /* __CONFIG_H */
494