1 /* 2 * Copyright 2013 Freescale Semiconductor, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 /* 8 * QorIQ P1 Tower boards configuration file 9 */ 10 #ifndef __CONFIG_H 11 #define __CONFIG_H 12 13 #if defined(CONFIG_TWR_P1025) 14 #define CONFIG_BOARDNAME "TWR-P1025" 15 #define CONFIG_PHY_ATHEROS 16 #define CONFIG_QE 17 #define CONFIG_SYS_LBC_LBCR 0x00080000 /* Conversion of LBC addr */ 18 #define CONFIG_SYS_LBC_LCRR 0x80000002 /* LB clock ratio reg */ 19 #endif 20 21 #ifdef CONFIG_SDCARD 22 #define CONFIG_RAMBOOT_SDCARD 23 #define CONFIG_SYS_RAMBOOT 24 #define CONFIG_SYS_EXTRA_ENV_RELOC 25 #define CONFIG_SYS_TEXT_BASE 0x11000000 26 #define CONFIG_RESET_VECTOR_ADDRESS 0x110bfffc 27 #endif 28 29 #ifndef CONFIG_SYS_TEXT_BASE 30 #define CONFIG_SYS_TEXT_BASE 0xeff40000 31 #endif 32 33 #ifndef CONFIG_RESET_VECTOR_ADDRESS 34 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc 35 #endif 36 37 #ifndef CONFIG_SYS_MONITOR_BASE 38 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 39 #endif 40 41 /* High Level Configuration Options */ 42 #define CONFIG_BOOKE 43 #define CONFIG_E500 44 45 #define CONFIG_MP 46 47 #define CONFIG_FSL_ELBC 48 #define CONFIG_PCIE1 /* PCIE controller 1 (slot 1) */ 49 #define CONFIG_PCIE2 /* PCIE controller 2 (slot 2) */ 50 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ 51 #define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */ 52 #define CONFIG_FSL_PCIE_RESET /* need PCIe reset errata */ 53 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ 54 55 #define CONFIG_FSL_LAW 56 #define CONFIG_TSEC_ENET /* tsec ethernet support */ 57 #define CONFIG_ENV_OVERWRITE 58 59 #define CONFIG_CMD_SATA 60 #define CONFIG_SATA_SIL3114 61 #define CONFIG_SYS_SATA_MAX_DEVICE 2 62 #define CONFIG_LIBATA 63 #define CONFIG_LBA48 64 65 #ifndef __ASSEMBLY__ 66 extern unsigned long get_board_sys_clk(unsigned long dummy); 67 #endif 68 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk(0) /*sysclk for TWR-P1025 */ 69 70 #define CONFIG_DDR_CLK_FREQ 66666666 71 72 #define CONFIG_HWCONFIG 73 /* 74 * These can be toggled for performance analysis, otherwise use default. 75 */ 76 #define CONFIG_L2_CACHE 77 #define CONFIG_BTB 78 79 #define CONFIG_BOARD_EARLY_INIT_F /* Call board_pre_init */ 80 81 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ 82 #define CONFIG_SYS_MEMTEST_END 0x1fffffff 83 #define CONFIG_PANIC_HANG /* do not reset board on panic */ 84 85 #define CONFIG_SYS_CCSRBAR 0xffe00000 86 #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR 87 88 /* DDR Setup */ 89 #define CONFIG_SYS_FSL_DDR3 90 91 #define CONFIG_SYS_SDRAM_SIZE_LAW LAW_SIZE_512M 92 #define CONFIG_CHIP_SELECTS_PER_CTRL 1 93 94 #define CONFIG_SYS_SDRAM_SIZE (1u << (CONFIG_SYS_SDRAM_SIZE_LAW - 19)) 95 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 96 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 97 98 #define CONFIG_NUM_DDR_CONTROLLERS 1 99 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 100 101 /* Default settings for DDR3 */ 102 #define CONFIG_SYS_DDR_CS0_BNDS 0x0000001f 103 #define CONFIG_SYS_DDR_CS0_CONFIG 0x80014202 104 #define CONFIG_SYS_DDR_CS0_CONFIG_2 0x00000000 105 #define CONFIG_SYS_DDR_CS1_BNDS 0x00000000 106 #define CONFIG_SYS_DDR_CS1_CONFIG 0x00000000 107 #define CONFIG_SYS_DDR_CS1_CONFIG_2 0x00000000 108 109 #define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef 110 #define CONFIG_SYS_DDR_INIT_ADDR 0x00000000 111 #define CONFIG_SYS_DDR_INIT_EXT_ADDR 0x00000000 112 #define CONFIG_SYS_DDR_MODE_CONTROL 0x00000000 113 114 #define CONFIG_SYS_DDR_ZQ_CONTROL 0x89080600 115 #define CONFIG_SYS_DDR_WRLVL_CONTROL 0x8655a608 116 #define CONFIG_SYS_DDR_SR_CNTR 0x00000000 117 #define CONFIG_SYS_DDR_RCW_1 0x00000000 118 #define CONFIG_SYS_DDR_RCW_2 0x00000000 119 #define CONFIG_SYS_DDR_CONTROL 0xc70c0000 /* Type = DDR3 */ 120 #define CONFIG_SYS_DDR_CONTROL_2 0x04401050 121 #define CONFIG_SYS_DDR_TIMING_4 0x00220001 122 #define CONFIG_SYS_DDR_TIMING_5 0x03402400 123 124 #define CONFIG_SYS_DDR_TIMING_3 0x00020000 125 #define CONFIG_SYS_DDR_TIMING_0 0x00220004 126 #define CONFIG_SYS_DDR_TIMING_1 0x5c5b6544 127 #define CONFIG_SYS_DDR_TIMING_2 0x0fa880de 128 #define CONFIG_SYS_DDR_CLK_CTRL 0x03000000 129 #define CONFIG_SYS_DDR_MODE_1 0x80461320 130 #define CONFIG_SYS_DDR_MODE_2 0x00008000 131 #define CONFIG_SYS_DDR_INTERVAL 0x09480000 132 133 /* 134 * Memory map 135 * 136 * 0x0000_0000 0x1fff_ffff DDR Up to 512MB cacheable 137 * 0x8000_0000 0xdfff_ffff PCI Express Mem 1.5G non-cacheable(PCIe * 3) 138 * 0xffc0_0000 0xffc3_ffff PCI IO range 256k non-cacheable 139 * 140 * Localbus 141 * 0xe000_0000 0xe002_0000 SSD1289 128K non-cacheable 142 * 0xec00_0000 0xefff_ffff FLASH Up to 64M non-cacheable 143 * 144 * 0xff90_0000 0xff97_ffff L2 SRAM Up to 512K cacheable 145 * 0xffd0_0000 0xffd0_3fff init ram 16K Cacheable 146 * 0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable 147 */ 148 149 /* 150 * Local Bus Definitions 151 */ 152 #define CONFIG_SYS_MAX_FLASH_SECT 512 /* 64M */ 153 #define CONFIG_SYS_FLASH_BASE 0xec000000 154 155 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE 156 157 #define CONFIG_FLASH_BR_PRELIM (BR_PHYS_ADDR((CONFIG_SYS_FLASH_BASE_PHYS)) \ 158 | BR_PS_16 | BR_V) 159 160 #define CONFIG_FLASH_OR_PRELIM 0xfc0000b1 161 162 #define CONFIG_SYS_SSD_BASE 0xe0000000 163 #define CONFIG_SYS_SSD_BASE_PHYS CONFIG_SYS_SSD_BASE 164 #define CONFIG_SSD_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_SSD_BASE_PHYS) | \ 165 BR_PS_16 | BR_V) 166 #define CONFIG_SSD_OR_PRELIM (OR_AM_64KB | OR_GPCM_CSNT | OR_GPCM_XACS | \ 167 OR_GPCM_ACS_DIV2 | OR_GPCM_SCY | \ 168 OR_GPCM_TRLX | OR_GPCM_EHTR | OR_GPCM_EAD) 169 170 #define CONFIG_SYS_BR2_PRELIM CONFIG_SSD_BR_PRELIM 171 #define CONFIG_SYS_OR2_PRELIM CONFIG_SSD_OR_PRELIM 172 173 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS} 174 #define CONFIG_SYS_FLASH_QUIET_TEST 175 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 176 177 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ 178 179 #undef CONFIG_SYS_FLASH_CHECKSUM 180 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 181 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 182 183 #define CONFIG_FLASH_CFI_DRIVER 184 #define CONFIG_SYS_FLASH_CFI 185 #define CONFIG_SYS_FLASH_EMPTY_INFO 186 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 187 188 #define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */ 189 190 #define CONFIG_SYS_INIT_RAM_LOCK 191 #define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 192 /* Initial L1 address */ 193 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS CONFIG_SYS_INIT_RAM_ADDR 194 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0 195 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS 196 /* Size of used area in RAM */ 197 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 198 199 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ 200 GENERATED_GBL_DATA_SIZE) 201 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 202 203 #define CONFIG_SYS_MONITOR_LEN (768 * 1024) 204 #define CONFIG_SYS_MALLOC_LEN (1024 * 1024)/* Reserved for malloc */ 205 206 #define CONFIG_SYS_BR0_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */ 207 #define CONFIG_SYS_OR0_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */ 208 209 /* Serial Port 210 * open - index 2 211 * shorted - index 1 212 */ 213 #define CONFIG_CONS_INDEX 1 214 #undef CONFIG_SERIAL_SOFTWARE_FIFO 215 #define CONFIG_SYS_NS16550_SERIAL 216 #define CONFIG_SYS_NS16550_REG_SIZE 1 217 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) 218 219 #define CONFIG_SYS_BAUDRATE_TABLE \ 220 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} 221 222 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) 223 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) 224 225 /* I2C */ 226 #define CONFIG_SYS_I2C 227 #define CONFIG_SYS_I2C_FSL /* Use FSL common I2C driver */ 228 #define CONFIG_SYS_FSL_I2C_SPEED 400000 /* I2C spd and slave address */ 229 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 230 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 231 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x52 232 233 /* 234 * I2C2 EEPROM 235 */ 236 #define CONFIG_SYS_FSL_I2C2_SPEED 400000 /* I2C spd and slave address */ 237 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F 238 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100 239 240 #define CONFIG_SYS_I2C_PCA9555_ADDR 0x23 241 242 /* enable read and write access to EEPROM */ 243 #define CONFIG_CMD_EEPROM 244 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 245 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 246 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 247 248 /* 249 * eSPI - Enhanced SPI 250 */ 251 #define CONFIG_HARD_SPI 252 253 #if defined(CONFIG_PCI) 254 /* 255 * General PCI 256 * Memory space is mapped 1-1, but I/O space must start from 0. 257 */ 258 259 /* controller 2, direct to uli, tgtid 2, Base address 9000 */ 260 #define CONFIG_SYS_PCIE2_NAME "TWR-ELEV PCIe SLOT" 261 #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000 262 #define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000 263 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000 264 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */ 265 #define CONFIG_SYS_PCIE2_IO_VIRT 0xffc10000 266 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 267 #define CONFIG_SYS_PCIE2_IO_PHYS 0xffc10000 268 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ 269 270 /* controller 1, tgtid 1, Base address a000 */ 271 #define CONFIG_SYS_PCIE1_NAME "mini PCIe SLOT" 272 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 273 #define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000 274 #define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000 275 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ 276 #define CONFIG_SYS_PCIE1_IO_VIRT 0xffc00000 277 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 278 #define CONFIG_SYS_PCIE1_IO_PHYS 0xffc00000 279 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ 280 281 #define CONFIG_CMD_PCI 282 283 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 284 #define CONFIG_DOS_PARTITION 285 #endif /* CONFIG_PCI */ 286 287 #if defined(CONFIG_TSEC_ENET) 288 289 #define CONFIG_MII /* MII PHY management */ 290 #define CONFIG_TSEC1 291 #define CONFIG_TSEC1_NAME "eTSEC1" 292 #undef CONFIG_TSEC2 293 #undef CONFIG_TSEC2_NAME 294 #define CONFIG_TSEC3 295 #define CONFIG_TSEC3_NAME "eTSEC3" 296 297 #define TSEC1_PHY_ADDR 2 298 #define TSEC2_PHY_ADDR 0 299 #define TSEC3_PHY_ADDR 1 300 301 #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 302 #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 303 #define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 304 305 #define TSEC1_PHYIDX 0 306 #define TSEC2_PHYIDX 0 307 #define TSEC3_PHYIDX 0 308 309 #define CONFIG_ETHPRIME "eTSEC1" 310 311 #define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */ 312 313 #define CONFIG_HAS_ETH0 314 #define CONFIG_HAS_ETH1 315 #undef CONFIG_HAS_ETH2 316 #endif /* CONFIG_TSEC_ENET */ 317 318 #ifdef CONFIG_QE 319 /* QE microcode/firmware address */ 320 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR 321 #define CONFIG_SYS_QE_FW_ADDR 0xefec0000 322 #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 323 #endif /* CONFIG_QE */ 324 325 #ifdef CONFIG_TWR_P1025 326 /* 327 * QE UEC ethernet configuration 328 */ 329 #define CONFIG_MIIM_ADDRESS (CONFIG_SYS_CCSRBAR + 0x82120) 330 331 #undef CONFIG_UEC_ETH 332 #define CONFIG_PHY_MODE_NEED_CHANGE 333 334 #define CONFIG_UEC_ETH1 /* ETH1 */ 335 #define CONFIG_HAS_ETH0 336 337 #ifdef CONFIG_UEC_ETH1 338 #define CONFIG_SYS_UEC1_UCC_NUM 0 /* UCC1 */ 339 #define CONFIG_SYS_UEC1_RX_CLK QE_CLK12 /* CLK12 for MII */ 340 #define CONFIG_SYS_UEC1_TX_CLK QE_CLK9 /* CLK9 for MII */ 341 #define CONFIG_SYS_UEC1_ETH_TYPE FAST_ETH 342 #define CONFIG_SYS_UEC1_PHY_ADDR 0x18 /* 0x18 for MII */ 343 #define CONFIG_SYS_UEC1_INTERFACE_TYPE PHY_INTERFACE_MODE_MII 344 #define CONFIG_SYS_UEC1_INTERFACE_SPEED 100 345 #endif /* CONFIG_UEC_ETH1 */ 346 347 #define CONFIG_UEC_ETH5 /* ETH5 */ 348 #define CONFIG_HAS_ETH1 349 350 #ifdef CONFIG_UEC_ETH5 351 #define CONFIG_SYS_UEC5_UCC_NUM 4 /* UCC5 */ 352 #define CONFIG_SYS_UEC5_RX_CLK QE_CLK_NONE 353 #define CONFIG_SYS_UEC5_TX_CLK QE_CLK13 /* CLK 13 for RMII */ 354 #define CONFIG_SYS_UEC5_ETH_TYPE FAST_ETH 355 #define CONFIG_SYS_UEC5_PHY_ADDR 0x19 /* 0x19 for RMII */ 356 #define CONFIG_SYS_UEC5_INTERFACE_TYPE PHY_INTERFACE_MODE_RMII 357 #define CONFIG_SYS_UEC5_INTERFACE_SPEED 100 358 #endif /* CONFIG_UEC_ETH5 */ 359 #endif /* CONFIG_TWR-P1025 */ 360 361 /* 362 * Dynamic MTD Partition support with mtdparts 363 */ 364 #define CONFIG_MTD_DEVICE 365 #define CONFIG_MTD_PARTITIONS 366 #define CONFIG_CMD_MTDPARTS 367 #define CONFIG_FLASH_CFI_MTD 368 #define MTDIDS_DEFAULT "nor0=ec000000.nor" 369 #define MTDPARTS_DEFAULT "mtdparts=ec000000.nor:256k(vsc7385-firmware)," \ 370 "256k(dtb),5632k(kernel),57856k(fs)," \ 371 "256k(qe-ucode-firmware),1280k(u-boot)" 372 373 /* 374 * Environment 375 */ 376 #ifdef CONFIG_SYS_RAMBOOT 377 #ifdef CONFIG_RAMBOOT_SDCARD 378 #define CONFIG_ENV_IS_IN_MMC 379 #define CONFIG_ENV_SIZE 0x2000 380 #define CONFIG_SYS_MMC_ENV_DEV 0 381 #else 382 #define CONFIG_ENV_IS_NOWHERE /* Store ENV in memory only */ 383 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) 384 #define CONFIG_ENV_SIZE 0x2000 385 #endif 386 #else 387 #define CONFIG_ENV_IS_IN_FLASH 388 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) 389 #define CONFIG_ENV_SIZE 0x2000 390 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ 391 #endif 392 393 #define CONFIG_LOADS_ECHO /* echo on for serial download */ 394 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ 395 396 /* 397 * Command line configuration. 398 */ 399 #define CONFIG_CMD_IRQ 400 #define CONFIG_CMD_REGINFO 401 402 /* 403 * USB 404 */ 405 #define CONFIG_HAS_FSL_DR_USB 406 407 #if defined(CONFIG_HAS_FSL_DR_USB) 408 #define CONFIG_USB_EHCI 409 410 #ifdef CONFIG_USB_EHCI 411 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 412 #define CONFIG_USB_EHCI_FSL 413 #endif 414 #endif 415 416 #define CONFIG_MMC 417 418 #ifdef CONFIG_MMC 419 #define CONFIG_FSL_ESDHC 420 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR 421 #define CONFIG_GENERIC_MMC 422 #endif 423 424 #if defined(CONFIG_MMC) || defined(CONFIG_USB_EHCI) \ 425 || defined(CONFIG_FSL_SATA) 426 #define CONFIG_DOS_PARTITION 427 #endif 428 429 #undef CONFIG_WATCHDOG /* watchdog disabled */ 430 431 /* 432 * Miscellaneous configurable options 433 */ 434 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 435 #define CONFIG_CMDLINE_EDITING /* Command-line editing */ 436 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 437 #if defined(CONFIG_CMD_KGDB) 438 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 439 #else 440 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 441 #endif 442 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) 443 /* Print Buffer Size */ 444 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 445 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */ 446 447 /* 448 * For booting Linux, the board info and command line data 449 * have to be in the first 64 MB of memory, since this is 450 * the maximum mapped by the Linux kernel during initialization. 451 */ 452 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory for Linux*/ 453 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 454 455 /* 456 * Environment Configuration 457 */ 458 #define CONFIG_HOSTNAME unknown 459 #define CONFIG_ROOTPATH "/opt/nfsroot" 460 #define CONFIG_BOOTFILE "uImage" 461 #define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */ 462 463 /* default location for tftp and bootm */ 464 #define CONFIG_LOADADDR 1000000 465 466 #define CONFIG_BOOTARGS /* the boot command will set bootargs */ 467 468 #define CONFIG_BAUDRATE 115200 469 470 #define CONFIG_EXTRA_ENV_SETTINGS \ 471 "netdev=eth0\0" \ 472 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ 473 "loadaddr=1000000\0" \ 474 "bootfile=uImage\0" \ 475 "dtbfile=twr-p1025twr.dtb\0" \ 476 "ramdiskfile=rootfs.ext2.gz.uboot\0" \ 477 "qefirmwarefile=fsl_qe_ucode_1021_10_A.bin\0" \ 478 "tftpflash=tftpboot $loadaddr $uboot; " \ 479 "protect off " __stringify(CONFIG_SYS_TEXT_BASE) " +$filesize; " \ 480 "erase " __stringify(CONFIG_SYS_TEXT_BASE) " +$filesize; " \ 481 "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) " $filesize; " \ 482 "protect on " __stringify(CONFIG_SYS_TEXT_BASE) " +$filesize; " \ 483 "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) " $filesize\0" \ 484 "kernelflash=tftpboot $loadaddr $bootfile; " \ 485 "protect off 0xefa80000 +$filesize; " \ 486 "erase 0xefa80000 +$filesize; " \ 487 "cp.b $loadaddr 0xefa80000 $filesize; " \ 488 "protect on 0xefa80000 +$filesize; " \ 489 "cmp.b $loadaddr 0xefa80000 $filesize\0" \ 490 "dtbflash=tftpboot $loadaddr $dtbfile; " \ 491 "protect off 0xefe80000 +$filesize; " \ 492 "erase 0xefe80000 +$filesize; " \ 493 "cp.b $loadaddr 0xefe80000 $filesize; " \ 494 "protect on 0xefe80000 +$filesize; " \ 495 "cmp.b $loadaddr 0xefe80000 $filesize\0" \ 496 "ramdiskflash=tftpboot $loadaddr $ramdiskfile; " \ 497 "protect off 0xeeb80000 +$filesize; " \ 498 "erase 0xeeb80000 +$filesize; " \ 499 "cp.b $loadaddr 0xeeb80000 $filesize; " \ 500 "protect on 0xeeb80000 +$filesize; " \ 501 "cmp.b $loadaddr 0xeeb80000 $filesize\0" \ 502 "qefirmwareflash=tftpboot $loadaddr $qefirmwarefile; " \ 503 "protect off 0xefec0000 +$filesize; " \ 504 "erase 0xefec0000 +$filesize; " \ 505 "cp.b $loadaddr 0xefec0000 $filesize; " \ 506 "protect on 0xefec0000 +$filesize; " \ 507 "cmp.b $loadaddr 0xefec0000 $filesize\0" \ 508 "consoledev=ttyS0\0" \ 509 "ramdiskaddr=2000000\0" \ 510 "ramdiskfile=rootfs.ext2.gz.uboot\0" \ 511 "fdtaddr=1e00000\0" \ 512 "bdev=sda1\0" \ 513 "norbootaddr=ef080000\0" \ 514 "norfdtaddr=ef040000\0" \ 515 "ramdisk_size=120000\0" \ 516 "usbboot=setenv bootargs root=/dev/sda1 rw rootdelay=5 " \ 517 "console=$consoledev,$baudrate $othbootargs ; bootm 0xefa80000 - 0xefe80000" 518 519 #define CONFIG_NFSBOOTCOMMAND \ 520 "setenv bootargs root=/dev/nfs rw " \ 521 "nfsroot=$serverip:$rootpath " \ 522 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 523 "console=$consoledev,$baudrate $othbootargs;" \ 524 "tftp $loadaddr $bootfile&&" \ 525 "tftp $fdtaddr $fdtfile&&" \ 526 "bootm $loadaddr - $fdtaddr" 527 528 #define CONFIG_HDBOOT \ 529 "setenv bootargs root=/dev/$bdev rw rootdelay=30 " \ 530 "console=$consoledev,$baudrate $othbootargs;" \ 531 "usb start;" \ 532 "ext2load usb 0:1 $loadaddr /boot/$bootfile;" \ 533 "ext2load usb 0:1 $fdtaddr /boot/$fdtfile;" \ 534 "bootm $loadaddr - $fdtaddr" 535 536 #define CONFIG_USB_FAT_BOOT \ 537 "setenv bootargs root=/dev/ram rw " \ 538 "console=$consoledev,$baudrate $othbootargs " \ 539 "ramdisk_size=$ramdisk_size;" \ 540 "usb start;" \ 541 "fatload usb 0:2 $loadaddr $bootfile;" \ 542 "fatload usb 0:2 $fdtaddr $fdtfile;" \ 543 "fatload usb 0:2 $ramdiskaddr $ramdiskfile;" \ 544 "bootm $loadaddr $ramdiskaddr $fdtaddr" 545 546 #define CONFIG_USB_EXT2_BOOT \ 547 "setenv bootargs root=/dev/ram rw " \ 548 "console=$consoledev,$baudrate $othbootargs " \ 549 "ramdisk_size=$ramdisk_size;" \ 550 "usb start;" \ 551 "ext2load usb 0:4 $loadaddr $bootfile;" \ 552 "ext2load usb 0:4 $fdtaddr $fdtfile;" \ 553 "ext2load usb 0:4 $ramdiskaddr $ramdiskfile;" \ 554 "bootm $loadaddr $ramdiskaddr $fdtaddr" 555 556 #define CONFIG_NORBOOT \ 557 "setenv bootargs root=/dev/mtdblock3 rw " \ 558 "console=$consoledev,$baudrate rootfstype=jffs2 $othbootargs;" \ 559 "bootm $norbootaddr - $norfdtaddr" 560 561 #define CONFIG_RAMBOOTCOMMAND_TFTP \ 562 "setenv bootargs root=/dev/ram rw " \ 563 "console=$consoledev,$baudrate $othbootargs " \ 564 "ramdisk_size=$ramdisk_size;" \ 565 "tftp $ramdiskaddr $ramdiskfile;" \ 566 "tftp $loadaddr $bootfile;" \ 567 "tftp $fdtaddr $fdtfile;" \ 568 "bootm $loadaddr $ramdiskaddr $fdtaddr" 569 570 #define CONFIG_RAMBOOTCOMMAND \ 571 "setenv bootargs root=/dev/ram rw " \ 572 "console=$consoledev,$baudrate $othbootargs " \ 573 "ramdisk_size=$ramdisk_size;" \ 574 "bootm 0xefa80000 0xeeb80000 0xefe80000" 575 576 #define CONFIG_BOOTCOMMAND CONFIG_RAMBOOTCOMMAND 577 578 #endif /* __CONFIG_H */ 579