1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * Copyright 2013 Freescale Semiconductor, Inc. 4 */ 5 6 /* 7 * QorIQ P1 Tower boards configuration file 8 */ 9 #ifndef __CONFIG_H 10 #define __CONFIG_H 11 12 #if defined(CONFIG_TWR_P1025) 13 #define CONFIG_BOARDNAME "TWR-P1025" 14 #define CONFIG_PHY_ATHEROS 15 #define CONFIG_QE 16 #define CONFIG_SYS_LBC_LBCR 0x00080000 /* Conversion of LBC addr */ 17 #define CONFIG_SYS_LBC_LCRR 0x80000002 /* LB clock ratio reg */ 18 #endif 19 20 #ifdef CONFIG_SDCARD 21 #define CONFIG_RAMBOOT_SDCARD 22 #define CONFIG_SYS_RAMBOOT 23 #define CONFIG_SYS_EXTRA_ENV_RELOC 24 #define CONFIG_RESET_VECTOR_ADDRESS 0x110bfffc 25 #endif 26 27 #ifndef CONFIG_RESET_VECTOR_ADDRESS 28 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc 29 #endif 30 31 #ifndef CONFIG_SYS_MONITOR_BASE 32 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 33 #endif 34 35 #define CONFIG_MP 36 37 #define CONFIG_PCIE1 /* PCIE controller 1 (slot 1) */ 38 #define CONFIG_PCIE2 /* PCIE controller 2 (slot 2) */ 39 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ 40 #define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */ 41 #define CONFIG_FSL_PCIE_RESET /* need PCIe reset errata */ 42 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ 43 44 #define CONFIG_ENV_OVERWRITE 45 46 #define CONFIG_SYS_SATA_MAX_DEVICE 2 47 #define CONFIG_LBA48 48 49 #ifndef __ASSEMBLY__ 50 extern unsigned long get_board_sys_clk(unsigned long dummy); 51 #endif 52 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk(0) /*sysclk for TWR-P1025 */ 53 54 #define CONFIG_DDR_CLK_FREQ 66666666 55 56 #define CONFIG_HWCONFIG 57 /* 58 * These can be toggled for performance analysis, otherwise use default. 59 */ 60 #define CONFIG_L2_CACHE 61 #define CONFIG_BTB 62 63 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ 64 #define CONFIG_SYS_MEMTEST_END 0x1fffffff 65 66 #define CONFIG_SYS_CCSRBAR 0xffe00000 67 #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR 68 69 /* DDR Setup */ 70 71 #define CONFIG_SYS_SDRAM_SIZE_LAW LAW_SIZE_512M 72 #define CONFIG_CHIP_SELECTS_PER_CTRL 1 73 74 #define CONFIG_SYS_SDRAM_SIZE (1u << (CONFIG_SYS_SDRAM_SIZE_LAW - 19)) 75 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 76 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 77 78 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 79 80 /* Default settings for DDR3 */ 81 #define CONFIG_SYS_DDR_CS0_BNDS 0x0000001f 82 #define CONFIG_SYS_DDR_CS0_CONFIG 0x80014202 83 #define CONFIG_SYS_DDR_CS0_CONFIG_2 0x00000000 84 #define CONFIG_SYS_DDR_CS1_BNDS 0x00000000 85 #define CONFIG_SYS_DDR_CS1_CONFIG 0x00000000 86 #define CONFIG_SYS_DDR_CS1_CONFIG_2 0x00000000 87 88 #define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef 89 #define CONFIG_SYS_DDR_INIT_ADDR 0x00000000 90 #define CONFIG_SYS_DDR_INIT_EXT_ADDR 0x00000000 91 #define CONFIG_SYS_DDR_MODE_CONTROL 0x00000000 92 93 #define CONFIG_SYS_DDR_ZQ_CONTROL 0x89080600 94 #define CONFIG_SYS_DDR_WRLVL_CONTROL 0x8655a608 95 #define CONFIG_SYS_DDR_SR_CNTR 0x00000000 96 #define CONFIG_SYS_DDR_RCW_1 0x00000000 97 #define CONFIG_SYS_DDR_RCW_2 0x00000000 98 #define CONFIG_SYS_DDR_CONTROL 0xc70c0000 /* Type = DDR3 */ 99 #define CONFIG_SYS_DDR_CONTROL_2 0x04401050 100 #define CONFIG_SYS_DDR_TIMING_4 0x00220001 101 #define CONFIG_SYS_DDR_TIMING_5 0x03402400 102 103 #define CONFIG_SYS_DDR_TIMING_3 0x00020000 104 #define CONFIG_SYS_DDR_TIMING_0 0x00220004 105 #define CONFIG_SYS_DDR_TIMING_1 0x5c5b6544 106 #define CONFIG_SYS_DDR_TIMING_2 0x0fa880de 107 #define CONFIG_SYS_DDR_CLK_CTRL 0x03000000 108 #define CONFIG_SYS_DDR_MODE_1 0x80461320 109 #define CONFIG_SYS_DDR_MODE_2 0x00008000 110 #define CONFIG_SYS_DDR_INTERVAL 0x09480000 111 112 /* 113 * Memory map 114 * 115 * 0x0000_0000 0x1fff_ffff DDR Up to 512MB cacheable 116 * 0x8000_0000 0xdfff_ffff PCI Express Mem 1.5G non-cacheable(PCIe * 3) 117 * 0xffc0_0000 0xffc3_ffff PCI IO range 256k non-cacheable 118 * 119 * Localbus 120 * 0xe000_0000 0xe002_0000 SSD1289 128K non-cacheable 121 * 0xec00_0000 0xefff_ffff FLASH Up to 64M non-cacheable 122 * 123 * 0xff90_0000 0xff97_ffff L2 SRAM Up to 512K cacheable 124 * 0xffd0_0000 0xffd0_3fff init ram 16K Cacheable 125 * 0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable 126 */ 127 128 /* 129 * Local Bus Definitions 130 */ 131 #define CONFIG_SYS_MAX_FLASH_SECT 512 /* 64M */ 132 #define CONFIG_SYS_FLASH_BASE 0xec000000 133 134 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE 135 136 #define CONFIG_FLASH_BR_PRELIM (BR_PHYS_ADDR((CONFIG_SYS_FLASH_BASE_PHYS)) \ 137 | BR_PS_16 | BR_V) 138 139 #define CONFIG_FLASH_OR_PRELIM 0xfc0000b1 140 141 #define CONFIG_SYS_SSD_BASE 0xe0000000 142 #define CONFIG_SYS_SSD_BASE_PHYS CONFIG_SYS_SSD_BASE 143 #define CONFIG_SSD_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_SSD_BASE_PHYS) | \ 144 BR_PS_16 | BR_V) 145 #define CONFIG_SSD_OR_PRELIM (OR_AM_64KB | OR_GPCM_CSNT | OR_GPCM_XACS | \ 146 OR_GPCM_ACS_DIV2 | OR_GPCM_SCY | \ 147 OR_GPCM_TRLX | OR_GPCM_EHTR | OR_GPCM_EAD) 148 149 #define CONFIG_SYS_BR2_PRELIM CONFIG_SSD_BR_PRELIM 150 #define CONFIG_SYS_OR2_PRELIM CONFIG_SSD_OR_PRELIM 151 152 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS} 153 #define CONFIG_SYS_FLASH_QUIET_TEST 154 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 155 156 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ 157 158 #undef CONFIG_SYS_FLASH_CHECKSUM 159 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 160 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 161 162 #define CONFIG_FLASH_CFI_DRIVER 163 #define CONFIG_SYS_FLASH_CFI 164 #define CONFIG_SYS_FLASH_EMPTY_INFO 165 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 166 167 #define CONFIG_SYS_INIT_RAM_LOCK 168 #define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 169 /* Initial L1 address */ 170 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS CONFIG_SYS_INIT_RAM_ADDR 171 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0 172 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS 173 /* Size of used area in RAM */ 174 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 175 176 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ 177 GENERATED_GBL_DATA_SIZE) 178 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 179 180 #define CONFIG_SYS_MONITOR_LEN (768 * 1024) 181 #define CONFIG_SYS_MALLOC_LEN (1024 * 1024)/* Reserved for malloc */ 182 183 #define CONFIG_SYS_BR0_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */ 184 #define CONFIG_SYS_OR0_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */ 185 186 /* Serial Port 187 * open - index 2 188 * shorted - index 1 189 */ 190 #undef CONFIG_SERIAL_SOFTWARE_FIFO 191 #define CONFIG_SYS_NS16550_SERIAL 192 #define CONFIG_SYS_NS16550_REG_SIZE 1 193 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) 194 195 #define CONFIG_SYS_BAUDRATE_TABLE \ 196 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} 197 198 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) 199 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) 200 201 /* I2C */ 202 #define CONFIG_SYS_I2C 203 #define CONFIG_SYS_I2C_FSL /* Use FSL common I2C driver */ 204 #define CONFIG_SYS_FSL_I2C_SPEED 400000 /* I2C spd and slave address */ 205 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 206 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 207 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x52 208 209 /* 210 * I2C2 EEPROM 211 */ 212 #define CONFIG_SYS_FSL_I2C2_SPEED 400000 /* I2C spd and slave address */ 213 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F 214 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100 215 216 #define CONFIG_SYS_I2C_PCA9555_ADDR 0x23 217 218 /* enable read and write access to EEPROM */ 219 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 220 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 221 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 222 223 /* 224 * eSPI - Enhanced SPI 225 */ 226 #define CONFIG_HARD_SPI 227 228 #if defined(CONFIG_PCI) 229 /* 230 * General PCI 231 * Memory space is mapped 1-1, but I/O space must start from 0. 232 */ 233 234 /* controller 2, direct to uli, tgtid 2, Base address 9000 */ 235 #define CONFIG_SYS_PCIE2_NAME "TWR-ELEV PCIe SLOT" 236 #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000 237 #define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000 238 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000 239 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */ 240 #define CONFIG_SYS_PCIE2_IO_VIRT 0xffc10000 241 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 242 #define CONFIG_SYS_PCIE2_IO_PHYS 0xffc10000 243 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ 244 245 /* controller 1, tgtid 1, Base address a000 */ 246 #define CONFIG_SYS_PCIE1_NAME "mini PCIe SLOT" 247 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 248 #define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000 249 #define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000 250 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ 251 #define CONFIG_SYS_PCIE1_IO_VIRT 0xffc00000 252 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 253 #define CONFIG_SYS_PCIE1_IO_PHYS 0xffc00000 254 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ 255 256 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 257 #endif /* CONFIG_PCI */ 258 259 #if defined(CONFIG_TSEC_ENET) 260 261 #define CONFIG_MII /* MII PHY management */ 262 #define CONFIG_TSEC1 263 #define CONFIG_TSEC1_NAME "eTSEC1" 264 #undef CONFIG_TSEC2 265 #undef CONFIG_TSEC2_NAME 266 #define CONFIG_TSEC3 267 #define CONFIG_TSEC3_NAME "eTSEC3" 268 269 #define TSEC1_PHY_ADDR 2 270 #define TSEC2_PHY_ADDR 0 271 #define TSEC3_PHY_ADDR 1 272 273 #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 274 #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 275 #define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 276 277 #define TSEC1_PHYIDX 0 278 #define TSEC2_PHYIDX 0 279 #define TSEC3_PHYIDX 0 280 281 #define CONFIG_ETHPRIME "eTSEC1" 282 283 #define CONFIG_HAS_ETH0 284 #define CONFIG_HAS_ETH1 285 #undef CONFIG_HAS_ETH2 286 #endif /* CONFIG_TSEC_ENET */ 287 288 #ifdef CONFIG_QE 289 /* QE microcode/firmware address */ 290 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR 291 #define CONFIG_SYS_QE_FW_ADDR 0xefec0000 292 #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 293 #endif /* CONFIG_QE */ 294 295 #ifdef CONFIG_TWR_P1025 296 /* 297 * QE UEC ethernet configuration 298 */ 299 #define CONFIG_MIIM_ADDRESS (CONFIG_SYS_CCSRBAR + 0x82120) 300 301 #undef CONFIG_UEC_ETH 302 #define CONFIG_PHY_MODE_NEED_CHANGE 303 304 #define CONFIG_UEC_ETH1 /* ETH1 */ 305 #define CONFIG_HAS_ETH0 306 307 #ifdef CONFIG_UEC_ETH1 308 #define CONFIG_SYS_UEC1_UCC_NUM 0 /* UCC1 */ 309 #define CONFIG_SYS_UEC1_RX_CLK QE_CLK12 /* CLK12 for MII */ 310 #define CONFIG_SYS_UEC1_TX_CLK QE_CLK9 /* CLK9 for MII */ 311 #define CONFIG_SYS_UEC1_ETH_TYPE FAST_ETH 312 #define CONFIG_SYS_UEC1_PHY_ADDR 0x18 /* 0x18 for MII */ 313 #define CONFIG_SYS_UEC1_INTERFACE_TYPE PHY_INTERFACE_MODE_MII 314 #define CONFIG_SYS_UEC1_INTERFACE_SPEED 100 315 #endif /* CONFIG_UEC_ETH1 */ 316 317 #define CONFIG_UEC_ETH5 /* ETH5 */ 318 #define CONFIG_HAS_ETH1 319 320 #ifdef CONFIG_UEC_ETH5 321 #define CONFIG_SYS_UEC5_UCC_NUM 4 /* UCC5 */ 322 #define CONFIG_SYS_UEC5_RX_CLK QE_CLK_NONE 323 #define CONFIG_SYS_UEC5_TX_CLK QE_CLK13 /* CLK 13 for RMII */ 324 #define CONFIG_SYS_UEC5_ETH_TYPE FAST_ETH 325 #define CONFIG_SYS_UEC5_PHY_ADDR 0x19 /* 0x19 for RMII */ 326 #define CONFIG_SYS_UEC5_INTERFACE_TYPE PHY_INTERFACE_MODE_RMII 327 #define CONFIG_SYS_UEC5_INTERFACE_SPEED 100 328 #endif /* CONFIG_UEC_ETH5 */ 329 #endif /* CONFIG_TWR-P1025 */ 330 331 /* 332 * Dynamic MTD Partition support with mtdparts 333 */ 334 #define CONFIG_MTD_DEVICE 335 #define CONFIG_MTD_PARTITIONS 336 #define CONFIG_FLASH_CFI_MTD 337 338 /* 339 * Environment 340 */ 341 #ifdef CONFIG_SYS_RAMBOOT 342 #ifdef CONFIG_RAMBOOT_SDCARD 343 #define CONFIG_ENV_SIZE 0x2000 344 #define CONFIG_SYS_MMC_ENV_DEV 0 345 #else 346 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) 347 #define CONFIG_ENV_SIZE 0x2000 348 #endif 349 #else 350 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) 351 #define CONFIG_ENV_SIZE 0x2000 352 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ 353 #endif 354 355 #define CONFIG_LOADS_ECHO /* echo on for serial download */ 356 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ 357 358 /* 359 * USB 360 */ 361 #define CONFIG_HAS_FSL_DR_USB 362 363 #if defined(CONFIG_HAS_FSL_DR_USB) 364 #ifdef CONFIG_USB_EHCI_HCD 365 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 366 #define CONFIG_USB_EHCI_FSL 367 #endif 368 #endif 369 370 #ifdef CONFIG_MMC 371 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR 372 #endif 373 374 #undef CONFIG_WATCHDOG /* watchdog disabled */ 375 376 /* 377 * Miscellaneous configurable options 378 */ 379 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 380 381 /* 382 * For booting Linux, the board info and command line data 383 * have to be in the first 64 MB of memory, since this is 384 * the maximum mapped by the Linux kernel during initialization. 385 */ 386 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory for Linux*/ 387 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 388 389 /* 390 * Environment Configuration 391 */ 392 #define CONFIG_HOSTNAME "unknown" 393 #define CONFIG_ROOTPATH "/opt/nfsroot" 394 #define CONFIG_BOOTFILE "uImage" 395 #define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */ 396 397 /* default location for tftp and bootm */ 398 #define CONFIG_LOADADDR 1000000 399 400 #define CONFIG_EXTRA_ENV_SETTINGS \ 401 "netdev=eth0\0" \ 402 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ 403 "loadaddr=1000000\0" \ 404 "bootfile=uImage\0" \ 405 "dtbfile=twr-p1025twr.dtb\0" \ 406 "ramdiskfile=rootfs.ext2.gz.uboot\0" \ 407 "qefirmwarefile=fsl_qe_ucode_1021_10_A.bin\0" \ 408 "tftpflash=tftpboot $loadaddr $uboot; " \ 409 "protect off " __stringify(CONFIG_SYS_TEXT_BASE) " +$filesize; " \ 410 "erase " __stringify(CONFIG_SYS_TEXT_BASE) " +$filesize; " \ 411 "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) " $filesize; " \ 412 "protect on " __stringify(CONFIG_SYS_TEXT_BASE) " +$filesize; " \ 413 "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) " $filesize\0" \ 414 "kernelflash=tftpboot $loadaddr $bootfile; " \ 415 "protect off 0xefa80000 +$filesize; " \ 416 "erase 0xefa80000 +$filesize; " \ 417 "cp.b $loadaddr 0xefa80000 $filesize; " \ 418 "protect on 0xefa80000 +$filesize; " \ 419 "cmp.b $loadaddr 0xefa80000 $filesize\0" \ 420 "dtbflash=tftpboot $loadaddr $dtbfile; " \ 421 "protect off 0xefe80000 +$filesize; " \ 422 "erase 0xefe80000 +$filesize; " \ 423 "cp.b $loadaddr 0xefe80000 $filesize; " \ 424 "protect on 0xefe80000 +$filesize; " \ 425 "cmp.b $loadaddr 0xefe80000 $filesize\0" \ 426 "ramdiskflash=tftpboot $loadaddr $ramdiskfile; " \ 427 "protect off 0xeeb80000 +$filesize; " \ 428 "erase 0xeeb80000 +$filesize; " \ 429 "cp.b $loadaddr 0xeeb80000 $filesize; " \ 430 "protect on 0xeeb80000 +$filesize; " \ 431 "cmp.b $loadaddr 0xeeb80000 $filesize\0" \ 432 "qefirmwareflash=tftpboot $loadaddr $qefirmwarefile; " \ 433 "protect off 0xefec0000 +$filesize; " \ 434 "erase 0xefec0000 +$filesize; " \ 435 "cp.b $loadaddr 0xefec0000 $filesize; " \ 436 "protect on 0xefec0000 +$filesize; " \ 437 "cmp.b $loadaddr 0xefec0000 $filesize\0" \ 438 "consoledev=ttyS0\0" \ 439 "ramdiskaddr=2000000\0" \ 440 "ramdiskfile=rootfs.ext2.gz.uboot\0" \ 441 "fdtaddr=1e00000\0" \ 442 "bdev=sda1\0" \ 443 "norbootaddr=ef080000\0" \ 444 "norfdtaddr=ef040000\0" \ 445 "ramdisk_size=120000\0" \ 446 "usbboot=setenv bootargs root=/dev/sda1 rw rootdelay=5 " \ 447 "console=$consoledev,$baudrate $othbootargs ; bootm 0xefa80000 - 0xefe80000" 448 449 #define CONFIG_NFSBOOTCOMMAND \ 450 "setenv bootargs root=/dev/nfs rw " \ 451 "nfsroot=$serverip:$rootpath " \ 452 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 453 "console=$consoledev,$baudrate $othbootargs;" \ 454 "tftp $loadaddr $bootfile&&" \ 455 "tftp $fdtaddr $fdtfile&&" \ 456 "bootm $loadaddr - $fdtaddr" 457 458 #define CONFIG_HDBOOT \ 459 "setenv bootargs root=/dev/$bdev rw rootdelay=30 " \ 460 "console=$consoledev,$baudrate $othbootargs;" \ 461 "usb start;" \ 462 "ext2load usb 0:1 $loadaddr /boot/$bootfile;" \ 463 "ext2load usb 0:1 $fdtaddr /boot/$fdtfile;" \ 464 "bootm $loadaddr - $fdtaddr" 465 466 #define CONFIG_USB_FAT_BOOT \ 467 "setenv bootargs root=/dev/ram rw " \ 468 "console=$consoledev,$baudrate $othbootargs " \ 469 "ramdisk_size=$ramdisk_size;" \ 470 "usb start;" \ 471 "fatload usb 0:2 $loadaddr $bootfile;" \ 472 "fatload usb 0:2 $fdtaddr $fdtfile;" \ 473 "fatload usb 0:2 $ramdiskaddr $ramdiskfile;" \ 474 "bootm $loadaddr $ramdiskaddr $fdtaddr" 475 476 #define CONFIG_USB_EXT2_BOOT \ 477 "setenv bootargs root=/dev/ram rw " \ 478 "console=$consoledev,$baudrate $othbootargs " \ 479 "ramdisk_size=$ramdisk_size;" \ 480 "usb start;" \ 481 "ext2load usb 0:4 $loadaddr $bootfile;" \ 482 "ext2load usb 0:4 $fdtaddr $fdtfile;" \ 483 "ext2load usb 0:4 $ramdiskaddr $ramdiskfile;" \ 484 "bootm $loadaddr $ramdiskaddr $fdtaddr" 485 486 #define CONFIG_NORBOOT \ 487 "setenv bootargs root=/dev/mtdblock3 rw " \ 488 "console=$consoledev,$baudrate rootfstype=jffs2 $othbootargs;" \ 489 "bootm $norbootaddr - $norfdtaddr" 490 491 #define CONFIG_RAMBOOTCOMMAND_TFTP \ 492 "setenv bootargs root=/dev/ram rw " \ 493 "console=$consoledev,$baudrate $othbootargs " \ 494 "ramdisk_size=$ramdisk_size;" \ 495 "tftp $ramdiskaddr $ramdiskfile;" \ 496 "tftp $loadaddr $bootfile;" \ 497 "tftp $fdtaddr $fdtfile;" \ 498 "bootm $loadaddr $ramdiskaddr $fdtaddr" 499 500 #define CONFIG_RAMBOOTCOMMAND \ 501 "setenv bootargs root=/dev/ram rw " \ 502 "console=$consoledev,$baudrate $othbootargs " \ 503 "ramdisk_size=$ramdisk_size;" \ 504 "bootm 0xefa80000 0xeeb80000 0xefe80000" 505 506 #define CONFIG_BOOTCOMMAND CONFIG_RAMBOOTCOMMAND 507 508 #endif /* __CONFIG_H */ 509