1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * Copyright 2013 Freescale Semiconductor, Inc. 4 */ 5 6 /* 7 * QorIQ P1 Tower boards configuration file 8 */ 9 #ifndef __CONFIG_H 10 #define __CONFIG_H 11 12 #if defined(CONFIG_TWR_P1025) 13 #define CONFIG_BOARDNAME "TWR-P1025" 14 #define CONFIG_PHY_ATHEROS 15 #define CONFIG_QE 16 #define CONFIG_SYS_LBC_LBCR 0x00080000 /* Conversion of LBC addr */ 17 #define CONFIG_SYS_LBC_LCRR 0x80000002 /* LB clock ratio reg */ 18 #endif 19 20 #ifdef CONFIG_SDCARD 21 #define CONFIG_RAMBOOT_SDCARD 22 #define CONFIG_SYS_RAMBOOT 23 #define CONFIG_SYS_EXTRA_ENV_RELOC 24 #define CONFIG_RESET_VECTOR_ADDRESS 0x110bfffc 25 #endif 26 27 #ifndef CONFIG_RESET_VECTOR_ADDRESS 28 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc 29 #endif 30 31 #ifndef CONFIG_SYS_MONITOR_BASE 32 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 33 #endif 34 35 #define CONFIG_PCIE1 /* PCIE controller 1 (slot 1) */ 36 #define CONFIG_PCIE2 /* PCIE controller 2 (slot 2) */ 37 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ 38 #define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */ 39 #define CONFIG_FSL_PCIE_RESET /* need PCIe reset errata */ 40 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ 41 42 #define CONFIG_ENV_OVERWRITE 43 44 #define CONFIG_SYS_SATA_MAX_DEVICE 2 45 #define CONFIG_LBA48 46 47 #ifndef __ASSEMBLY__ 48 extern unsigned long get_board_sys_clk(unsigned long dummy); 49 #endif 50 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk(0) /*sysclk for TWR-P1025 */ 51 52 #define CONFIG_DDR_CLK_FREQ 66666666 53 54 #define CONFIG_HWCONFIG 55 /* 56 * These can be toggled for performance analysis, otherwise use default. 57 */ 58 #define CONFIG_L2_CACHE 59 #define CONFIG_BTB 60 61 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ 62 #define CONFIG_SYS_MEMTEST_END 0x1fffffff 63 64 #define CONFIG_SYS_CCSRBAR 0xffe00000 65 #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR 66 67 /* DDR Setup */ 68 69 #define CONFIG_SYS_SDRAM_SIZE_LAW LAW_SIZE_512M 70 #define CONFIG_CHIP_SELECTS_PER_CTRL 1 71 72 #define CONFIG_SYS_SDRAM_SIZE (1u << (CONFIG_SYS_SDRAM_SIZE_LAW - 19)) 73 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 74 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 75 76 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 77 78 /* Default settings for DDR3 */ 79 #define CONFIG_SYS_DDR_CS0_BNDS 0x0000001f 80 #define CONFIG_SYS_DDR_CS0_CONFIG 0x80014202 81 #define CONFIG_SYS_DDR_CS0_CONFIG_2 0x00000000 82 #define CONFIG_SYS_DDR_CS1_BNDS 0x00000000 83 #define CONFIG_SYS_DDR_CS1_CONFIG 0x00000000 84 #define CONFIG_SYS_DDR_CS1_CONFIG_2 0x00000000 85 86 #define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef 87 #define CONFIG_SYS_DDR_INIT_ADDR 0x00000000 88 #define CONFIG_SYS_DDR_INIT_EXT_ADDR 0x00000000 89 #define CONFIG_SYS_DDR_MODE_CONTROL 0x00000000 90 91 #define CONFIG_SYS_DDR_ZQ_CONTROL 0x89080600 92 #define CONFIG_SYS_DDR_WRLVL_CONTROL 0x8655a608 93 #define CONFIG_SYS_DDR_SR_CNTR 0x00000000 94 #define CONFIG_SYS_DDR_RCW_1 0x00000000 95 #define CONFIG_SYS_DDR_RCW_2 0x00000000 96 #define CONFIG_SYS_DDR_CONTROL 0xc70c0000 /* Type = DDR3 */ 97 #define CONFIG_SYS_DDR_CONTROL_2 0x04401050 98 #define CONFIG_SYS_DDR_TIMING_4 0x00220001 99 #define CONFIG_SYS_DDR_TIMING_5 0x03402400 100 101 #define CONFIG_SYS_DDR_TIMING_3 0x00020000 102 #define CONFIG_SYS_DDR_TIMING_0 0x00220004 103 #define CONFIG_SYS_DDR_TIMING_1 0x5c5b6544 104 #define CONFIG_SYS_DDR_TIMING_2 0x0fa880de 105 #define CONFIG_SYS_DDR_CLK_CTRL 0x03000000 106 #define CONFIG_SYS_DDR_MODE_1 0x80461320 107 #define CONFIG_SYS_DDR_MODE_2 0x00008000 108 #define CONFIG_SYS_DDR_INTERVAL 0x09480000 109 110 /* 111 * Memory map 112 * 113 * 0x0000_0000 0x1fff_ffff DDR Up to 512MB cacheable 114 * 0x8000_0000 0xdfff_ffff PCI Express Mem 1.5G non-cacheable(PCIe * 3) 115 * 0xffc0_0000 0xffc3_ffff PCI IO range 256k non-cacheable 116 * 117 * Localbus 118 * 0xe000_0000 0xe002_0000 SSD1289 128K non-cacheable 119 * 0xec00_0000 0xefff_ffff FLASH Up to 64M non-cacheable 120 * 121 * 0xff90_0000 0xff97_ffff L2 SRAM Up to 512K cacheable 122 * 0xffd0_0000 0xffd0_3fff init ram 16K Cacheable 123 * 0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable 124 */ 125 126 /* 127 * Local Bus Definitions 128 */ 129 #define CONFIG_SYS_MAX_FLASH_SECT 512 /* 64M */ 130 #define CONFIG_SYS_FLASH_BASE 0xec000000 131 132 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE 133 134 #define CONFIG_FLASH_BR_PRELIM (BR_PHYS_ADDR((CONFIG_SYS_FLASH_BASE_PHYS)) \ 135 | BR_PS_16 | BR_V) 136 137 #define CONFIG_FLASH_OR_PRELIM 0xfc0000b1 138 139 #define CONFIG_SYS_SSD_BASE 0xe0000000 140 #define CONFIG_SYS_SSD_BASE_PHYS CONFIG_SYS_SSD_BASE 141 #define CONFIG_SSD_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_SSD_BASE_PHYS) | \ 142 BR_PS_16 | BR_V) 143 #define CONFIG_SSD_OR_PRELIM (OR_AM_64KB | OR_GPCM_CSNT | OR_GPCM_XACS | \ 144 OR_GPCM_ACS_DIV2 | OR_GPCM_SCY | \ 145 OR_GPCM_TRLX | OR_GPCM_EHTR | OR_GPCM_EAD) 146 147 #define CONFIG_SYS_BR2_PRELIM CONFIG_SSD_BR_PRELIM 148 #define CONFIG_SYS_OR2_PRELIM CONFIG_SSD_OR_PRELIM 149 150 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS} 151 #define CONFIG_SYS_FLASH_QUIET_TEST 152 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 153 154 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ 155 156 #undef CONFIG_SYS_FLASH_CHECKSUM 157 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 158 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 159 160 #define CONFIG_FLASH_CFI_DRIVER 161 #define CONFIG_SYS_FLASH_CFI 162 #define CONFIG_SYS_FLASH_EMPTY_INFO 163 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 164 165 #define CONFIG_SYS_INIT_RAM_LOCK 166 #define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 167 /* Initial L1 address */ 168 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS CONFIG_SYS_INIT_RAM_ADDR 169 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0 170 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS 171 /* Size of used area in RAM */ 172 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 173 174 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ 175 GENERATED_GBL_DATA_SIZE) 176 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 177 178 #define CONFIG_SYS_MONITOR_LEN (768 * 1024) 179 #define CONFIG_SYS_MALLOC_LEN (1024 * 1024)/* Reserved for malloc */ 180 181 #define CONFIG_SYS_BR0_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */ 182 #define CONFIG_SYS_OR0_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */ 183 184 /* Serial Port 185 * open - index 2 186 * shorted - index 1 187 */ 188 #undef CONFIG_SERIAL_SOFTWARE_FIFO 189 #define CONFIG_SYS_NS16550_SERIAL 190 #define CONFIG_SYS_NS16550_REG_SIZE 1 191 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) 192 193 #define CONFIG_SYS_BAUDRATE_TABLE \ 194 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} 195 196 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) 197 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) 198 199 /* I2C */ 200 #define CONFIG_SYS_I2C 201 #define CONFIG_SYS_I2C_FSL /* Use FSL common I2C driver */ 202 #define CONFIG_SYS_FSL_I2C_SPEED 400000 /* I2C spd and slave address */ 203 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 204 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 205 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x52 206 207 /* 208 * I2C2 EEPROM 209 */ 210 #define CONFIG_SYS_FSL_I2C2_SPEED 400000 /* I2C spd and slave address */ 211 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F 212 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100 213 214 #define CONFIG_SYS_I2C_PCA9555_ADDR 0x23 215 216 /* enable read and write access to EEPROM */ 217 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 218 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 219 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 220 221 /* 222 * eSPI - Enhanced SPI 223 */ 224 #define CONFIG_HARD_SPI 225 226 #if defined(CONFIG_PCI) 227 /* 228 * General PCI 229 * Memory space is mapped 1-1, but I/O space must start from 0. 230 */ 231 232 /* controller 2, direct to uli, tgtid 2, Base address 9000 */ 233 #define CONFIG_SYS_PCIE2_NAME "TWR-ELEV PCIe SLOT" 234 #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000 235 #define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000 236 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000 237 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */ 238 #define CONFIG_SYS_PCIE2_IO_VIRT 0xffc10000 239 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 240 #define CONFIG_SYS_PCIE2_IO_PHYS 0xffc10000 241 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ 242 243 /* controller 1, tgtid 1, Base address a000 */ 244 #define CONFIG_SYS_PCIE1_NAME "mini PCIe SLOT" 245 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 246 #define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000 247 #define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000 248 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ 249 #define CONFIG_SYS_PCIE1_IO_VIRT 0xffc00000 250 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 251 #define CONFIG_SYS_PCIE1_IO_PHYS 0xffc00000 252 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ 253 254 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 255 #endif /* CONFIG_PCI */ 256 257 #if defined(CONFIG_TSEC_ENET) 258 259 #define CONFIG_MII /* MII PHY management */ 260 #define CONFIG_TSEC1 261 #define CONFIG_TSEC1_NAME "eTSEC1" 262 #undef CONFIG_TSEC2 263 #undef CONFIG_TSEC2_NAME 264 #define CONFIG_TSEC3 265 #define CONFIG_TSEC3_NAME "eTSEC3" 266 267 #define TSEC1_PHY_ADDR 2 268 #define TSEC2_PHY_ADDR 0 269 #define TSEC3_PHY_ADDR 1 270 271 #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 272 #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 273 #define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 274 275 #define TSEC1_PHYIDX 0 276 #define TSEC2_PHYIDX 0 277 #define TSEC3_PHYIDX 0 278 279 #define CONFIG_ETHPRIME "eTSEC1" 280 281 #define CONFIG_HAS_ETH0 282 #define CONFIG_HAS_ETH1 283 #undef CONFIG_HAS_ETH2 284 #endif /* CONFIG_TSEC_ENET */ 285 286 #ifdef CONFIG_QE 287 /* QE microcode/firmware address */ 288 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR 289 #define CONFIG_SYS_QE_FW_ADDR 0xefec0000 290 #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 291 #endif /* CONFIG_QE */ 292 293 #ifdef CONFIG_TWR_P1025 294 /* 295 * QE UEC ethernet configuration 296 */ 297 #define CONFIG_MIIM_ADDRESS (CONFIG_SYS_CCSRBAR + 0x82120) 298 299 #undef CONFIG_UEC_ETH 300 #define CONFIG_PHY_MODE_NEED_CHANGE 301 302 #define CONFIG_UEC_ETH1 /* ETH1 */ 303 #define CONFIG_HAS_ETH0 304 305 #ifdef CONFIG_UEC_ETH1 306 #define CONFIG_SYS_UEC1_UCC_NUM 0 /* UCC1 */ 307 #define CONFIG_SYS_UEC1_RX_CLK QE_CLK12 /* CLK12 for MII */ 308 #define CONFIG_SYS_UEC1_TX_CLK QE_CLK9 /* CLK9 for MII */ 309 #define CONFIG_SYS_UEC1_ETH_TYPE FAST_ETH 310 #define CONFIG_SYS_UEC1_PHY_ADDR 0x18 /* 0x18 for MII */ 311 #define CONFIG_SYS_UEC1_INTERFACE_TYPE PHY_INTERFACE_MODE_MII 312 #define CONFIG_SYS_UEC1_INTERFACE_SPEED 100 313 #endif /* CONFIG_UEC_ETH1 */ 314 315 #define CONFIG_UEC_ETH5 /* ETH5 */ 316 #define CONFIG_HAS_ETH1 317 318 #ifdef CONFIG_UEC_ETH5 319 #define CONFIG_SYS_UEC5_UCC_NUM 4 /* UCC5 */ 320 #define CONFIG_SYS_UEC5_RX_CLK QE_CLK_NONE 321 #define CONFIG_SYS_UEC5_TX_CLK QE_CLK13 /* CLK 13 for RMII */ 322 #define CONFIG_SYS_UEC5_ETH_TYPE FAST_ETH 323 #define CONFIG_SYS_UEC5_PHY_ADDR 0x19 /* 0x19 for RMII */ 324 #define CONFIG_SYS_UEC5_INTERFACE_TYPE PHY_INTERFACE_MODE_RMII 325 #define CONFIG_SYS_UEC5_INTERFACE_SPEED 100 326 #endif /* CONFIG_UEC_ETH5 */ 327 #endif /* CONFIG_TWR-P1025 */ 328 329 /* 330 * Dynamic MTD Partition support with mtdparts 331 */ 332 #define CONFIG_FLASH_CFI_MTD 333 334 /* 335 * Environment 336 */ 337 #ifdef CONFIG_SYS_RAMBOOT 338 #ifdef CONFIG_RAMBOOT_SDCARD 339 #define CONFIG_ENV_SIZE 0x2000 340 #define CONFIG_SYS_MMC_ENV_DEV 0 341 #else 342 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) 343 #define CONFIG_ENV_SIZE 0x2000 344 #endif 345 #else 346 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) 347 #define CONFIG_ENV_SIZE 0x2000 348 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ 349 #endif 350 351 #define CONFIG_LOADS_ECHO /* echo on for serial download */ 352 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ 353 354 /* 355 * USB 356 */ 357 #define CONFIG_HAS_FSL_DR_USB 358 359 #if defined(CONFIG_HAS_FSL_DR_USB) 360 #ifdef CONFIG_USB_EHCI_HCD 361 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 362 #define CONFIG_USB_EHCI_FSL 363 #endif 364 #endif 365 366 #ifdef CONFIG_MMC 367 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR 368 #endif 369 370 #undef CONFIG_WATCHDOG /* watchdog disabled */ 371 372 /* 373 * Miscellaneous configurable options 374 */ 375 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 376 377 /* 378 * For booting Linux, the board info and command line data 379 * have to be in the first 64 MB of memory, since this is 380 * the maximum mapped by the Linux kernel during initialization. 381 */ 382 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory for Linux*/ 383 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 384 385 /* 386 * Environment Configuration 387 */ 388 #define CONFIG_HOSTNAME "unknown" 389 #define CONFIG_ROOTPATH "/opt/nfsroot" 390 #define CONFIG_BOOTFILE "uImage" 391 #define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */ 392 393 /* default location for tftp and bootm */ 394 #define CONFIG_LOADADDR 1000000 395 396 #define CONFIG_EXTRA_ENV_SETTINGS \ 397 "netdev=eth0\0" \ 398 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ 399 "loadaddr=1000000\0" \ 400 "bootfile=uImage\0" \ 401 "dtbfile=twr-p1025twr.dtb\0" \ 402 "ramdiskfile=rootfs.ext2.gz.uboot\0" \ 403 "qefirmwarefile=fsl_qe_ucode_1021_10_A.bin\0" \ 404 "tftpflash=tftpboot $loadaddr $uboot; " \ 405 "protect off " __stringify(CONFIG_SYS_TEXT_BASE) " +$filesize; " \ 406 "erase " __stringify(CONFIG_SYS_TEXT_BASE) " +$filesize; " \ 407 "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) " $filesize; " \ 408 "protect on " __stringify(CONFIG_SYS_TEXT_BASE) " +$filesize; " \ 409 "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) " $filesize\0" \ 410 "kernelflash=tftpboot $loadaddr $bootfile; " \ 411 "protect off 0xefa80000 +$filesize; " \ 412 "erase 0xefa80000 +$filesize; " \ 413 "cp.b $loadaddr 0xefa80000 $filesize; " \ 414 "protect on 0xefa80000 +$filesize; " \ 415 "cmp.b $loadaddr 0xefa80000 $filesize\0" \ 416 "dtbflash=tftpboot $loadaddr $dtbfile; " \ 417 "protect off 0xefe80000 +$filesize; " \ 418 "erase 0xefe80000 +$filesize; " \ 419 "cp.b $loadaddr 0xefe80000 $filesize; " \ 420 "protect on 0xefe80000 +$filesize; " \ 421 "cmp.b $loadaddr 0xefe80000 $filesize\0" \ 422 "ramdiskflash=tftpboot $loadaddr $ramdiskfile; " \ 423 "protect off 0xeeb80000 +$filesize; " \ 424 "erase 0xeeb80000 +$filesize; " \ 425 "cp.b $loadaddr 0xeeb80000 $filesize; " \ 426 "protect on 0xeeb80000 +$filesize; " \ 427 "cmp.b $loadaddr 0xeeb80000 $filesize\0" \ 428 "qefirmwareflash=tftpboot $loadaddr $qefirmwarefile; " \ 429 "protect off 0xefec0000 +$filesize; " \ 430 "erase 0xefec0000 +$filesize; " \ 431 "cp.b $loadaddr 0xefec0000 $filesize; " \ 432 "protect on 0xefec0000 +$filesize; " \ 433 "cmp.b $loadaddr 0xefec0000 $filesize\0" \ 434 "consoledev=ttyS0\0" \ 435 "ramdiskaddr=2000000\0" \ 436 "ramdiskfile=rootfs.ext2.gz.uboot\0" \ 437 "fdtaddr=1e00000\0" \ 438 "bdev=sda1\0" \ 439 "norbootaddr=ef080000\0" \ 440 "norfdtaddr=ef040000\0" \ 441 "ramdisk_size=120000\0" \ 442 "usbboot=setenv bootargs root=/dev/sda1 rw rootdelay=5 " \ 443 "console=$consoledev,$baudrate $othbootargs ; bootm 0xefa80000 - 0xefe80000" 444 445 #define CONFIG_NFSBOOTCOMMAND \ 446 "setenv bootargs root=/dev/nfs rw " \ 447 "nfsroot=$serverip:$rootpath " \ 448 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 449 "console=$consoledev,$baudrate $othbootargs;" \ 450 "tftp $loadaddr $bootfile&&" \ 451 "tftp $fdtaddr $fdtfile&&" \ 452 "bootm $loadaddr - $fdtaddr" 453 454 #define CONFIG_HDBOOT \ 455 "setenv bootargs root=/dev/$bdev rw rootdelay=30 " \ 456 "console=$consoledev,$baudrate $othbootargs;" \ 457 "usb start;" \ 458 "ext2load usb 0:1 $loadaddr /boot/$bootfile;" \ 459 "ext2load usb 0:1 $fdtaddr /boot/$fdtfile;" \ 460 "bootm $loadaddr - $fdtaddr" 461 462 #define CONFIG_USB_FAT_BOOT \ 463 "setenv bootargs root=/dev/ram rw " \ 464 "console=$consoledev,$baudrate $othbootargs " \ 465 "ramdisk_size=$ramdisk_size;" \ 466 "usb start;" \ 467 "fatload usb 0:2 $loadaddr $bootfile;" \ 468 "fatload usb 0:2 $fdtaddr $fdtfile;" \ 469 "fatload usb 0:2 $ramdiskaddr $ramdiskfile;" \ 470 "bootm $loadaddr $ramdiskaddr $fdtaddr" 471 472 #define CONFIG_USB_EXT2_BOOT \ 473 "setenv bootargs root=/dev/ram rw " \ 474 "console=$consoledev,$baudrate $othbootargs " \ 475 "ramdisk_size=$ramdisk_size;" \ 476 "usb start;" \ 477 "ext2load usb 0:4 $loadaddr $bootfile;" \ 478 "ext2load usb 0:4 $fdtaddr $fdtfile;" \ 479 "ext2load usb 0:4 $ramdiskaddr $ramdiskfile;" \ 480 "bootm $loadaddr $ramdiskaddr $fdtaddr" 481 482 #define CONFIG_NORBOOT \ 483 "setenv bootargs root=/dev/mtdblock3 rw " \ 484 "console=$consoledev,$baudrate rootfstype=jffs2 $othbootargs;" \ 485 "bootm $norbootaddr - $norfdtaddr" 486 487 #define CONFIG_RAMBOOTCOMMAND_TFTP \ 488 "setenv bootargs root=/dev/ram rw " \ 489 "console=$consoledev,$baudrate $othbootargs " \ 490 "ramdisk_size=$ramdisk_size;" \ 491 "tftp $ramdiskaddr $ramdiskfile;" \ 492 "tftp $loadaddr $bootfile;" \ 493 "tftp $fdtaddr $fdtfile;" \ 494 "bootm $loadaddr $ramdiskaddr $fdtaddr" 495 496 #define CONFIG_RAMBOOTCOMMAND \ 497 "setenv bootargs root=/dev/ram rw " \ 498 "console=$consoledev,$baudrate $othbootargs " \ 499 "ramdisk_size=$ramdisk_size;" \ 500 "bootm 0xefa80000 0xeeb80000 0xefe80000" 501 502 #define CONFIG_BOOTCOMMAND CONFIG_RAMBOOTCOMMAND 503 504 #endif /* __CONFIG_H */ 505