1 /* 2 * Copyright 2013 Freescale Semiconductor, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 /* 8 * QorIQ P1 Tower boards configuration file 9 */ 10 #ifndef __CONFIG_H 11 #define __CONFIG_H 12 13 #if defined(CONFIG_TWR_P1025) 14 #define CONFIG_BOARDNAME "TWR-P1025" 15 #define CONFIG_P1025 16 #define CONFIG_PHY_ATHEROS 17 #define CONFIG_QE 18 #define CONFIG_SYS_LBC_LBCR 0x00080000 /* Conversion of LBC addr */ 19 #define CONFIG_SYS_LBC_LCRR 0x80000002 /* LB clock ratio reg */ 20 #endif 21 22 #ifdef CONFIG_SDCARD 23 #define CONFIG_RAMBOOT_SDCARD 24 #define CONFIG_SYS_RAMBOOT 25 #define CONFIG_SYS_EXTRA_ENV_RELOC 26 #define CONFIG_SYS_TEXT_BASE 0x11000000 27 #define CONFIG_RESET_VECTOR_ADDRESS 0x110bfffc 28 #endif 29 30 #ifndef CONFIG_SYS_TEXT_BASE 31 #define CONFIG_SYS_TEXT_BASE 0xeff40000 32 #endif 33 34 #ifndef CONFIG_RESET_VECTOR_ADDRESS 35 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc 36 #endif 37 38 #ifndef CONFIG_SYS_MONITOR_BASE 39 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 40 #endif 41 42 /* High Level Configuration Options */ 43 #define CONFIG_BOOKE 44 #define CONFIG_E500 45 46 #define CONFIG_MP 47 48 #define CONFIG_FSL_ELBC 49 #define CONFIG_PCIE1 /* PCIE controller 1 (slot 1) */ 50 #define CONFIG_PCIE2 /* PCIE controller 2 (slot 2) */ 51 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ 52 #define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */ 53 #define CONFIG_FSL_PCIE_RESET /* need PCIe reset errata */ 54 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ 55 56 #define CONFIG_FSL_LAW 57 #define CONFIG_TSEC_ENET /* tsec ethernet support */ 58 #define CONFIG_ENV_OVERWRITE 59 60 #define CONFIG_CMD_SATA 61 #define CONFIG_SATA_SIL3114 62 #define CONFIG_SYS_SATA_MAX_DEVICE 2 63 #define CONFIG_LIBATA 64 #define CONFIG_LBA48 65 66 #ifndef __ASSEMBLY__ 67 extern unsigned long get_board_sys_clk(unsigned long dummy); 68 #endif 69 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk(0) /*sysclk for TWR-P1025 */ 70 71 #define CONFIG_DDR_CLK_FREQ 66666666 72 73 #define CONFIG_HWCONFIG 74 /* 75 * These can be toggled for performance analysis, otherwise use default. 76 */ 77 #define CONFIG_L2_CACHE 78 #define CONFIG_BTB 79 80 #define CONFIG_BOARD_EARLY_INIT_F /* Call board_pre_init */ 81 82 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ 83 #define CONFIG_SYS_MEMTEST_END 0x1fffffff 84 #define CONFIG_PANIC_HANG /* do not reset board on panic */ 85 86 #define CONFIG_SYS_CCSRBAR 0xffe00000 87 #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR 88 89 /* DDR Setup */ 90 #define CONFIG_SYS_FSL_DDR3 91 92 #define CONFIG_SYS_SDRAM_SIZE_LAW LAW_SIZE_512M 93 #define CONFIG_CHIP_SELECTS_PER_CTRL 1 94 95 #define CONFIG_SYS_SDRAM_SIZE (1u << (CONFIG_SYS_SDRAM_SIZE_LAW - 19)) 96 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 97 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 98 99 #define CONFIG_NUM_DDR_CONTROLLERS 1 100 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 101 102 /* Default settings for DDR3 */ 103 #define CONFIG_SYS_DDR_CS0_BNDS 0x0000001f 104 #define CONFIG_SYS_DDR_CS0_CONFIG 0x80014202 105 #define CONFIG_SYS_DDR_CS0_CONFIG_2 0x00000000 106 #define CONFIG_SYS_DDR_CS1_BNDS 0x00000000 107 #define CONFIG_SYS_DDR_CS1_CONFIG 0x00000000 108 #define CONFIG_SYS_DDR_CS1_CONFIG_2 0x00000000 109 110 #define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef 111 #define CONFIG_SYS_DDR_INIT_ADDR 0x00000000 112 #define CONFIG_SYS_DDR_INIT_EXT_ADDR 0x00000000 113 #define CONFIG_SYS_DDR_MODE_CONTROL 0x00000000 114 115 #define CONFIG_SYS_DDR_ZQ_CONTROL 0x89080600 116 #define CONFIG_SYS_DDR_WRLVL_CONTROL 0x8655a608 117 #define CONFIG_SYS_DDR_SR_CNTR 0x00000000 118 #define CONFIG_SYS_DDR_RCW_1 0x00000000 119 #define CONFIG_SYS_DDR_RCW_2 0x00000000 120 #define CONFIG_SYS_DDR_CONTROL 0xc70c0000 /* Type = DDR3 */ 121 #define CONFIG_SYS_DDR_CONTROL_2 0x04401050 122 #define CONFIG_SYS_DDR_TIMING_4 0x00220001 123 #define CONFIG_SYS_DDR_TIMING_5 0x03402400 124 125 #define CONFIG_SYS_DDR_TIMING_3 0x00020000 126 #define CONFIG_SYS_DDR_TIMING_0 0x00220004 127 #define CONFIG_SYS_DDR_TIMING_1 0x5c5b6544 128 #define CONFIG_SYS_DDR_TIMING_2 0x0fa880de 129 #define CONFIG_SYS_DDR_CLK_CTRL 0x03000000 130 #define CONFIG_SYS_DDR_MODE_1 0x80461320 131 #define CONFIG_SYS_DDR_MODE_2 0x00008000 132 #define CONFIG_SYS_DDR_INTERVAL 0x09480000 133 134 /* 135 * Memory map 136 * 137 * 0x0000_0000 0x1fff_ffff DDR Up to 512MB cacheable 138 * 0x8000_0000 0xdfff_ffff PCI Express Mem 1.5G non-cacheable(PCIe * 3) 139 * 0xffc0_0000 0xffc3_ffff PCI IO range 256k non-cacheable 140 * 141 * Localbus 142 * 0xe000_0000 0xe002_0000 SSD1289 128K non-cacheable 143 * 0xec00_0000 0xefff_ffff FLASH Up to 64M non-cacheable 144 * 145 * 0xff90_0000 0xff97_ffff L2 SRAM Up to 512K cacheable 146 * 0xffd0_0000 0xffd0_3fff init ram 16K Cacheable 147 * 0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable 148 */ 149 150 /* 151 * Local Bus Definitions 152 */ 153 #define CONFIG_SYS_MAX_FLASH_SECT 512 /* 64M */ 154 #define CONFIG_SYS_FLASH_BASE 0xec000000 155 156 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE 157 158 #define CONFIG_FLASH_BR_PRELIM (BR_PHYS_ADDR((CONFIG_SYS_FLASH_BASE_PHYS)) \ 159 | BR_PS_16 | BR_V) 160 161 #define CONFIG_FLASH_OR_PRELIM 0xfc0000b1 162 163 #define CONFIG_SYS_SSD_BASE 0xe0000000 164 #define CONFIG_SYS_SSD_BASE_PHYS CONFIG_SYS_SSD_BASE 165 #define CONFIG_SSD_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_SSD_BASE_PHYS) | \ 166 BR_PS_16 | BR_V) 167 #define CONFIG_SSD_OR_PRELIM (OR_AM_64KB | OR_GPCM_CSNT | OR_GPCM_XACS | \ 168 OR_GPCM_ACS_DIV2 | OR_GPCM_SCY | \ 169 OR_GPCM_TRLX | OR_GPCM_EHTR | OR_GPCM_EAD) 170 171 #define CONFIG_SYS_BR2_PRELIM CONFIG_SSD_BR_PRELIM 172 #define CONFIG_SYS_OR2_PRELIM CONFIG_SSD_OR_PRELIM 173 174 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS} 175 #define CONFIG_SYS_FLASH_QUIET_TEST 176 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 177 178 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ 179 180 #undef CONFIG_SYS_FLASH_CHECKSUM 181 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 182 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 183 184 #define CONFIG_FLASH_CFI_DRIVER 185 #define CONFIG_SYS_FLASH_CFI 186 #define CONFIG_SYS_FLASH_EMPTY_INFO 187 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 188 189 #define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */ 190 191 #define CONFIG_SYS_INIT_RAM_LOCK 192 #define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 193 /* Initial L1 address */ 194 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS CONFIG_SYS_INIT_RAM_ADDR 195 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0 196 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS 197 /* Size of used area in RAM */ 198 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 199 200 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ 201 GENERATED_GBL_DATA_SIZE) 202 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 203 204 #define CONFIG_SYS_MONITOR_LEN (768 * 1024) 205 #define CONFIG_SYS_MALLOC_LEN (1024 * 1024)/* Reserved for malloc */ 206 207 #define CONFIG_SYS_BR0_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */ 208 #define CONFIG_SYS_OR0_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */ 209 210 /* Serial Port 211 * open - index 2 212 * shorted - index 1 213 */ 214 #define CONFIG_CONS_INDEX 1 215 #undef CONFIG_SERIAL_SOFTWARE_FIFO 216 #define CONFIG_SYS_NS16550_SERIAL 217 #define CONFIG_SYS_NS16550_REG_SIZE 1 218 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) 219 220 #define CONFIG_SYS_BAUDRATE_TABLE \ 221 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} 222 223 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) 224 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) 225 226 /* I2C */ 227 #define CONFIG_SYS_I2C 228 #define CONFIG_SYS_I2C_FSL /* Use FSL common I2C driver */ 229 #define CONFIG_SYS_FSL_I2C_SPEED 400000 /* I2C spd and slave address */ 230 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 231 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 232 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x52 233 234 /* 235 * I2C2 EEPROM 236 */ 237 #define CONFIG_SYS_FSL_I2C2_SPEED 400000 /* I2C spd and slave address */ 238 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F 239 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100 240 241 #define CONFIG_SYS_I2C_PCA9555_ADDR 0x23 242 243 /* enable read and write access to EEPROM */ 244 #define CONFIG_CMD_EEPROM 245 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 246 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 247 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 248 249 /* 250 * eSPI - Enhanced SPI 251 */ 252 #define CONFIG_HARD_SPI 253 254 #if defined(CONFIG_PCI) 255 /* 256 * General PCI 257 * Memory space is mapped 1-1, but I/O space must start from 0. 258 */ 259 260 /* controller 2, direct to uli, tgtid 2, Base address 9000 */ 261 #define CONFIG_SYS_PCIE2_NAME "TWR-ELEV PCIe SLOT" 262 #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000 263 #define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000 264 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000 265 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */ 266 #define CONFIG_SYS_PCIE2_IO_VIRT 0xffc10000 267 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 268 #define CONFIG_SYS_PCIE2_IO_PHYS 0xffc10000 269 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ 270 271 /* controller 1, tgtid 1, Base address a000 */ 272 #define CONFIG_SYS_PCIE1_NAME "mini PCIe SLOT" 273 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 274 #define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000 275 #define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000 276 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ 277 #define CONFIG_SYS_PCIE1_IO_VIRT 0xffc00000 278 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 279 #define CONFIG_SYS_PCIE1_IO_PHYS 0xffc00000 280 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ 281 282 #define CONFIG_CMD_PCI 283 284 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 285 #define CONFIG_DOS_PARTITION 286 #endif /* CONFIG_PCI */ 287 288 #if defined(CONFIG_TSEC_ENET) 289 290 #define CONFIG_MII /* MII PHY management */ 291 #define CONFIG_TSEC1 292 #define CONFIG_TSEC1_NAME "eTSEC1" 293 #undef CONFIG_TSEC2 294 #undef CONFIG_TSEC2_NAME 295 #define CONFIG_TSEC3 296 #define CONFIG_TSEC3_NAME "eTSEC3" 297 298 #define TSEC1_PHY_ADDR 2 299 #define TSEC2_PHY_ADDR 0 300 #define TSEC3_PHY_ADDR 1 301 302 #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 303 #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 304 #define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 305 306 #define TSEC1_PHYIDX 0 307 #define TSEC2_PHYIDX 0 308 #define TSEC3_PHYIDX 0 309 310 #define CONFIG_ETHPRIME "eTSEC1" 311 312 #define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */ 313 314 #define CONFIG_HAS_ETH0 315 #define CONFIG_HAS_ETH1 316 #undef CONFIG_HAS_ETH2 317 #endif /* CONFIG_TSEC_ENET */ 318 319 #ifdef CONFIG_QE 320 /* QE microcode/firmware address */ 321 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR 322 #define CONFIG_SYS_QE_FW_ADDR 0xefec0000 323 #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 324 #endif /* CONFIG_QE */ 325 326 #ifdef CONFIG_TWR_P1025 327 /* 328 * QE UEC ethernet configuration 329 */ 330 #define CONFIG_MIIM_ADDRESS (CONFIG_SYS_CCSRBAR + 0x82120) 331 332 #undef CONFIG_UEC_ETH 333 #define CONFIG_PHY_MODE_NEED_CHANGE 334 335 #define CONFIG_UEC_ETH1 /* ETH1 */ 336 #define CONFIG_HAS_ETH0 337 338 #ifdef CONFIG_UEC_ETH1 339 #define CONFIG_SYS_UEC1_UCC_NUM 0 /* UCC1 */ 340 #define CONFIG_SYS_UEC1_RX_CLK QE_CLK12 /* CLK12 for MII */ 341 #define CONFIG_SYS_UEC1_TX_CLK QE_CLK9 /* CLK9 for MII */ 342 #define CONFIG_SYS_UEC1_ETH_TYPE FAST_ETH 343 #define CONFIG_SYS_UEC1_PHY_ADDR 0x18 /* 0x18 for MII */ 344 #define CONFIG_SYS_UEC1_INTERFACE_TYPE PHY_INTERFACE_MODE_MII 345 #define CONFIG_SYS_UEC1_INTERFACE_SPEED 100 346 #endif /* CONFIG_UEC_ETH1 */ 347 348 #define CONFIG_UEC_ETH5 /* ETH5 */ 349 #define CONFIG_HAS_ETH1 350 351 #ifdef CONFIG_UEC_ETH5 352 #define CONFIG_SYS_UEC5_UCC_NUM 4 /* UCC5 */ 353 #define CONFIG_SYS_UEC5_RX_CLK QE_CLK_NONE 354 #define CONFIG_SYS_UEC5_TX_CLK QE_CLK13 /* CLK 13 for RMII */ 355 #define CONFIG_SYS_UEC5_ETH_TYPE FAST_ETH 356 #define CONFIG_SYS_UEC5_PHY_ADDR 0x19 /* 0x19 for RMII */ 357 #define CONFIG_SYS_UEC5_INTERFACE_TYPE PHY_INTERFACE_MODE_RMII 358 #define CONFIG_SYS_UEC5_INTERFACE_SPEED 100 359 #endif /* CONFIG_UEC_ETH5 */ 360 #endif /* CONFIG_TWR-P1025 */ 361 362 /* 363 * Dynamic MTD Partition support with mtdparts 364 */ 365 #define CONFIG_MTD_DEVICE 366 #define CONFIG_MTD_PARTITIONS 367 #define CONFIG_CMD_MTDPARTS 368 #define CONFIG_FLASH_CFI_MTD 369 #define MTDIDS_DEFAULT "nor0=ec000000.nor" 370 #define MTDPARTS_DEFAULT "mtdparts=ec000000.nor:256k(vsc7385-firmware)," \ 371 "256k(dtb),5632k(kernel),57856k(fs)," \ 372 "256k(qe-ucode-firmware),1280k(u-boot)" 373 374 /* 375 * Environment 376 */ 377 #ifdef CONFIG_SYS_RAMBOOT 378 #ifdef CONFIG_RAMBOOT_SDCARD 379 #define CONFIG_ENV_IS_IN_MMC 380 #define CONFIG_ENV_SIZE 0x2000 381 #define CONFIG_SYS_MMC_ENV_DEV 0 382 #else 383 #define CONFIG_ENV_IS_NOWHERE /* Store ENV in memory only */ 384 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) 385 #define CONFIG_ENV_SIZE 0x2000 386 #endif 387 #else 388 #define CONFIG_ENV_IS_IN_FLASH 389 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) 390 #define CONFIG_ENV_SIZE 0x2000 391 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ 392 #endif 393 394 #define CONFIG_LOADS_ECHO /* echo on for serial download */ 395 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ 396 397 /* 398 * Command line configuration. 399 */ 400 #define CONFIG_CMD_IRQ 401 #define CONFIG_CMD_REGINFO 402 403 /* 404 * USB 405 */ 406 #define CONFIG_HAS_FSL_DR_USB 407 408 #if defined(CONFIG_HAS_FSL_DR_USB) 409 #define CONFIG_USB_EHCI 410 411 #ifdef CONFIG_USB_EHCI 412 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 413 #define CONFIG_USB_EHCI_FSL 414 #endif 415 #endif 416 417 #define CONFIG_MMC 418 419 #ifdef CONFIG_MMC 420 #define CONFIG_FSL_ESDHC 421 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR 422 #define CONFIG_GENERIC_MMC 423 #endif 424 425 #if defined(CONFIG_MMC) || defined(CONFIG_USB_EHCI) \ 426 || defined(CONFIG_FSL_SATA) 427 #define CONFIG_DOS_PARTITION 428 #endif 429 430 #undef CONFIG_WATCHDOG /* watchdog disabled */ 431 432 /* 433 * Miscellaneous configurable options 434 */ 435 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 436 #define CONFIG_CMDLINE_EDITING /* Command-line editing */ 437 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 438 #if defined(CONFIG_CMD_KGDB) 439 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 440 #else 441 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 442 #endif 443 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) 444 /* Print Buffer Size */ 445 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 446 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */ 447 448 /* 449 * For booting Linux, the board info and command line data 450 * have to be in the first 64 MB of memory, since this is 451 * the maximum mapped by the Linux kernel during initialization. 452 */ 453 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory for Linux*/ 454 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 455 456 /* 457 * Environment Configuration 458 */ 459 #define CONFIG_HOSTNAME unknown 460 #define CONFIG_ROOTPATH "/opt/nfsroot" 461 #define CONFIG_BOOTFILE "uImage" 462 #define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */ 463 464 /* default location for tftp and bootm */ 465 #define CONFIG_LOADADDR 1000000 466 467 #define CONFIG_BOOTARGS /* the boot command will set bootargs */ 468 469 #define CONFIG_BAUDRATE 115200 470 471 #define CONFIG_EXTRA_ENV_SETTINGS \ 472 "netdev=eth0\0" \ 473 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ 474 "loadaddr=1000000\0" \ 475 "bootfile=uImage\0" \ 476 "dtbfile=twr-p1025twr.dtb\0" \ 477 "ramdiskfile=rootfs.ext2.gz.uboot\0" \ 478 "qefirmwarefile=fsl_qe_ucode_1021_10_A.bin\0" \ 479 "tftpflash=tftpboot $loadaddr $uboot; " \ 480 "protect off " __stringify(CONFIG_SYS_TEXT_BASE) " +$filesize; " \ 481 "erase " __stringify(CONFIG_SYS_TEXT_BASE) " +$filesize; " \ 482 "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) " $filesize; " \ 483 "protect on " __stringify(CONFIG_SYS_TEXT_BASE) " +$filesize; " \ 484 "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) " $filesize\0" \ 485 "kernelflash=tftpboot $loadaddr $bootfile; " \ 486 "protect off 0xefa80000 +$filesize; " \ 487 "erase 0xefa80000 +$filesize; " \ 488 "cp.b $loadaddr 0xefa80000 $filesize; " \ 489 "protect on 0xefa80000 +$filesize; " \ 490 "cmp.b $loadaddr 0xefa80000 $filesize\0" \ 491 "dtbflash=tftpboot $loadaddr $dtbfile; " \ 492 "protect off 0xefe80000 +$filesize; " \ 493 "erase 0xefe80000 +$filesize; " \ 494 "cp.b $loadaddr 0xefe80000 $filesize; " \ 495 "protect on 0xefe80000 +$filesize; " \ 496 "cmp.b $loadaddr 0xefe80000 $filesize\0" \ 497 "ramdiskflash=tftpboot $loadaddr $ramdiskfile; " \ 498 "protect off 0xeeb80000 +$filesize; " \ 499 "erase 0xeeb80000 +$filesize; " \ 500 "cp.b $loadaddr 0xeeb80000 $filesize; " \ 501 "protect on 0xeeb80000 +$filesize; " \ 502 "cmp.b $loadaddr 0xeeb80000 $filesize\0" \ 503 "qefirmwareflash=tftpboot $loadaddr $qefirmwarefile; " \ 504 "protect off 0xefec0000 +$filesize; " \ 505 "erase 0xefec0000 +$filesize; " \ 506 "cp.b $loadaddr 0xefec0000 $filesize; " \ 507 "protect on 0xefec0000 +$filesize; " \ 508 "cmp.b $loadaddr 0xefec0000 $filesize\0" \ 509 "consoledev=ttyS0\0" \ 510 "ramdiskaddr=2000000\0" \ 511 "ramdiskfile=rootfs.ext2.gz.uboot\0" \ 512 "fdtaddr=1e00000\0" \ 513 "bdev=sda1\0" \ 514 "norbootaddr=ef080000\0" \ 515 "norfdtaddr=ef040000\0" \ 516 "ramdisk_size=120000\0" \ 517 "usbboot=setenv bootargs root=/dev/sda1 rw rootdelay=5 " \ 518 "console=$consoledev,$baudrate $othbootargs ; bootm 0xefa80000 - 0xefe80000" 519 520 #define CONFIG_NFSBOOTCOMMAND \ 521 "setenv bootargs root=/dev/nfs rw " \ 522 "nfsroot=$serverip:$rootpath " \ 523 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 524 "console=$consoledev,$baudrate $othbootargs;" \ 525 "tftp $loadaddr $bootfile&&" \ 526 "tftp $fdtaddr $fdtfile&&" \ 527 "bootm $loadaddr - $fdtaddr" 528 529 #define CONFIG_HDBOOT \ 530 "setenv bootargs root=/dev/$bdev rw rootdelay=30 " \ 531 "console=$consoledev,$baudrate $othbootargs;" \ 532 "usb start;" \ 533 "ext2load usb 0:1 $loadaddr /boot/$bootfile;" \ 534 "ext2load usb 0:1 $fdtaddr /boot/$fdtfile;" \ 535 "bootm $loadaddr - $fdtaddr" 536 537 #define CONFIG_USB_FAT_BOOT \ 538 "setenv bootargs root=/dev/ram rw " \ 539 "console=$consoledev,$baudrate $othbootargs " \ 540 "ramdisk_size=$ramdisk_size;" \ 541 "usb start;" \ 542 "fatload usb 0:2 $loadaddr $bootfile;" \ 543 "fatload usb 0:2 $fdtaddr $fdtfile;" \ 544 "fatload usb 0:2 $ramdiskaddr $ramdiskfile;" \ 545 "bootm $loadaddr $ramdiskaddr $fdtaddr" 546 547 #define CONFIG_USB_EXT2_BOOT \ 548 "setenv bootargs root=/dev/ram rw " \ 549 "console=$consoledev,$baudrate $othbootargs " \ 550 "ramdisk_size=$ramdisk_size;" \ 551 "usb start;" \ 552 "ext2load usb 0:4 $loadaddr $bootfile;" \ 553 "ext2load usb 0:4 $fdtaddr $fdtfile;" \ 554 "ext2load usb 0:4 $ramdiskaddr $ramdiskfile;" \ 555 "bootm $loadaddr $ramdiskaddr $fdtaddr" 556 557 #define CONFIG_NORBOOT \ 558 "setenv bootargs root=/dev/mtdblock3 rw " \ 559 "console=$consoledev,$baudrate rootfstype=jffs2 $othbootargs;" \ 560 "bootm $norbootaddr - $norfdtaddr" 561 562 #define CONFIG_RAMBOOTCOMMAND_TFTP \ 563 "setenv bootargs root=/dev/ram rw " \ 564 "console=$consoledev,$baudrate $othbootargs " \ 565 "ramdisk_size=$ramdisk_size;" \ 566 "tftp $ramdiskaddr $ramdiskfile;" \ 567 "tftp $loadaddr $bootfile;" \ 568 "tftp $fdtaddr $fdtfile;" \ 569 "bootm $loadaddr $ramdiskaddr $fdtaddr" 570 571 #define CONFIG_RAMBOOTCOMMAND \ 572 "setenv bootargs root=/dev/ram rw " \ 573 "console=$consoledev,$baudrate $othbootargs " \ 574 "ramdisk_size=$ramdisk_size;" \ 575 "bootm 0xefa80000 0xeeb80000 0xefe80000" 576 577 #define CONFIG_BOOTCOMMAND CONFIG_RAMBOOTCOMMAND 578 579 #endif /* __CONFIG_H */ 580