1 /* 2 * Copyright 2013 Freescale Semiconductor, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 /* 8 * QorIQ P1 Tower boards configuration file 9 */ 10 #ifndef __CONFIG_H 11 #define __CONFIG_H 12 13 #if defined(CONFIG_TWR_P1025) 14 #define CONFIG_BOARDNAME "TWR-P1025" 15 #define CONFIG_PHY_ATHEROS 16 #define CONFIG_QE 17 #define CONFIG_SYS_LBC_LBCR 0x00080000 /* Conversion of LBC addr */ 18 #define CONFIG_SYS_LBC_LCRR 0x80000002 /* LB clock ratio reg */ 19 #endif 20 21 #ifdef CONFIG_SDCARD 22 #define CONFIG_RAMBOOT_SDCARD 23 #define CONFIG_SYS_RAMBOOT 24 #define CONFIG_SYS_EXTRA_ENV_RELOC 25 #define CONFIG_RESET_VECTOR_ADDRESS 0x110bfffc 26 #endif 27 28 #ifndef CONFIG_RESET_VECTOR_ADDRESS 29 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc 30 #endif 31 32 #ifndef CONFIG_SYS_MONITOR_BASE 33 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 34 #endif 35 36 #define CONFIG_MP 37 38 #define CONFIG_PCIE1 /* PCIE controller 1 (slot 1) */ 39 #define CONFIG_PCIE2 /* PCIE controller 2 (slot 2) */ 40 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ 41 #define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */ 42 #define CONFIG_FSL_PCIE_RESET /* need PCIe reset errata */ 43 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ 44 45 #define CONFIG_TSEC_ENET /* tsec ethernet support */ 46 #define CONFIG_ENV_OVERWRITE 47 48 #define CONFIG_SYS_SATA_MAX_DEVICE 2 49 #define CONFIG_LBA48 50 51 #ifndef __ASSEMBLY__ 52 extern unsigned long get_board_sys_clk(unsigned long dummy); 53 #endif 54 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk(0) /*sysclk for TWR-P1025 */ 55 56 #define CONFIG_DDR_CLK_FREQ 66666666 57 58 #define CONFIG_HWCONFIG 59 /* 60 * These can be toggled for performance analysis, otherwise use default. 61 */ 62 #define CONFIG_L2_CACHE 63 #define CONFIG_BTB 64 65 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ 66 #define CONFIG_SYS_MEMTEST_END 0x1fffffff 67 68 #define CONFIG_SYS_CCSRBAR 0xffe00000 69 #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR 70 71 /* DDR Setup */ 72 73 #define CONFIG_SYS_SDRAM_SIZE_LAW LAW_SIZE_512M 74 #define CONFIG_CHIP_SELECTS_PER_CTRL 1 75 76 #define CONFIG_SYS_SDRAM_SIZE (1u << (CONFIG_SYS_SDRAM_SIZE_LAW - 19)) 77 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 78 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 79 80 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 81 82 /* Default settings for DDR3 */ 83 #define CONFIG_SYS_DDR_CS0_BNDS 0x0000001f 84 #define CONFIG_SYS_DDR_CS0_CONFIG 0x80014202 85 #define CONFIG_SYS_DDR_CS0_CONFIG_2 0x00000000 86 #define CONFIG_SYS_DDR_CS1_BNDS 0x00000000 87 #define CONFIG_SYS_DDR_CS1_CONFIG 0x00000000 88 #define CONFIG_SYS_DDR_CS1_CONFIG_2 0x00000000 89 90 #define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef 91 #define CONFIG_SYS_DDR_INIT_ADDR 0x00000000 92 #define CONFIG_SYS_DDR_INIT_EXT_ADDR 0x00000000 93 #define CONFIG_SYS_DDR_MODE_CONTROL 0x00000000 94 95 #define CONFIG_SYS_DDR_ZQ_CONTROL 0x89080600 96 #define CONFIG_SYS_DDR_WRLVL_CONTROL 0x8655a608 97 #define CONFIG_SYS_DDR_SR_CNTR 0x00000000 98 #define CONFIG_SYS_DDR_RCW_1 0x00000000 99 #define CONFIG_SYS_DDR_RCW_2 0x00000000 100 #define CONFIG_SYS_DDR_CONTROL 0xc70c0000 /* Type = DDR3 */ 101 #define CONFIG_SYS_DDR_CONTROL_2 0x04401050 102 #define CONFIG_SYS_DDR_TIMING_4 0x00220001 103 #define CONFIG_SYS_DDR_TIMING_5 0x03402400 104 105 #define CONFIG_SYS_DDR_TIMING_3 0x00020000 106 #define CONFIG_SYS_DDR_TIMING_0 0x00220004 107 #define CONFIG_SYS_DDR_TIMING_1 0x5c5b6544 108 #define CONFIG_SYS_DDR_TIMING_2 0x0fa880de 109 #define CONFIG_SYS_DDR_CLK_CTRL 0x03000000 110 #define CONFIG_SYS_DDR_MODE_1 0x80461320 111 #define CONFIG_SYS_DDR_MODE_2 0x00008000 112 #define CONFIG_SYS_DDR_INTERVAL 0x09480000 113 114 /* 115 * Memory map 116 * 117 * 0x0000_0000 0x1fff_ffff DDR Up to 512MB cacheable 118 * 0x8000_0000 0xdfff_ffff PCI Express Mem 1.5G non-cacheable(PCIe * 3) 119 * 0xffc0_0000 0xffc3_ffff PCI IO range 256k non-cacheable 120 * 121 * Localbus 122 * 0xe000_0000 0xe002_0000 SSD1289 128K non-cacheable 123 * 0xec00_0000 0xefff_ffff FLASH Up to 64M non-cacheable 124 * 125 * 0xff90_0000 0xff97_ffff L2 SRAM Up to 512K cacheable 126 * 0xffd0_0000 0xffd0_3fff init ram 16K Cacheable 127 * 0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable 128 */ 129 130 /* 131 * Local Bus Definitions 132 */ 133 #define CONFIG_SYS_MAX_FLASH_SECT 512 /* 64M */ 134 #define CONFIG_SYS_FLASH_BASE 0xec000000 135 136 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE 137 138 #define CONFIG_FLASH_BR_PRELIM (BR_PHYS_ADDR((CONFIG_SYS_FLASH_BASE_PHYS)) \ 139 | BR_PS_16 | BR_V) 140 141 #define CONFIG_FLASH_OR_PRELIM 0xfc0000b1 142 143 #define CONFIG_SYS_SSD_BASE 0xe0000000 144 #define CONFIG_SYS_SSD_BASE_PHYS CONFIG_SYS_SSD_BASE 145 #define CONFIG_SSD_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_SSD_BASE_PHYS) | \ 146 BR_PS_16 | BR_V) 147 #define CONFIG_SSD_OR_PRELIM (OR_AM_64KB | OR_GPCM_CSNT | OR_GPCM_XACS | \ 148 OR_GPCM_ACS_DIV2 | OR_GPCM_SCY | \ 149 OR_GPCM_TRLX | OR_GPCM_EHTR | OR_GPCM_EAD) 150 151 #define CONFIG_SYS_BR2_PRELIM CONFIG_SSD_BR_PRELIM 152 #define CONFIG_SYS_OR2_PRELIM CONFIG_SSD_OR_PRELIM 153 154 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS} 155 #define CONFIG_SYS_FLASH_QUIET_TEST 156 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 157 158 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ 159 160 #undef CONFIG_SYS_FLASH_CHECKSUM 161 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 162 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 163 164 #define CONFIG_FLASH_CFI_DRIVER 165 #define CONFIG_SYS_FLASH_CFI 166 #define CONFIG_SYS_FLASH_EMPTY_INFO 167 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 168 169 #define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */ 170 171 #define CONFIG_SYS_INIT_RAM_LOCK 172 #define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 173 /* Initial L1 address */ 174 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS CONFIG_SYS_INIT_RAM_ADDR 175 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0 176 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS 177 /* Size of used area in RAM */ 178 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 179 180 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ 181 GENERATED_GBL_DATA_SIZE) 182 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 183 184 #define CONFIG_SYS_MONITOR_LEN (768 * 1024) 185 #define CONFIG_SYS_MALLOC_LEN (1024 * 1024)/* Reserved for malloc */ 186 187 #define CONFIG_SYS_BR0_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */ 188 #define CONFIG_SYS_OR0_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */ 189 190 /* Serial Port 191 * open - index 2 192 * shorted - index 1 193 */ 194 #undef CONFIG_SERIAL_SOFTWARE_FIFO 195 #define CONFIG_SYS_NS16550_SERIAL 196 #define CONFIG_SYS_NS16550_REG_SIZE 1 197 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) 198 199 #define CONFIG_SYS_BAUDRATE_TABLE \ 200 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} 201 202 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) 203 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) 204 205 /* I2C */ 206 #define CONFIG_SYS_I2C 207 #define CONFIG_SYS_I2C_FSL /* Use FSL common I2C driver */ 208 #define CONFIG_SYS_FSL_I2C_SPEED 400000 /* I2C spd and slave address */ 209 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 210 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 211 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x52 212 213 /* 214 * I2C2 EEPROM 215 */ 216 #define CONFIG_SYS_FSL_I2C2_SPEED 400000 /* I2C spd and slave address */ 217 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F 218 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100 219 220 #define CONFIG_SYS_I2C_PCA9555_ADDR 0x23 221 222 /* enable read and write access to EEPROM */ 223 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 224 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 225 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 226 227 /* 228 * eSPI - Enhanced SPI 229 */ 230 #define CONFIG_HARD_SPI 231 232 #if defined(CONFIG_PCI) 233 /* 234 * General PCI 235 * Memory space is mapped 1-1, but I/O space must start from 0. 236 */ 237 238 /* controller 2, direct to uli, tgtid 2, Base address 9000 */ 239 #define CONFIG_SYS_PCIE2_NAME "TWR-ELEV PCIe SLOT" 240 #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000 241 #define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000 242 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000 243 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */ 244 #define CONFIG_SYS_PCIE2_IO_VIRT 0xffc10000 245 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 246 #define CONFIG_SYS_PCIE2_IO_PHYS 0xffc10000 247 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ 248 249 /* controller 1, tgtid 1, Base address a000 */ 250 #define CONFIG_SYS_PCIE1_NAME "mini PCIe SLOT" 251 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 252 #define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000 253 #define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000 254 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ 255 #define CONFIG_SYS_PCIE1_IO_VIRT 0xffc00000 256 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 257 #define CONFIG_SYS_PCIE1_IO_PHYS 0xffc00000 258 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ 259 260 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 261 #endif /* CONFIG_PCI */ 262 263 #if defined(CONFIG_TSEC_ENET) 264 265 #define CONFIG_MII /* MII PHY management */ 266 #define CONFIG_TSEC1 267 #define CONFIG_TSEC1_NAME "eTSEC1" 268 #undef CONFIG_TSEC2 269 #undef CONFIG_TSEC2_NAME 270 #define CONFIG_TSEC3 271 #define CONFIG_TSEC3_NAME "eTSEC3" 272 273 #define TSEC1_PHY_ADDR 2 274 #define TSEC2_PHY_ADDR 0 275 #define TSEC3_PHY_ADDR 1 276 277 #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 278 #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 279 #define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 280 281 #define TSEC1_PHYIDX 0 282 #define TSEC2_PHYIDX 0 283 #define TSEC3_PHYIDX 0 284 285 #define CONFIG_ETHPRIME "eTSEC1" 286 287 #define CONFIG_HAS_ETH0 288 #define CONFIG_HAS_ETH1 289 #undef CONFIG_HAS_ETH2 290 #endif /* CONFIG_TSEC_ENET */ 291 292 #ifdef CONFIG_QE 293 /* QE microcode/firmware address */ 294 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR 295 #define CONFIG_SYS_QE_FW_ADDR 0xefec0000 296 #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 297 #endif /* CONFIG_QE */ 298 299 #ifdef CONFIG_TWR_P1025 300 /* 301 * QE UEC ethernet configuration 302 */ 303 #define CONFIG_MIIM_ADDRESS (CONFIG_SYS_CCSRBAR + 0x82120) 304 305 #undef CONFIG_UEC_ETH 306 #define CONFIG_PHY_MODE_NEED_CHANGE 307 308 #define CONFIG_UEC_ETH1 /* ETH1 */ 309 #define CONFIG_HAS_ETH0 310 311 #ifdef CONFIG_UEC_ETH1 312 #define CONFIG_SYS_UEC1_UCC_NUM 0 /* UCC1 */ 313 #define CONFIG_SYS_UEC1_RX_CLK QE_CLK12 /* CLK12 for MII */ 314 #define CONFIG_SYS_UEC1_TX_CLK QE_CLK9 /* CLK9 for MII */ 315 #define CONFIG_SYS_UEC1_ETH_TYPE FAST_ETH 316 #define CONFIG_SYS_UEC1_PHY_ADDR 0x18 /* 0x18 for MII */ 317 #define CONFIG_SYS_UEC1_INTERFACE_TYPE PHY_INTERFACE_MODE_MII 318 #define CONFIG_SYS_UEC1_INTERFACE_SPEED 100 319 #endif /* CONFIG_UEC_ETH1 */ 320 321 #define CONFIG_UEC_ETH5 /* ETH5 */ 322 #define CONFIG_HAS_ETH1 323 324 #ifdef CONFIG_UEC_ETH5 325 #define CONFIG_SYS_UEC5_UCC_NUM 4 /* UCC5 */ 326 #define CONFIG_SYS_UEC5_RX_CLK QE_CLK_NONE 327 #define CONFIG_SYS_UEC5_TX_CLK QE_CLK13 /* CLK 13 for RMII */ 328 #define CONFIG_SYS_UEC5_ETH_TYPE FAST_ETH 329 #define CONFIG_SYS_UEC5_PHY_ADDR 0x19 /* 0x19 for RMII */ 330 #define CONFIG_SYS_UEC5_INTERFACE_TYPE PHY_INTERFACE_MODE_RMII 331 #define CONFIG_SYS_UEC5_INTERFACE_SPEED 100 332 #endif /* CONFIG_UEC_ETH5 */ 333 #endif /* CONFIG_TWR-P1025 */ 334 335 /* 336 * Dynamic MTD Partition support with mtdparts 337 */ 338 #define CONFIG_MTD_DEVICE 339 #define CONFIG_MTD_PARTITIONS 340 #define CONFIG_FLASH_CFI_MTD 341 342 /* 343 * Environment 344 */ 345 #ifdef CONFIG_SYS_RAMBOOT 346 #ifdef CONFIG_RAMBOOT_SDCARD 347 #define CONFIG_ENV_SIZE 0x2000 348 #define CONFIG_SYS_MMC_ENV_DEV 0 349 #else 350 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) 351 #define CONFIG_ENV_SIZE 0x2000 352 #endif 353 #else 354 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) 355 #define CONFIG_ENV_SIZE 0x2000 356 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ 357 #endif 358 359 #define CONFIG_LOADS_ECHO /* echo on for serial download */ 360 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ 361 362 /* 363 * USB 364 */ 365 #define CONFIG_HAS_FSL_DR_USB 366 367 #if defined(CONFIG_HAS_FSL_DR_USB) 368 #ifdef CONFIG_USB_EHCI_HCD 369 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 370 #define CONFIG_USB_EHCI_FSL 371 #endif 372 #endif 373 374 #ifdef CONFIG_MMC 375 #define CONFIG_FSL_ESDHC 376 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR 377 #endif 378 379 #undef CONFIG_WATCHDOG /* watchdog disabled */ 380 381 /* 382 * Miscellaneous configurable options 383 */ 384 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 385 386 /* 387 * For booting Linux, the board info and command line data 388 * have to be in the first 64 MB of memory, since this is 389 * the maximum mapped by the Linux kernel during initialization. 390 */ 391 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory for Linux*/ 392 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 393 394 /* 395 * Environment Configuration 396 */ 397 #define CONFIG_HOSTNAME unknown 398 #define CONFIG_ROOTPATH "/opt/nfsroot" 399 #define CONFIG_BOOTFILE "uImage" 400 #define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */ 401 402 /* default location for tftp and bootm */ 403 #define CONFIG_LOADADDR 1000000 404 405 #define CONFIG_EXTRA_ENV_SETTINGS \ 406 "netdev=eth0\0" \ 407 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ 408 "loadaddr=1000000\0" \ 409 "bootfile=uImage\0" \ 410 "dtbfile=twr-p1025twr.dtb\0" \ 411 "ramdiskfile=rootfs.ext2.gz.uboot\0" \ 412 "qefirmwarefile=fsl_qe_ucode_1021_10_A.bin\0" \ 413 "tftpflash=tftpboot $loadaddr $uboot; " \ 414 "protect off " __stringify(CONFIG_SYS_TEXT_BASE) " +$filesize; " \ 415 "erase " __stringify(CONFIG_SYS_TEXT_BASE) " +$filesize; " \ 416 "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) " $filesize; " \ 417 "protect on " __stringify(CONFIG_SYS_TEXT_BASE) " +$filesize; " \ 418 "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) " $filesize\0" \ 419 "kernelflash=tftpboot $loadaddr $bootfile; " \ 420 "protect off 0xefa80000 +$filesize; " \ 421 "erase 0xefa80000 +$filesize; " \ 422 "cp.b $loadaddr 0xefa80000 $filesize; " \ 423 "protect on 0xefa80000 +$filesize; " \ 424 "cmp.b $loadaddr 0xefa80000 $filesize\0" \ 425 "dtbflash=tftpboot $loadaddr $dtbfile; " \ 426 "protect off 0xefe80000 +$filesize; " \ 427 "erase 0xefe80000 +$filesize; " \ 428 "cp.b $loadaddr 0xefe80000 $filesize; " \ 429 "protect on 0xefe80000 +$filesize; " \ 430 "cmp.b $loadaddr 0xefe80000 $filesize\0" \ 431 "ramdiskflash=tftpboot $loadaddr $ramdiskfile; " \ 432 "protect off 0xeeb80000 +$filesize; " \ 433 "erase 0xeeb80000 +$filesize; " \ 434 "cp.b $loadaddr 0xeeb80000 $filesize; " \ 435 "protect on 0xeeb80000 +$filesize; " \ 436 "cmp.b $loadaddr 0xeeb80000 $filesize\0" \ 437 "qefirmwareflash=tftpboot $loadaddr $qefirmwarefile; " \ 438 "protect off 0xefec0000 +$filesize; " \ 439 "erase 0xefec0000 +$filesize; " \ 440 "cp.b $loadaddr 0xefec0000 $filesize; " \ 441 "protect on 0xefec0000 +$filesize; " \ 442 "cmp.b $loadaddr 0xefec0000 $filesize\0" \ 443 "consoledev=ttyS0\0" \ 444 "ramdiskaddr=2000000\0" \ 445 "ramdiskfile=rootfs.ext2.gz.uboot\0" \ 446 "fdtaddr=1e00000\0" \ 447 "bdev=sda1\0" \ 448 "norbootaddr=ef080000\0" \ 449 "norfdtaddr=ef040000\0" \ 450 "ramdisk_size=120000\0" \ 451 "usbboot=setenv bootargs root=/dev/sda1 rw rootdelay=5 " \ 452 "console=$consoledev,$baudrate $othbootargs ; bootm 0xefa80000 - 0xefe80000" 453 454 #define CONFIG_NFSBOOTCOMMAND \ 455 "setenv bootargs root=/dev/nfs rw " \ 456 "nfsroot=$serverip:$rootpath " \ 457 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 458 "console=$consoledev,$baudrate $othbootargs;" \ 459 "tftp $loadaddr $bootfile&&" \ 460 "tftp $fdtaddr $fdtfile&&" \ 461 "bootm $loadaddr - $fdtaddr" 462 463 #define CONFIG_HDBOOT \ 464 "setenv bootargs root=/dev/$bdev rw rootdelay=30 " \ 465 "console=$consoledev,$baudrate $othbootargs;" \ 466 "usb start;" \ 467 "ext2load usb 0:1 $loadaddr /boot/$bootfile;" \ 468 "ext2load usb 0:1 $fdtaddr /boot/$fdtfile;" \ 469 "bootm $loadaddr - $fdtaddr" 470 471 #define CONFIG_USB_FAT_BOOT \ 472 "setenv bootargs root=/dev/ram rw " \ 473 "console=$consoledev,$baudrate $othbootargs " \ 474 "ramdisk_size=$ramdisk_size;" \ 475 "usb start;" \ 476 "fatload usb 0:2 $loadaddr $bootfile;" \ 477 "fatload usb 0:2 $fdtaddr $fdtfile;" \ 478 "fatload usb 0:2 $ramdiskaddr $ramdiskfile;" \ 479 "bootm $loadaddr $ramdiskaddr $fdtaddr" 480 481 #define CONFIG_USB_EXT2_BOOT \ 482 "setenv bootargs root=/dev/ram rw " \ 483 "console=$consoledev,$baudrate $othbootargs " \ 484 "ramdisk_size=$ramdisk_size;" \ 485 "usb start;" \ 486 "ext2load usb 0:4 $loadaddr $bootfile;" \ 487 "ext2load usb 0:4 $fdtaddr $fdtfile;" \ 488 "ext2load usb 0:4 $ramdiskaddr $ramdiskfile;" \ 489 "bootm $loadaddr $ramdiskaddr $fdtaddr" 490 491 #define CONFIG_NORBOOT \ 492 "setenv bootargs root=/dev/mtdblock3 rw " \ 493 "console=$consoledev,$baudrate rootfstype=jffs2 $othbootargs;" \ 494 "bootm $norbootaddr - $norfdtaddr" 495 496 #define CONFIG_RAMBOOTCOMMAND_TFTP \ 497 "setenv bootargs root=/dev/ram rw " \ 498 "console=$consoledev,$baudrate $othbootargs " \ 499 "ramdisk_size=$ramdisk_size;" \ 500 "tftp $ramdiskaddr $ramdiskfile;" \ 501 "tftp $loadaddr $bootfile;" \ 502 "tftp $fdtaddr $fdtfile;" \ 503 "bootm $loadaddr $ramdiskaddr $fdtaddr" 504 505 #define CONFIG_RAMBOOTCOMMAND \ 506 "setenv bootargs root=/dev/ram rw " \ 507 "console=$consoledev,$baudrate $othbootargs " \ 508 "ramdisk_size=$ramdisk_size;" \ 509 "bootm 0xefa80000 0xeeb80000 0xefe80000" 510 511 #define CONFIG_BOOTCOMMAND CONFIG_RAMBOOTCOMMAND 512 513 #endif /* __CONFIG_H */ 514