1 /* 2 * Copyright 2013 Freescale Semiconductor, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 /* 8 * QorIQ P1 Tower boards configuration file 9 */ 10 #ifndef __CONFIG_H 11 #define __CONFIG_H 12 13 #if defined(CONFIG_TWR_P1025) 14 #define CONFIG_BOARDNAME "TWR-P1025" 15 #define CONFIG_PHY_ATHEROS 16 #define CONFIG_QE 17 #define CONFIG_SYS_LBC_LBCR 0x00080000 /* Conversion of LBC addr */ 18 #define CONFIG_SYS_LBC_LCRR 0x80000002 /* LB clock ratio reg */ 19 #endif 20 21 #ifdef CONFIG_SDCARD 22 #define CONFIG_RAMBOOT_SDCARD 23 #define CONFIG_SYS_RAMBOOT 24 #define CONFIG_SYS_EXTRA_ENV_RELOC 25 #define CONFIG_RESET_VECTOR_ADDRESS 0x110bfffc 26 #endif 27 28 #ifndef CONFIG_RESET_VECTOR_ADDRESS 29 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc 30 #endif 31 32 #ifndef CONFIG_SYS_MONITOR_BASE 33 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 34 #endif 35 36 #define CONFIG_MP 37 38 #define CONFIG_PCIE1 /* PCIE controller 1 (slot 1) */ 39 #define CONFIG_PCIE2 /* PCIE controller 2 (slot 2) */ 40 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ 41 #define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */ 42 #define CONFIG_FSL_PCIE_RESET /* need PCIe reset errata */ 43 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ 44 45 #define CONFIG_ENV_OVERWRITE 46 47 #define CONFIG_SYS_SATA_MAX_DEVICE 2 48 #define CONFIG_LBA48 49 50 #ifndef __ASSEMBLY__ 51 extern unsigned long get_board_sys_clk(unsigned long dummy); 52 #endif 53 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk(0) /*sysclk for TWR-P1025 */ 54 55 #define CONFIG_DDR_CLK_FREQ 66666666 56 57 #define CONFIG_HWCONFIG 58 /* 59 * These can be toggled for performance analysis, otherwise use default. 60 */ 61 #define CONFIG_L2_CACHE 62 #define CONFIG_BTB 63 64 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ 65 #define CONFIG_SYS_MEMTEST_END 0x1fffffff 66 67 #define CONFIG_SYS_CCSRBAR 0xffe00000 68 #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR 69 70 /* DDR Setup */ 71 72 #define CONFIG_SYS_SDRAM_SIZE_LAW LAW_SIZE_512M 73 #define CONFIG_CHIP_SELECTS_PER_CTRL 1 74 75 #define CONFIG_SYS_SDRAM_SIZE (1u << (CONFIG_SYS_SDRAM_SIZE_LAW - 19)) 76 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 77 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 78 79 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 80 81 /* Default settings for DDR3 */ 82 #define CONFIG_SYS_DDR_CS0_BNDS 0x0000001f 83 #define CONFIG_SYS_DDR_CS0_CONFIG 0x80014202 84 #define CONFIG_SYS_DDR_CS0_CONFIG_2 0x00000000 85 #define CONFIG_SYS_DDR_CS1_BNDS 0x00000000 86 #define CONFIG_SYS_DDR_CS1_CONFIG 0x00000000 87 #define CONFIG_SYS_DDR_CS1_CONFIG_2 0x00000000 88 89 #define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef 90 #define CONFIG_SYS_DDR_INIT_ADDR 0x00000000 91 #define CONFIG_SYS_DDR_INIT_EXT_ADDR 0x00000000 92 #define CONFIG_SYS_DDR_MODE_CONTROL 0x00000000 93 94 #define CONFIG_SYS_DDR_ZQ_CONTROL 0x89080600 95 #define CONFIG_SYS_DDR_WRLVL_CONTROL 0x8655a608 96 #define CONFIG_SYS_DDR_SR_CNTR 0x00000000 97 #define CONFIG_SYS_DDR_RCW_1 0x00000000 98 #define CONFIG_SYS_DDR_RCW_2 0x00000000 99 #define CONFIG_SYS_DDR_CONTROL 0xc70c0000 /* Type = DDR3 */ 100 #define CONFIG_SYS_DDR_CONTROL_2 0x04401050 101 #define CONFIG_SYS_DDR_TIMING_4 0x00220001 102 #define CONFIG_SYS_DDR_TIMING_5 0x03402400 103 104 #define CONFIG_SYS_DDR_TIMING_3 0x00020000 105 #define CONFIG_SYS_DDR_TIMING_0 0x00220004 106 #define CONFIG_SYS_DDR_TIMING_1 0x5c5b6544 107 #define CONFIG_SYS_DDR_TIMING_2 0x0fa880de 108 #define CONFIG_SYS_DDR_CLK_CTRL 0x03000000 109 #define CONFIG_SYS_DDR_MODE_1 0x80461320 110 #define CONFIG_SYS_DDR_MODE_2 0x00008000 111 #define CONFIG_SYS_DDR_INTERVAL 0x09480000 112 113 /* 114 * Memory map 115 * 116 * 0x0000_0000 0x1fff_ffff DDR Up to 512MB cacheable 117 * 0x8000_0000 0xdfff_ffff PCI Express Mem 1.5G non-cacheable(PCIe * 3) 118 * 0xffc0_0000 0xffc3_ffff PCI IO range 256k non-cacheable 119 * 120 * Localbus 121 * 0xe000_0000 0xe002_0000 SSD1289 128K non-cacheable 122 * 0xec00_0000 0xefff_ffff FLASH Up to 64M non-cacheable 123 * 124 * 0xff90_0000 0xff97_ffff L2 SRAM Up to 512K cacheable 125 * 0xffd0_0000 0xffd0_3fff init ram 16K Cacheable 126 * 0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable 127 */ 128 129 /* 130 * Local Bus Definitions 131 */ 132 #define CONFIG_SYS_MAX_FLASH_SECT 512 /* 64M */ 133 #define CONFIG_SYS_FLASH_BASE 0xec000000 134 135 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE 136 137 #define CONFIG_FLASH_BR_PRELIM (BR_PHYS_ADDR((CONFIG_SYS_FLASH_BASE_PHYS)) \ 138 | BR_PS_16 | BR_V) 139 140 #define CONFIG_FLASH_OR_PRELIM 0xfc0000b1 141 142 #define CONFIG_SYS_SSD_BASE 0xe0000000 143 #define CONFIG_SYS_SSD_BASE_PHYS CONFIG_SYS_SSD_BASE 144 #define CONFIG_SSD_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_SSD_BASE_PHYS) | \ 145 BR_PS_16 | BR_V) 146 #define CONFIG_SSD_OR_PRELIM (OR_AM_64KB | OR_GPCM_CSNT | OR_GPCM_XACS | \ 147 OR_GPCM_ACS_DIV2 | OR_GPCM_SCY | \ 148 OR_GPCM_TRLX | OR_GPCM_EHTR | OR_GPCM_EAD) 149 150 #define CONFIG_SYS_BR2_PRELIM CONFIG_SSD_BR_PRELIM 151 #define CONFIG_SYS_OR2_PRELIM CONFIG_SSD_OR_PRELIM 152 153 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS} 154 #define CONFIG_SYS_FLASH_QUIET_TEST 155 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 156 157 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ 158 159 #undef CONFIG_SYS_FLASH_CHECKSUM 160 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 161 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 162 163 #define CONFIG_FLASH_CFI_DRIVER 164 #define CONFIG_SYS_FLASH_CFI 165 #define CONFIG_SYS_FLASH_EMPTY_INFO 166 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 167 168 #define CONFIG_SYS_INIT_RAM_LOCK 169 #define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 170 /* Initial L1 address */ 171 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS CONFIG_SYS_INIT_RAM_ADDR 172 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0 173 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS 174 /* Size of used area in RAM */ 175 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 176 177 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ 178 GENERATED_GBL_DATA_SIZE) 179 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 180 181 #define CONFIG_SYS_MONITOR_LEN (768 * 1024) 182 #define CONFIG_SYS_MALLOC_LEN (1024 * 1024)/* Reserved for malloc */ 183 184 #define CONFIG_SYS_BR0_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */ 185 #define CONFIG_SYS_OR0_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */ 186 187 /* Serial Port 188 * open - index 2 189 * shorted - index 1 190 */ 191 #undef CONFIG_SERIAL_SOFTWARE_FIFO 192 #define CONFIG_SYS_NS16550_SERIAL 193 #define CONFIG_SYS_NS16550_REG_SIZE 1 194 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) 195 196 #define CONFIG_SYS_BAUDRATE_TABLE \ 197 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} 198 199 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) 200 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) 201 202 /* I2C */ 203 #define CONFIG_SYS_I2C 204 #define CONFIG_SYS_I2C_FSL /* Use FSL common I2C driver */ 205 #define CONFIG_SYS_FSL_I2C_SPEED 400000 /* I2C spd and slave address */ 206 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 207 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 208 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x52 209 210 /* 211 * I2C2 EEPROM 212 */ 213 #define CONFIG_SYS_FSL_I2C2_SPEED 400000 /* I2C spd and slave address */ 214 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F 215 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100 216 217 #define CONFIG_SYS_I2C_PCA9555_ADDR 0x23 218 219 /* enable read and write access to EEPROM */ 220 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 221 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 222 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 223 224 /* 225 * eSPI - Enhanced SPI 226 */ 227 #define CONFIG_HARD_SPI 228 229 #if defined(CONFIG_PCI) 230 /* 231 * General PCI 232 * Memory space is mapped 1-1, but I/O space must start from 0. 233 */ 234 235 /* controller 2, direct to uli, tgtid 2, Base address 9000 */ 236 #define CONFIG_SYS_PCIE2_NAME "TWR-ELEV PCIe SLOT" 237 #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000 238 #define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000 239 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000 240 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */ 241 #define CONFIG_SYS_PCIE2_IO_VIRT 0xffc10000 242 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 243 #define CONFIG_SYS_PCIE2_IO_PHYS 0xffc10000 244 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ 245 246 /* controller 1, tgtid 1, Base address a000 */ 247 #define CONFIG_SYS_PCIE1_NAME "mini PCIe SLOT" 248 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 249 #define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000 250 #define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000 251 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ 252 #define CONFIG_SYS_PCIE1_IO_VIRT 0xffc00000 253 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 254 #define CONFIG_SYS_PCIE1_IO_PHYS 0xffc00000 255 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ 256 257 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 258 #endif /* CONFIG_PCI */ 259 260 #if defined(CONFIG_TSEC_ENET) 261 262 #define CONFIG_MII /* MII PHY management */ 263 #define CONFIG_TSEC1 264 #define CONFIG_TSEC1_NAME "eTSEC1" 265 #undef CONFIG_TSEC2 266 #undef CONFIG_TSEC2_NAME 267 #define CONFIG_TSEC3 268 #define CONFIG_TSEC3_NAME "eTSEC3" 269 270 #define TSEC1_PHY_ADDR 2 271 #define TSEC2_PHY_ADDR 0 272 #define TSEC3_PHY_ADDR 1 273 274 #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 275 #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 276 #define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 277 278 #define TSEC1_PHYIDX 0 279 #define TSEC2_PHYIDX 0 280 #define TSEC3_PHYIDX 0 281 282 #define CONFIG_ETHPRIME "eTSEC1" 283 284 #define CONFIG_HAS_ETH0 285 #define CONFIG_HAS_ETH1 286 #undef CONFIG_HAS_ETH2 287 #endif /* CONFIG_TSEC_ENET */ 288 289 #ifdef CONFIG_QE 290 /* QE microcode/firmware address */ 291 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR 292 #define CONFIG_SYS_QE_FW_ADDR 0xefec0000 293 #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 294 #endif /* CONFIG_QE */ 295 296 #ifdef CONFIG_TWR_P1025 297 /* 298 * QE UEC ethernet configuration 299 */ 300 #define CONFIG_MIIM_ADDRESS (CONFIG_SYS_CCSRBAR + 0x82120) 301 302 #undef CONFIG_UEC_ETH 303 #define CONFIG_PHY_MODE_NEED_CHANGE 304 305 #define CONFIG_UEC_ETH1 /* ETH1 */ 306 #define CONFIG_HAS_ETH0 307 308 #ifdef CONFIG_UEC_ETH1 309 #define CONFIG_SYS_UEC1_UCC_NUM 0 /* UCC1 */ 310 #define CONFIG_SYS_UEC1_RX_CLK QE_CLK12 /* CLK12 for MII */ 311 #define CONFIG_SYS_UEC1_TX_CLK QE_CLK9 /* CLK9 for MII */ 312 #define CONFIG_SYS_UEC1_ETH_TYPE FAST_ETH 313 #define CONFIG_SYS_UEC1_PHY_ADDR 0x18 /* 0x18 for MII */ 314 #define CONFIG_SYS_UEC1_INTERFACE_TYPE PHY_INTERFACE_MODE_MII 315 #define CONFIG_SYS_UEC1_INTERFACE_SPEED 100 316 #endif /* CONFIG_UEC_ETH1 */ 317 318 #define CONFIG_UEC_ETH5 /* ETH5 */ 319 #define CONFIG_HAS_ETH1 320 321 #ifdef CONFIG_UEC_ETH5 322 #define CONFIG_SYS_UEC5_UCC_NUM 4 /* UCC5 */ 323 #define CONFIG_SYS_UEC5_RX_CLK QE_CLK_NONE 324 #define CONFIG_SYS_UEC5_TX_CLK QE_CLK13 /* CLK 13 for RMII */ 325 #define CONFIG_SYS_UEC5_ETH_TYPE FAST_ETH 326 #define CONFIG_SYS_UEC5_PHY_ADDR 0x19 /* 0x19 for RMII */ 327 #define CONFIG_SYS_UEC5_INTERFACE_TYPE PHY_INTERFACE_MODE_RMII 328 #define CONFIG_SYS_UEC5_INTERFACE_SPEED 100 329 #endif /* CONFIG_UEC_ETH5 */ 330 #endif /* CONFIG_TWR-P1025 */ 331 332 /* 333 * Dynamic MTD Partition support with mtdparts 334 */ 335 #define CONFIG_MTD_DEVICE 336 #define CONFIG_MTD_PARTITIONS 337 #define CONFIG_FLASH_CFI_MTD 338 339 /* 340 * Environment 341 */ 342 #ifdef CONFIG_SYS_RAMBOOT 343 #ifdef CONFIG_RAMBOOT_SDCARD 344 #define CONFIG_ENV_SIZE 0x2000 345 #define CONFIG_SYS_MMC_ENV_DEV 0 346 #else 347 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) 348 #define CONFIG_ENV_SIZE 0x2000 349 #endif 350 #else 351 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) 352 #define CONFIG_ENV_SIZE 0x2000 353 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ 354 #endif 355 356 #define CONFIG_LOADS_ECHO /* echo on for serial download */ 357 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ 358 359 /* 360 * USB 361 */ 362 #define CONFIG_HAS_FSL_DR_USB 363 364 #if defined(CONFIG_HAS_FSL_DR_USB) 365 #ifdef CONFIG_USB_EHCI_HCD 366 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 367 #define CONFIG_USB_EHCI_FSL 368 #endif 369 #endif 370 371 #ifdef CONFIG_MMC 372 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR 373 #endif 374 375 #undef CONFIG_WATCHDOG /* watchdog disabled */ 376 377 /* 378 * Miscellaneous configurable options 379 */ 380 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 381 382 /* 383 * For booting Linux, the board info and command line data 384 * have to be in the first 64 MB of memory, since this is 385 * the maximum mapped by the Linux kernel during initialization. 386 */ 387 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory for Linux*/ 388 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 389 390 /* 391 * Environment Configuration 392 */ 393 #define CONFIG_HOSTNAME "unknown" 394 #define CONFIG_ROOTPATH "/opt/nfsroot" 395 #define CONFIG_BOOTFILE "uImage" 396 #define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */ 397 398 /* default location for tftp and bootm */ 399 #define CONFIG_LOADADDR 1000000 400 401 #define CONFIG_EXTRA_ENV_SETTINGS \ 402 "netdev=eth0\0" \ 403 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ 404 "loadaddr=1000000\0" \ 405 "bootfile=uImage\0" \ 406 "dtbfile=twr-p1025twr.dtb\0" \ 407 "ramdiskfile=rootfs.ext2.gz.uboot\0" \ 408 "qefirmwarefile=fsl_qe_ucode_1021_10_A.bin\0" \ 409 "tftpflash=tftpboot $loadaddr $uboot; " \ 410 "protect off " __stringify(CONFIG_SYS_TEXT_BASE) " +$filesize; " \ 411 "erase " __stringify(CONFIG_SYS_TEXT_BASE) " +$filesize; " \ 412 "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) " $filesize; " \ 413 "protect on " __stringify(CONFIG_SYS_TEXT_BASE) " +$filesize; " \ 414 "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) " $filesize\0" \ 415 "kernelflash=tftpboot $loadaddr $bootfile; " \ 416 "protect off 0xefa80000 +$filesize; " \ 417 "erase 0xefa80000 +$filesize; " \ 418 "cp.b $loadaddr 0xefa80000 $filesize; " \ 419 "protect on 0xefa80000 +$filesize; " \ 420 "cmp.b $loadaddr 0xefa80000 $filesize\0" \ 421 "dtbflash=tftpboot $loadaddr $dtbfile; " \ 422 "protect off 0xefe80000 +$filesize; " \ 423 "erase 0xefe80000 +$filesize; " \ 424 "cp.b $loadaddr 0xefe80000 $filesize; " \ 425 "protect on 0xefe80000 +$filesize; " \ 426 "cmp.b $loadaddr 0xefe80000 $filesize\0" \ 427 "ramdiskflash=tftpboot $loadaddr $ramdiskfile; " \ 428 "protect off 0xeeb80000 +$filesize; " \ 429 "erase 0xeeb80000 +$filesize; " \ 430 "cp.b $loadaddr 0xeeb80000 $filesize; " \ 431 "protect on 0xeeb80000 +$filesize; " \ 432 "cmp.b $loadaddr 0xeeb80000 $filesize\0" \ 433 "qefirmwareflash=tftpboot $loadaddr $qefirmwarefile; " \ 434 "protect off 0xefec0000 +$filesize; " \ 435 "erase 0xefec0000 +$filesize; " \ 436 "cp.b $loadaddr 0xefec0000 $filesize; " \ 437 "protect on 0xefec0000 +$filesize; " \ 438 "cmp.b $loadaddr 0xefec0000 $filesize\0" \ 439 "consoledev=ttyS0\0" \ 440 "ramdiskaddr=2000000\0" \ 441 "ramdiskfile=rootfs.ext2.gz.uboot\0" \ 442 "fdtaddr=1e00000\0" \ 443 "bdev=sda1\0" \ 444 "norbootaddr=ef080000\0" \ 445 "norfdtaddr=ef040000\0" \ 446 "ramdisk_size=120000\0" \ 447 "usbboot=setenv bootargs root=/dev/sda1 rw rootdelay=5 " \ 448 "console=$consoledev,$baudrate $othbootargs ; bootm 0xefa80000 - 0xefe80000" 449 450 #define CONFIG_NFSBOOTCOMMAND \ 451 "setenv bootargs root=/dev/nfs rw " \ 452 "nfsroot=$serverip:$rootpath " \ 453 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 454 "console=$consoledev,$baudrate $othbootargs;" \ 455 "tftp $loadaddr $bootfile&&" \ 456 "tftp $fdtaddr $fdtfile&&" \ 457 "bootm $loadaddr - $fdtaddr" 458 459 #define CONFIG_HDBOOT \ 460 "setenv bootargs root=/dev/$bdev rw rootdelay=30 " \ 461 "console=$consoledev,$baudrate $othbootargs;" \ 462 "usb start;" \ 463 "ext2load usb 0:1 $loadaddr /boot/$bootfile;" \ 464 "ext2load usb 0:1 $fdtaddr /boot/$fdtfile;" \ 465 "bootm $loadaddr - $fdtaddr" 466 467 #define CONFIG_USB_FAT_BOOT \ 468 "setenv bootargs root=/dev/ram rw " \ 469 "console=$consoledev,$baudrate $othbootargs " \ 470 "ramdisk_size=$ramdisk_size;" \ 471 "usb start;" \ 472 "fatload usb 0:2 $loadaddr $bootfile;" \ 473 "fatload usb 0:2 $fdtaddr $fdtfile;" \ 474 "fatload usb 0:2 $ramdiskaddr $ramdiskfile;" \ 475 "bootm $loadaddr $ramdiskaddr $fdtaddr" 476 477 #define CONFIG_USB_EXT2_BOOT \ 478 "setenv bootargs root=/dev/ram rw " \ 479 "console=$consoledev,$baudrate $othbootargs " \ 480 "ramdisk_size=$ramdisk_size;" \ 481 "usb start;" \ 482 "ext2load usb 0:4 $loadaddr $bootfile;" \ 483 "ext2load usb 0:4 $fdtaddr $fdtfile;" \ 484 "ext2load usb 0:4 $ramdiskaddr $ramdiskfile;" \ 485 "bootm $loadaddr $ramdiskaddr $fdtaddr" 486 487 #define CONFIG_NORBOOT \ 488 "setenv bootargs root=/dev/mtdblock3 rw " \ 489 "console=$consoledev,$baudrate rootfstype=jffs2 $othbootargs;" \ 490 "bootm $norbootaddr - $norfdtaddr" 491 492 #define CONFIG_RAMBOOTCOMMAND_TFTP \ 493 "setenv bootargs root=/dev/ram rw " \ 494 "console=$consoledev,$baudrate $othbootargs " \ 495 "ramdisk_size=$ramdisk_size;" \ 496 "tftp $ramdiskaddr $ramdiskfile;" \ 497 "tftp $loadaddr $bootfile;" \ 498 "tftp $fdtaddr $fdtfile;" \ 499 "bootm $loadaddr $ramdiskaddr $fdtaddr" 500 501 #define CONFIG_RAMBOOTCOMMAND \ 502 "setenv bootargs root=/dev/ram rw " \ 503 "console=$consoledev,$baudrate $othbootargs " \ 504 "ramdisk_size=$ramdisk_size;" \ 505 "bootm 0xefa80000 0xeeb80000 0xefe80000" 506 507 #define CONFIG_BOOTCOMMAND CONFIG_RAMBOOTCOMMAND 508 509 #endif /* __CONFIG_H */ 510