1 /* 2 * Copyright 2013 Freescale Semiconductor, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 /* 8 * QorIQ P1 Tower boards configuration file 9 */ 10 #ifndef __CONFIG_H 11 #define __CONFIG_H 12 13 #if defined(CONFIG_TWR_P1025) 14 #define CONFIG_BOARDNAME "TWR-P1025" 15 #define CONFIG_PHY_ATHEROS 16 #define CONFIG_QE 17 #define CONFIG_SYS_LBC_LBCR 0x00080000 /* Conversion of LBC addr */ 18 #define CONFIG_SYS_LBC_LCRR 0x80000002 /* LB clock ratio reg */ 19 #endif 20 21 #ifdef CONFIG_SDCARD 22 #define CONFIG_RAMBOOT_SDCARD 23 #define CONFIG_SYS_RAMBOOT 24 #define CONFIG_SYS_EXTRA_ENV_RELOC 25 #define CONFIG_RESET_VECTOR_ADDRESS 0x110bfffc 26 #endif 27 28 #ifndef CONFIG_RESET_VECTOR_ADDRESS 29 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc 30 #endif 31 32 #ifndef CONFIG_SYS_MONITOR_BASE 33 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 34 #endif 35 36 #define CONFIG_MP 37 38 #define CONFIG_PCIE1 /* PCIE controller 1 (slot 1) */ 39 #define CONFIG_PCIE2 /* PCIE controller 2 (slot 2) */ 40 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ 41 #define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */ 42 #define CONFIG_FSL_PCIE_RESET /* need PCIe reset errata */ 43 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ 44 45 #define CONFIG_TSEC_ENET /* tsec ethernet support */ 46 #define CONFIG_ENV_OVERWRITE 47 48 #define CONFIG_SYS_SATA_MAX_DEVICE 2 49 #define CONFIG_LBA48 50 51 #ifndef __ASSEMBLY__ 52 extern unsigned long get_board_sys_clk(unsigned long dummy); 53 #endif 54 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk(0) /*sysclk for TWR-P1025 */ 55 56 #define CONFIG_DDR_CLK_FREQ 66666666 57 58 #define CONFIG_HWCONFIG 59 /* 60 * These can be toggled for performance analysis, otherwise use default. 61 */ 62 #define CONFIG_L2_CACHE 63 #define CONFIG_BTB 64 65 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ 66 #define CONFIG_SYS_MEMTEST_END 0x1fffffff 67 68 #define CONFIG_SYS_CCSRBAR 0xffe00000 69 #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR 70 71 /* DDR Setup */ 72 73 #define CONFIG_SYS_SDRAM_SIZE_LAW LAW_SIZE_512M 74 #define CONFIG_CHIP_SELECTS_PER_CTRL 1 75 76 #define CONFIG_SYS_SDRAM_SIZE (1u << (CONFIG_SYS_SDRAM_SIZE_LAW - 19)) 77 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 78 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 79 80 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 81 82 /* Default settings for DDR3 */ 83 #define CONFIG_SYS_DDR_CS0_BNDS 0x0000001f 84 #define CONFIG_SYS_DDR_CS0_CONFIG 0x80014202 85 #define CONFIG_SYS_DDR_CS0_CONFIG_2 0x00000000 86 #define CONFIG_SYS_DDR_CS1_BNDS 0x00000000 87 #define CONFIG_SYS_DDR_CS1_CONFIG 0x00000000 88 #define CONFIG_SYS_DDR_CS1_CONFIG_2 0x00000000 89 90 #define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef 91 #define CONFIG_SYS_DDR_INIT_ADDR 0x00000000 92 #define CONFIG_SYS_DDR_INIT_EXT_ADDR 0x00000000 93 #define CONFIG_SYS_DDR_MODE_CONTROL 0x00000000 94 95 #define CONFIG_SYS_DDR_ZQ_CONTROL 0x89080600 96 #define CONFIG_SYS_DDR_WRLVL_CONTROL 0x8655a608 97 #define CONFIG_SYS_DDR_SR_CNTR 0x00000000 98 #define CONFIG_SYS_DDR_RCW_1 0x00000000 99 #define CONFIG_SYS_DDR_RCW_2 0x00000000 100 #define CONFIG_SYS_DDR_CONTROL 0xc70c0000 /* Type = DDR3 */ 101 #define CONFIG_SYS_DDR_CONTROL_2 0x04401050 102 #define CONFIG_SYS_DDR_TIMING_4 0x00220001 103 #define CONFIG_SYS_DDR_TIMING_5 0x03402400 104 105 #define CONFIG_SYS_DDR_TIMING_3 0x00020000 106 #define CONFIG_SYS_DDR_TIMING_0 0x00220004 107 #define CONFIG_SYS_DDR_TIMING_1 0x5c5b6544 108 #define CONFIG_SYS_DDR_TIMING_2 0x0fa880de 109 #define CONFIG_SYS_DDR_CLK_CTRL 0x03000000 110 #define CONFIG_SYS_DDR_MODE_1 0x80461320 111 #define CONFIG_SYS_DDR_MODE_2 0x00008000 112 #define CONFIG_SYS_DDR_INTERVAL 0x09480000 113 114 /* 115 * Memory map 116 * 117 * 0x0000_0000 0x1fff_ffff DDR Up to 512MB cacheable 118 * 0x8000_0000 0xdfff_ffff PCI Express Mem 1.5G non-cacheable(PCIe * 3) 119 * 0xffc0_0000 0xffc3_ffff PCI IO range 256k non-cacheable 120 * 121 * Localbus 122 * 0xe000_0000 0xe002_0000 SSD1289 128K non-cacheable 123 * 0xec00_0000 0xefff_ffff FLASH Up to 64M non-cacheable 124 * 125 * 0xff90_0000 0xff97_ffff L2 SRAM Up to 512K cacheable 126 * 0xffd0_0000 0xffd0_3fff init ram 16K Cacheable 127 * 0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable 128 */ 129 130 /* 131 * Local Bus Definitions 132 */ 133 #define CONFIG_SYS_MAX_FLASH_SECT 512 /* 64M */ 134 #define CONFIG_SYS_FLASH_BASE 0xec000000 135 136 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE 137 138 #define CONFIG_FLASH_BR_PRELIM (BR_PHYS_ADDR((CONFIG_SYS_FLASH_BASE_PHYS)) \ 139 | BR_PS_16 | BR_V) 140 141 #define CONFIG_FLASH_OR_PRELIM 0xfc0000b1 142 143 #define CONFIG_SYS_SSD_BASE 0xe0000000 144 #define CONFIG_SYS_SSD_BASE_PHYS CONFIG_SYS_SSD_BASE 145 #define CONFIG_SSD_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_SSD_BASE_PHYS) | \ 146 BR_PS_16 | BR_V) 147 #define CONFIG_SSD_OR_PRELIM (OR_AM_64KB | OR_GPCM_CSNT | OR_GPCM_XACS | \ 148 OR_GPCM_ACS_DIV2 | OR_GPCM_SCY | \ 149 OR_GPCM_TRLX | OR_GPCM_EHTR | OR_GPCM_EAD) 150 151 #define CONFIG_SYS_BR2_PRELIM CONFIG_SSD_BR_PRELIM 152 #define CONFIG_SYS_OR2_PRELIM CONFIG_SSD_OR_PRELIM 153 154 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS} 155 #define CONFIG_SYS_FLASH_QUIET_TEST 156 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 157 158 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ 159 160 #undef CONFIG_SYS_FLASH_CHECKSUM 161 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 162 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 163 164 #define CONFIG_FLASH_CFI_DRIVER 165 #define CONFIG_SYS_FLASH_CFI 166 #define CONFIG_SYS_FLASH_EMPTY_INFO 167 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 168 169 #define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */ 170 171 #define CONFIG_SYS_INIT_RAM_LOCK 172 #define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 173 /* Initial L1 address */ 174 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS CONFIG_SYS_INIT_RAM_ADDR 175 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0 176 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS 177 /* Size of used area in RAM */ 178 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 179 180 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ 181 GENERATED_GBL_DATA_SIZE) 182 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 183 184 #define CONFIG_SYS_MONITOR_LEN (768 * 1024) 185 #define CONFIG_SYS_MALLOC_LEN (1024 * 1024)/* Reserved for malloc */ 186 187 #define CONFIG_SYS_BR0_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */ 188 #define CONFIG_SYS_OR0_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */ 189 190 /* Serial Port 191 * open - index 2 192 * shorted - index 1 193 */ 194 #define CONFIG_CONS_INDEX 1 195 #undef CONFIG_SERIAL_SOFTWARE_FIFO 196 #define CONFIG_SYS_NS16550_SERIAL 197 #define CONFIG_SYS_NS16550_REG_SIZE 1 198 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) 199 200 #define CONFIG_SYS_BAUDRATE_TABLE \ 201 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} 202 203 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) 204 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) 205 206 /* I2C */ 207 #define CONFIG_SYS_I2C 208 #define CONFIG_SYS_I2C_FSL /* Use FSL common I2C driver */ 209 #define CONFIG_SYS_FSL_I2C_SPEED 400000 /* I2C spd and slave address */ 210 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 211 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 212 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x52 213 214 /* 215 * I2C2 EEPROM 216 */ 217 #define CONFIG_SYS_FSL_I2C2_SPEED 400000 /* I2C spd and slave address */ 218 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F 219 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100 220 221 #define CONFIG_SYS_I2C_PCA9555_ADDR 0x23 222 223 /* enable read and write access to EEPROM */ 224 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 225 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 226 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 227 228 /* 229 * eSPI - Enhanced SPI 230 */ 231 #define CONFIG_HARD_SPI 232 233 #if defined(CONFIG_PCI) 234 /* 235 * General PCI 236 * Memory space is mapped 1-1, but I/O space must start from 0. 237 */ 238 239 /* controller 2, direct to uli, tgtid 2, Base address 9000 */ 240 #define CONFIG_SYS_PCIE2_NAME "TWR-ELEV PCIe SLOT" 241 #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000 242 #define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000 243 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000 244 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */ 245 #define CONFIG_SYS_PCIE2_IO_VIRT 0xffc10000 246 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 247 #define CONFIG_SYS_PCIE2_IO_PHYS 0xffc10000 248 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ 249 250 /* controller 1, tgtid 1, Base address a000 */ 251 #define CONFIG_SYS_PCIE1_NAME "mini PCIe SLOT" 252 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 253 #define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000 254 #define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000 255 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ 256 #define CONFIG_SYS_PCIE1_IO_VIRT 0xffc00000 257 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 258 #define CONFIG_SYS_PCIE1_IO_PHYS 0xffc00000 259 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ 260 261 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 262 #endif /* CONFIG_PCI */ 263 264 #if defined(CONFIG_TSEC_ENET) 265 266 #define CONFIG_MII /* MII PHY management */ 267 #define CONFIG_TSEC1 268 #define CONFIG_TSEC1_NAME "eTSEC1" 269 #undef CONFIG_TSEC2 270 #undef CONFIG_TSEC2_NAME 271 #define CONFIG_TSEC3 272 #define CONFIG_TSEC3_NAME "eTSEC3" 273 274 #define TSEC1_PHY_ADDR 2 275 #define TSEC2_PHY_ADDR 0 276 #define TSEC3_PHY_ADDR 1 277 278 #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 279 #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 280 #define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 281 282 #define TSEC1_PHYIDX 0 283 #define TSEC2_PHYIDX 0 284 #define TSEC3_PHYIDX 0 285 286 #define CONFIG_ETHPRIME "eTSEC1" 287 288 #define CONFIG_HAS_ETH0 289 #define CONFIG_HAS_ETH1 290 #undef CONFIG_HAS_ETH2 291 #endif /* CONFIG_TSEC_ENET */ 292 293 #ifdef CONFIG_QE 294 /* QE microcode/firmware address */ 295 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR 296 #define CONFIG_SYS_QE_FW_ADDR 0xefec0000 297 #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 298 #endif /* CONFIG_QE */ 299 300 #ifdef CONFIG_TWR_P1025 301 /* 302 * QE UEC ethernet configuration 303 */ 304 #define CONFIG_MIIM_ADDRESS (CONFIG_SYS_CCSRBAR + 0x82120) 305 306 #undef CONFIG_UEC_ETH 307 #define CONFIG_PHY_MODE_NEED_CHANGE 308 309 #define CONFIG_UEC_ETH1 /* ETH1 */ 310 #define CONFIG_HAS_ETH0 311 312 #ifdef CONFIG_UEC_ETH1 313 #define CONFIG_SYS_UEC1_UCC_NUM 0 /* UCC1 */ 314 #define CONFIG_SYS_UEC1_RX_CLK QE_CLK12 /* CLK12 for MII */ 315 #define CONFIG_SYS_UEC1_TX_CLK QE_CLK9 /* CLK9 for MII */ 316 #define CONFIG_SYS_UEC1_ETH_TYPE FAST_ETH 317 #define CONFIG_SYS_UEC1_PHY_ADDR 0x18 /* 0x18 for MII */ 318 #define CONFIG_SYS_UEC1_INTERFACE_TYPE PHY_INTERFACE_MODE_MII 319 #define CONFIG_SYS_UEC1_INTERFACE_SPEED 100 320 #endif /* CONFIG_UEC_ETH1 */ 321 322 #define CONFIG_UEC_ETH5 /* ETH5 */ 323 #define CONFIG_HAS_ETH1 324 325 #ifdef CONFIG_UEC_ETH5 326 #define CONFIG_SYS_UEC5_UCC_NUM 4 /* UCC5 */ 327 #define CONFIG_SYS_UEC5_RX_CLK QE_CLK_NONE 328 #define CONFIG_SYS_UEC5_TX_CLK QE_CLK13 /* CLK 13 for RMII */ 329 #define CONFIG_SYS_UEC5_ETH_TYPE FAST_ETH 330 #define CONFIG_SYS_UEC5_PHY_ADDR 0x19 /* 0x19 for RMII */ 331 #define CONFIG_SYS_UEC5_INTERFACE_TYPE PHY_INTERFACE_MODE_RMII 332 #define CONFIG_SYS_UEC5_INTERFACE_SPEED 100 333 #endif /* CONFIG_UEC_ETH5 */ 334 #endif /* CONFIG_TWR-P1025 */ 335 336 /* 337 * Dynamic MTD Partition support with mtdparts 338 */ 339 #define CONFIG_MTD_DEVICE 340 #define CONFIG_MTD_PARTITIONS 341 #define CONFIG_FLASH_CFI_MTD 342 343 /* 344 * Environment 345 */ 346 #ifdef CONFIG_SYS_RAMBOOT 347 #ifdef CONFIG_RAMBOOT_SDCARD 348 #define CONFIG_ENV_SIZE 0x2000 349 #define CONFIG_SYS_MMC_ENV_DEV 0 350 #else 351 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) 352 #define CONFIG_ENV_SIZE 0x2000 353 #endif 354 #else 355 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) 356 #define CONFIG_ENV_SIZE 0x2000 357 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ 358 #endif 359 360 #define CONFIG_LOADS_ECHO /* echo on for serial download */ 361 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ 362 363 /* 364 * USB 365 */ 366 #define CONFIG_HAS_FSL_DR_USB 367 368 #if defined(CONFIG_HAS_FSL_DR_USB) 369 #ifdef CONFIG_USB_EHCI_HCD 370 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 371 #define CONFIG_USB_EHCI_FSL 372 #endif 373 #endif 374 375 #ifdef CONFIG_MMC 376 #define CONFIG_FSL_ESDHC 377 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR 378 #endif 379 380 #undef CONFIG_WATCHDOG /* watchdog disabled */ 381 382 /* 383 * Miscellaneous configurable options 384 */ 385 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 386 387 /* 388 * For booting Linux, the board info and command line data 389 * have to be in the first 64 MB of memory, since this is 390 * the maximum mapped by the Linux kernel during initialization. 391 */ 392 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory for Linux*/ 393 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 394 395 /* 396 * Environment Configuration 397 */ 398 #define CONFIG_HOSTNAME unknown 399 #define CONFIG_ROOTPATH "/opt/nfsroot" 400 #define CONFIG_BOOTFILE "uImage" 401 #define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */ 402 403 /* default location for tftp and bootm */ 404 #define CONFIG_LOADADDR 1000000 405 406 #define CONFIG_EXTRA_ENV_SETTINGS \ 407 "netdev=eth0\0" \ 408 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ 409 "loadaddr=1000000\0" \ 410 "bootfile=uImage\0" \ 411 "dtbfile=twr-p1025twr.dtb\0" \ 412 "ramdiskfile=rootfs.ext2.gz.uboot\0" \ 413 "qefirmwarefile=fsl_qe_ucode_1021_10_A.bin\0" \ 414 "tftpflash=tftpboot $loadaddr $uboot; " \ 415 "protect off " __stringify(CONFIG_SYS_TEXT_BASE) " +$filesize; " \ 416 "erase " __stringify(CONFIG_SYS_TEXT_BASE) " +$filesize; " \ 417 "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) " $filesize; " \ 418 "protect on " __stringify(CONFIG_SYS_TEXT_BASE) " +$filesize; " \ 419 "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) " $filesize\0" \ 420 "kernelflash=tftpboot $loadaddr $bootfile; " \ 421 "protect off 0xefa80000 +$filesize; " \ 422 "erase 0xefa80000 +$filesize; " \ 423 "cp.b $loadaddr 0xefa80000 $filesize; " \ 424 "protect on 0xefa80000 +$filesize; " \ 425 "cmp.b $loadaddr 0xefa80000 $filesize\0" \ 426 "dtbflash=tftpboot $loadaddr $dtbfile; " \ 427 "protect off 0xefe80000 +$filesize; " \ 428 "erase 0xefe80000 +$filesize; " \ 429 "cp.b $loadaddr 0xefe80000 $filesize; " \ 430 "protect on 0xefe80000 +$filesize; " \ 431 "cmp.b $loadaddr 0xefe80000 $filesize\0" \ 432 "ramdiskflash=tftpboot $loadaddr $ramdiskfile; " \ 433 "protect off 0xeeb80000 +$filesize; " \ 434 "erase 0xeeb80000 +$filesize; " \ 435 "cp.b $loadaddr 0xeeb80000 $filesize; " \ 436 "protect on 0xeeb80000 +$filesize; " \ 437 "cmp.b $loadaddr 0xeeb80000 $filesize\0" \ 438 "qefirmwareflash=tftpboot $loadaddr $qefirmwarefile; " \ 439 "protect off 0xefec0000 +$filesize; " \ 440 "erase 0xefec0000 +$filesize; " \ 441 "cp.b $loadaddr 0xefec0000 $filesize; " \ 442 "protect on 0xefec0000 +$filesize; " \ 443 "cmp.b $loadaddr 0xefec0000 $filesize\0" \ 444 "consoledev=ttyS0\0" \ 445 "ramdiskaddr=2000000\0" \ 446 "ramdiskfile=rootfs.ext2.gz.uboot\0" \ 447 "fdtaddr=1e00000\0" \ 448 "bdev=sda1\0" \ 449 "norbootaddr=ef080000\0" \ 450 "norfdtaddr=ef040000\0" \ 451 "ramdisk_size=120000\0" \ 452 "usbboot=setenv bootargs root=/dev/sda1 rw rootdelay=5 " \ 453 "console=$consoledev,$baudrate $othbootargs ; bootm 0xefa80000 - 0xefe80000" 454 455 #define CONFIG_NFSBOOTCOMMAND \ 456 "setenv bootargs root=/dev/nfs rw " \ 457 "nfsroot=$serverip:$rootpath " \ 458 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 459 "console=$consoledev,$baudrate $othbootargs;" \ 460 "tftp $loadaddr $bootfile&&" \ 461 "tftp $fdtaddr $fdtfile&&" \ 462 "bootm $loadaddr - $fdtaddr" 463 464 #define CONFIG_HDBOOT \ 465 "setenv bootargs root=/dev/$bdev rw rootdelay=30 " \ 466 "console=$consoledev,$baudrate $othbootargs;" \ 467 "usb start;" \ 468 "ext2load usb 0:1 $loadaddr /boot/$bootfile;" \ 469 "ext2load usb 0:1 $fdtaddr /boot/$fdtfile;" \ 470 "bootm $loadaddr - $fdtaddr" 471 472 #define CONFIG_USB_FAT_BOOT \ 473 "setenv bootargs root=/dev/ram rw " \ 474 "console=$consoledev,$baudrate $othbootargs " \ 475 "ramdisk_size=$ramdisk_size;" \ 476 "usb start;" \ 477 "fatload usb 0:2 $loadaddr $bootfile;" \ 478 "fatload usb 0:2 $fdtaddr $fdtfile;" \ 479 "fatload usb 0:2 $ramdiskaddr $ramdiskfile;" \ 480 "bootm $loadaddr $ramdiskaddr $fdtaddr" 481 482 #define CONFIG_USB_EXT2_BOOT \ 483 "setenv bootargs root=/dev/ram rw " \ 484 "console=$consoledev,$baudrate $othbootargs " \ 485 "ramdisk_size=$ramdisk_size;" \ 486 "usb start;" \ 487 "ext2load usb 0:4 $loadaddr $bootfile;" \ 488 "ext2load usb 0:4 $fdtaddr $fdtfile;" \ 489 "ext2load usb 0:4 $ramdiskaddr $ramdiskfile;" \ 490 "bootm $loadaddr $ramdiskaddr $fdtaddr" 491 492 #define CONFIG_NORBOOT \ 493 "setenv bootargs root=/dev/mtdblock3 rw " \ 494 "console=$consoledev,$baudrate rootfstype=jffs2 $othbootargs;" \ 495 "bootm $norbootaddr - $norfdtaddr" 496 497 #define CONFIG_RAMBOOTCOMMAND_TFTP \ 498 "setenv bootargs root=/dev/ram rw " \ 499 "console=$consoledev,$baudrate $othbootargs " \ 500 "ramdisk_size=$ramdisk_size;" \ 501 "tftp $ramdiskaddr $ramdiskfile;" \ 502 "tftp $loadaddr $bootfile;" \ 503 "tftp $fdtaddr $fdtfile;" \ 504 "bootm $loadaddr $ramdiskaddr $fdtaddr" 505 506 #define CONFIG_RAMBOOTCOMMAND \ 507 "setenv bootargs root=/dev/ram rw " \ 508 "console=$consoledev,$baudrate $othbootargs " \ 509 "ramdisk_size=$ramdisk_size;" \ 510 "bootm 0xefa80000 0xeeb80000 0xefe80000" 511 512 #define CONFIG_BOOTCOMMAND CONFIG_RAMBOOTCOMMAND 513 514 #endif /* __CONFIG_H */ 515