1 /* 2 * Copyright 2013 Freescale Semiconductor, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 /* 8 * QorIQ P1 Tower boards configuration file 9 */ 10 #ifndef __CONFIG_H 11 #define __CONFIG_H 12 13 #if defined(CONFIG_TWR_P1025) 14 #define CONFIG_BOARDNAME "TWR-P1025" 15 #define CONFIG_PHY_ATHEROS 16 #define CONFIG_QE 17 #define CONFIG_SYS_LBC_LBCR 0x00080000 /* Conversion of LBC addr */ 18 #define CONFIG_SYS_LBC_LCRR 0x80000002 /* LB clock ratio reg */ 19 #endif 20 21 #ifdef CONFIG_SDCARD 22 #define CONFIG_RAMBOOT_SDCARD 23 #define CONFIG_SYS_RAMBOOT 24 #define CONFIG_SYS_EXTRA_ENV_RELOC 25 #define CONFIG_SYS_TEXT_BASE 0x11000000 26 #define CONFIG_RESET_VECTOR_ADDRESS 0x110bfffc 27 #endif 28 29 #ifndef CONFIG_SYS_TEXT_BASE 30 #define CONFIG_SYS_TEXT_BASE 0xeff40000 31 #endif 32 33 #ifndef CONFIG_RESET_VECTOR_ADDRESS 34 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc 35 #endif 36 37 #ifndef CONFIG_SYS_MONITOR_BASE 38 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 39 #endif 40 41 #define CONFIG_MP 42 43 #define CONFIG_PCIE1 /* PCIE controller 1 (slot 1) */ 44 #define CONFIG_PCIE2 /* PCIE controller 2 (slot 2) */ 45 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ 46 #define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */ 47 #define CONFIG_FSL_PCIE_RESET /* need PCIe reset errata */ 48 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ 49 50 #define CONFIG_TSEC_ENET /* tsec ethernet support */ 51 #define CONFIG_ENV_OVERWRITE 52 53 #define CONFIG_SYS_SATA_MAX_DEVICE 2 54 #define CONFIG_LBA48 55 56 #ifndef __ASSEMBLY__ 57 extern unsigned long get_board_sys_clk(unsigned long dummy); 58 #endif 59 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk(0) /*sysclk for TWR-P1025 */ 60 61 #define CONFIG_DDR_CLK_FREQ 66666666 62 63 #define CONFIG_HWCONFIG 64 /* 65 * These can be toggled for performance analysis, otherwise use default. 66 */ 67 #define CONFIG_L2_CACHE 68 #define CONFIG_BTB 69 70 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ 71 #define CONFIG_SYS_MEMTEST_END 0x1fffffff 72 73 #define CONFIG_SYS_CCSRBAR 0xffe00000 74 #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR 75 76 /* DDR Setup */ 77 78 #define CONFIG_SYS_SDRAM_SIZE_LAW LAW_SIZE_512M 79 #define CONFIG_CHIP_SELECTS_PER_CTRL 1 80 81 #define CONFIG_SYS_SDRAM_SIZE (1u << (CONFIG_SYS_SDRAM_SIZE_LAW - 19)) 82 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 83 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 84 85 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 86 87 /* Default settings for DDR3 */ 88 #define CONFIG_SYS_DDR_CS0_BNDS 0x0000001f 89 #define CONFIG_SYS_DDR_CS0_CONFIG 0x80014202 90 #define CONFIG_SYS_DDR_CS0_CONFIG_2 0x00000000 91 #define CONFIG_SYS_DDR_CS1_BNDS 0x00000000 92 #define CONFIG_SYS_DDR_CS1_CONFIG 0x00000000 93 #define CONFIG_SYS_DDR_CS1_CONFIG_2 0x00000000 94 95 #define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef 96 #define CONFIG_SYS_DDR_INIT_ADDR 0x00000000 97 #define CONFIG_SYS_DDR_INIT_EXT_ADDR 0x00000000 98 #define CONFIG_SYS_DDR_MODE_CONTROL 0x00000000 99 100 #define CONFIG_SYS_DDR_ZQ_CONTROL 0x89080600 101 #define CONFIG_SYS_DDR_WRLVL_CONTROL 0x8655a608 102 #define CONFIG_SYS_DDR_SR_CNTR 0x00000000 103 #define CONFIG_SYS_DDR_RCW_1 0x00000000 104 #define CONFIG_SYS_DDR_RCW_2 0x00000000 105 #define CONFIG_SYS_DDR_CONTROL 0xc70c0000 /* Type = DDR3 */ 106 #define CONFIG_SYS_DDR_CONTROL_2 0x04401050 107 #define CONFIG_SYS_DDR_TIMING_4 0x00220001 108 #define CONFIG_SYS_DDR_TIMING_5 0x03402400 109 110 #define CONFIG_SYS_DDR_TIMING_3 0x00020000 111 #define CONFIG_SYS_DDR_TIMING_0 0x00220004 112 #define CONFIG_SYS_DDR_TIMING_1 0x5c5b6544 113 #define CONFIG_SYS_DDR_TIMING_2 0x0fa880de 114 #define CONFIG_SYS_DDR_CLK_CTRL 0x03000000 115 #define CONFIG_SYS_DDR_MODE_1 0x80461320 116 #define CONFIG_SYS_DDR_MODE_2 0x00008000 117 #define CONFIG_SYS_DDR_INTERVAL 0x09480000 118 119 /* 120 * Memory map 121 * 122 * 0x0000_0000 0x1fff_ffff DDR Up to 512MB cacheable 123 * 0x8000_0000 0xdfff_ffff PCI Express Mem 1.5G non-cacheable(PCIe * 3) 124 * 0xffc0_0000 0xffc3_ffff PCI IO range 256k non-cacheable 125 * 126 * Localbus 127 * 0xe000_0000 0xe002_0000 SSD1289 128K non-cacheable 128 * 0xec00_0000 0xefff_ffff FLASH Up to 64M non-cacheable 129 * 130 * 0xff90_0000 0xff97_ffff L2 SRAM Up to 512K cacheable 131 * 0xffd0_0000 0xffd0_3fff init ram 16K Cacheable 132 * 0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable 133 */ 134 135 /* 136 * Local Bus Definitions 137 */ 138 #define CONFIG_SYS_MAX_FLASH_SECT 512 /* 64M */ 139 #define CONFIG_SYS_FLASH_BASE 0xec000000 140 141 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE 142 143 #define CONFIG_FLASH_BR_PRELIM (BR_PHYS_ADDR((CONFIG_SYS_FLASH_BASE_PHYS)) \ 144 | BR_PS_16 | BR_V) 145 146 #define CONFIG_FLASH_OR_PRELIM 0xfc0000b1 147 148 #define CONFIG_SYS_SSD_BASE 0xe0000000 149 #define CONFIG_SYS_SSD_BASE_PHYS CONFIG_SYS_SSD_BASE 150 #define CONFIG_SSD_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_SSD_BASE_PHYS) | \ 151 BR_PS_16 | BR_V) 152 #define CONFIG_SSD_OR_PRELIM (OR_AM_64KB | OR_GPCM_CSNT | OR_GPCM_XACS | \ 153 OR_GPCM_ACS_DIV2 | OR_GPCM_SCY | \ 154 OR_GPCM_TRLX | OR_GPCM_EHTR | OR_GPCM_EAD) 155 156 #define CONFIG_SYS_BR2_PRELIM CONFIG_SSD_BR_PRELIM 157 #define CONFIG_SYS_OR2_PRELIM CONFIG_SSD_OR_PRELIM 158 159 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS} 160 #define CONFIG_SYS_FLASH_QUIET_TEST 161 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 162 163 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ 164 165 #undef CONFIG_SYS_FLASH_CHECKSUM 166 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 167 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 168 169 #define CONFIG_FLASH_CFI_DRIVER 170 #define CONFIG_SYS_FLASH_CFI 171 #define CONFIG_SYS_FLASH_EMPTY_INFO 172 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 173 174 #define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */ 175 176 #define CONFIG_SYS_INIT_RAM_LOCK 177 #define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 178 /* Initial L1 address */ 179 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS CONFIG_SYS_INIT_RAM_ADDR 180 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0 181 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS 182 /* Size of used area in RAM */ 183 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 184 185 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ 186 GENERATED_GBL_DATA_SIZE) 187 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 188 189 #define CONFIG_SYS_MONITOR_LEN (768 * 1024) 190 #define CONFIG_SYS_MALLOC_LEN (1024 * 1024)/* Reserved for malloc */ 191 192 #define CONFIG_SYS_BR0_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */ 193 #define CONFIG_SYS_OR0_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */ 194 195 /* Serial Port 196 * open - index 2 197 * shorted - index 1 198 */ 199 #define CONFIG_CONS_INDEX 1 200 #undef CONFIG_SERIAL_SOFTWARE_FIFO 201 #define CONFIG_SYS_NS16550_SERIAL 202 #define CONFIG_SYS_NS16550_REG_SIZE 1 203 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) 204 205 #define CONFIG_SYS_BAUDRATE_TABLE \ 206 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} 207 208 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) 209 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) 210 211 /* I2C */ 212 #define CONFIG_SYS_I2C 213 #define CONFIG_SYS_I2C_FSL /* Use FSL common I2C driver */ 214 #define CONFIG_SYS_FSL_I2C_SPEED 400000 /* I2C spd and slave address */ 215 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 216 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 217 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x52 218 219 /* 220 * I2C2 EEPROM 221 */ 222 #define CONFIG_SYS_FSL_I2C2_SPEED 400000 /* I2C spd and slave address */ 223 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F 224 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100 225 226 #define CONFIG_SYS_I2C_PCA9555_ADDR 0x23 227 228 /* enable read and write access to EEPROM */ 229 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 230 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 231 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 232 233 /* 234 * eSPI - Enhanced SPI 235 */ 236 #define CONFIG_HARD_SPI 237 238 #if defined(CONFIG_PCI) 239 /* 240 * General PCI 241 * Memory space is mapped 1-1, but I/O space must start from 0. 242 */ 243 244 /* controller 2, direct to uli, tgtid 2, Base address 9000 */ 245 #define CONFIG_SYS_PCIE2_NAME "TWR-ELEV PCIe SLOT" 246 #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000 247 #define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000 248 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000 249 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */ 250 #define CONFIG_SYS_PCIE2_IO_VIRT 0xffc10000 251 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 252 #define CONFIG_SYS_PCIE2_IO_PHYS 0xffc10000 253 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ 254 255 /* controller 1, tgtid 1, Base address a000 */ 256 #define CONFIG_SYS_PCIE1_NAME "mini PCIe SLOT" 257 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 258 #define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000 259 #define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000 260 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ 261 #define CONFIG_SYS_PCIE1_IO_VIRT 0xffc00000 262 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 263 #define CONFIG_SYS_PCIE1_IO_PHYS 0xffc00000 264 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ 265 266 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 267 #endif /* CONFIG_PCI */ 268 269 #if defined(CONFIG_TSEC_ENET) 270 271 #define CONFIG_MII /* MII PHY management */ 272 #define CONFIG_TSEC1 273 #define CONFIG_TSEC1_NAME "eTSEC1" 274 #undef CONFIG_TSEC2 275 #undef CONFIG_TSEC2_NAME 276 #define CONFIG_TSEC3 277 #define CONFIG_TSEC3_NAME "eTSEC3" 278 279 #define TSEC1_PHY_ADDR 2 280 #define TSEC2_PHY_ADDR 0 281 #define TSEC3_PHY_ADDR 1 282 283 #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 284 #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 285 #define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 286 287 #define TSEC1_PHYIDX 0 288 #define TSEC2_PHYIDX 0 289 #define TSEC3_PHYIDX 0 290 291 #define CONFIG_ETHPRIME "eTSEC1" 292 293 #define CONFIG_HAS_ETH0 294 #define CONFIG_HAS_ETH1 295 #undef CONFIG_HAS_ETH2 296 #endif /* CONFIG_TSEC_ENET */ 297 298 #ifdef CONFIG_QE 299 /* QE microcode/firmware address */ 300 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR 301 #define CONFIG_SYS_QE_FW_ADDR 0xefec0000 302 #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 303 #endif /* CONFIG_QE */ 304 305 #ifdef CONFIG_TWR_P1025 306 /* 307 * QE UEC ethernet configuration 308 */ 309 #define CONFIG_MIIM_ADDRESS (CONFIG_SYS_CCSRBAR + 0x82120) 310 311 #undef CONFIG_UEC_ETH 312 #define CONFIG_PHY_MODE_NEED_CHANGE 313 314 #define CONFIG_UEC_ETH1 /* ETH1 */ 315 #define CONFIG_HAS_ETH0 316 317 #ifdef CONFIG_UEC_ETH1 318 #define CONFIG_SYS_UEC1_UCC_NUM 0 /* UCC1 */ 319 #define CONFIG_SYS_UEC1_RX_CLK QE_CLK12 /* CLK12 for MII */ 320 #define CONFIG_SYS_UEC1_TX_CLK QE_CLK9 /* CLK9 for MII */ 321 #define CONFIG_SYS_UEC1_ETH_TYPE FAST_ETH 322 #define CONFIG_SYS_UEC1_PHY_ADDR 0x18 /* 0x18 for MII */ 323 #define CONFIG_SYS_UEC1_INTERFACE_TYPE PHY_INTERFACE_MODE_MII 324 #define CONFIG_SYS_UEC1_INTERFACE_SPEED 100 325 #endif /* CONFIG_UEC_ETH1 */ 326 327 #define CONFIG_UEC_ETH5 /* ETH5 */ 328 #define CONFIG_HAS_ETH1 329 330 #ifdef CONFIG_UEC_ETH5 331 #define CONFIG_SYS_UEC5_UCC_NUM 4 /* UCC5 */ 332 #define CONFIG_SYS_UEC5_RX_CLK QE_CLK_NONE 333 #define CONFIG_SYS_UEC5_TX_CLK QE_CLK13 /* CLK 13 for RMII */ 334 #define CONFIG_SYS_UEC5_ETH_TYPE FAST_ETH 335 #define CONFIG_SYS_UEC5_PHY_ADDR 0x19 /* 0x19 for RMII */ 336 #define CONFIG_SYS_UEC5_INTERFACE_TYPE PHY_INTERFACE_MODE_RMII 337 #define CONFIG_SYS_UEC5_INTERFACE_SPEED 100 338 #endif /* CONFIG_UEC_ETH5 */ 339 #endif /* CONFIG_TWR-P1025 */ 340 341 /* 342 * Dynamic MTD Partition support with mtdparts 343 */ 344 #define CONFIG_MTD_DEVICE 345 #define CONFIG_MTD_PARTITIONS 346 #define CONFIG_FLASH_CFI_MTD 347 348 /* 349 * Environment 350 */ 351 #ifdef CONFIG_SYS_RAMBOOT 352 #ifdef CONFIG_RAMBOOT_SDCARD 353 #define CONFIG_ENV_SIZE 0x2000 354 #define CONFIG_SYS_MMC_ENV_DEV 0 355 #else 356 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) 357 #define CONFIG_ENV_SIZE 0x2000 358 #endif 359 #else 360 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) 361 #define CONFIG_ENV_SIZE 0x2000 362 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ 363 #endif 364 365 #define CONFIG_LOADS_ECHO /* echo on for serial download */ 366 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ 367 368 /* 369 * USB 370 */ 371 #define CONFIG_HAS_FSL_DR_USB 372 373 #if defined(CONFIG_HAS_FSL_DR_USB) 374 #ifdef CONFIG_USB_EHCI_HCD 375 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 376 #define CONFIG_USB_EHCI_FSL 377 #endif 378 #endif 379 380 #ifdef CONFIG_MMC 381 #define CONFIG_FSL_ESDHC 382 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR 383 #endif 384 385 #undef CONFIG_WATCHDOG /* watchdog disabled */ 386 387 /* 388 * Miscellaneous configurable options 389 */ 390 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 391 #define CONFIG_CMDLINE_EDITING /* Command-line editing */ 392 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 393 394 /* 395 * For booting Linux, the board info and command line data 396 * have to be in the first 64 MB of memory, since this is 397 * the maximum mapped by the Linux kernel during initialization. 398 */ 399 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory for Linux*/ 400 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 401 402 /* 403 * Environment Configuration 404 */ 405 #define CONFIG_HOSTNAME unknown 406 #define CONFIG_ROOTPATH "/opt/nfsroot" 407 #define CONFIG_BOOTFILE "uImage" 408 #define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */ 409 410 /* default location for tftp and bootm */ 411 #define CONFIG_LOADADDR 1000000 412 413 #define CONFIG_EXTRA_ENV_SETTINGS \ 414 "netdev=eth0\0" \ 415 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ 416 "loadaddr=1000000\0" \ 417 "bootfile=uImage\0" \ 418 "dtbfile=twr-p1025twr.dtb\0" \ 419 "ramdiskfile=rootfs.ext2.gz.uboot\0" \ 420 "qefirmwarefile=fsl_qe_ucode_1021_10_A.bin\0" \ 421 "tftpflash=tftpboot $loadaddr $uboot; " \ 422 "protect off " __stringify(CONFIG_SYS_TEXT_BASE) " +$filesize; " \ 423 "erase " __stringify(CONFIG_SYS_TEXT_BASE) " +$filesize; " \ 424 "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) " $filesize; " \ 425 "protect on " __stringify(CONFIG_SYS_TEXT_BASE) " +$filesize; " \ 426 "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) " $filesize\0" \ 427 "kernelflash=tftpboot $loadaddr $bootfile; " \ 428 "protect off 0xefa80000 +$filesize; " \ 429 "erase 0xefa80000 +$filesize; " \ 430 "cp.b $loadaddr 0xefa80000 $filesize; " \ 431 "protect on 0xefa80000 +$filesize; " \ 432 "cmp.b $loadaddr 0xefa80000 $filesize\0" \ 433 "dtbflash=tftpboot $loadaddr $dtbfile; " \ 434 "protect off 0xefe80000 +$filesize; " \ 435 "erase 0xefe80000 +$filesize; " \ 436 "cp.b $loadaddr 0xefe80000 $filesize; " \ 437 "protect on 0xefe80000 +$filesize; " \ 438 "cmp.b $loadaddr 0xefe80000 $filesize\0" \ 439 "ramdiskflash=tftpboot $loadaddr $ramdiskfile; " \ 440 "protect off 0xeeb80000 +$filesize; " \ 441 "erase 0xeeb80000 +$filesize; " \ 442 "cp.b $loadaddr 0xeeb80000 $filesize; " \ 443 "protect on 0xeeb80000 +$filesize; " \ 444 "cmp.b $loadaddr 0xeeb80000 $filesize\0" \ 445 "qefirmwareflash=tftpboot $loadaddr $qefirmwarefile; " \ 446 "protect off 0xefec0000 +$filesize; " \ 447 "erase 0xefec0000 +$filesize; " \ 448 "cp.b $loadaddr 0xefec0000 $filesize; " \ 449 "protect on 0xefec0000 +$filesize; " \ 450 "cmp.b $loadaddr 0xefec0000 $filesize\0" \ 451 "consoledev=ttyS0\0" \ 452 "ramdiskaddr=2000000\0" \ 453 "ramdiskfile=rootfs.ext2.gz.uboot\0" \ 454 "fdtaddr=1e00000\0" \ 455 "bdev=sda1\0" \ 456 "norbootaddr=ef080000\0" \ 457 "norfdtaddr=ef040000\0" \ 458 "ramdisk_size=120000\0" \ 459 "usbboot=setenv bootargs root=/dev/sda1 rw rootdelay=5 " \ 460 "console=$consoledev,$baudrate $othbootargs ; bootm 0xefa80000 - 0xefe80000" 461 462 #define CONFIG_NFSBOOTCOMMAND \ 463 "setenv bootargs root=/dev/nfs rw " \ 464 "nfsroot=$serverip:$rootpath " \ 465 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 466 "console=$consoledev,$baudrate $othbootargs;" \ 467 "tftp $loadaddr $bootfile&&" \ 468 "tftp $fdtaddr $fdtfile&&" \ 469 "bootm $loadaddr - $fdtaddr" 470 471 #define CONFIG_HDBOOT \ 472 "setenv bootargs root=/dev/$bdev rw rootdelay=30 " \ 473 "console=$consoledev,$baudrate $othbootargs;" \ 474 "usb start;" \ 475 "ext2load usb 0:1 $loadaddr /boot/$bootfile;" \ 476 "ext2load usb 0:1 $fdtaddr /boot/$fdtfile;" \ 477 "bootm $loadaddr - $fdtaddr" 478 479 #define CONFIG_USB_FAT_BOOT \ 480 "setenv bootargs root=/dev/ram rw " \ 481 "console=$consoledev,$baudrate $othbootargs " \ 482 "ramdisk_size=$ramdisk_size;" \ 483 "usb start;" \ 484 "fatload usb 0:2 $loadaddr $bootfile;" \ 485 "fatload usb 0:2 $fdtaddr $fdtfile;" \ 486 "fatload usb 0:2 $ramdiskaddr $ramdiskfile;" \ 487 "bootm $loadaddr $ramdiskaddr $fdtaddr" 488 489 #define CONFIG_USB_EXT2_BOOT \ 490 "setenv bootargs root=/dev/ram rw " \ 491 "console=$consoledev,$baudrate $othbootargs " \ 492 "ramdisk_size=$ramdisk_size;" \ 493 "usb start;" \ 494 "ext2load usb 0:4 $loadaddr $bootfile;" \ 495 "ext2load usb 0:4 $fdtaddr $fdtfile;" \ 496 "ext2load usb 0:4 $ramdiskaddr $ramdiskfile;" \ 497 "bootm $loadaddr $ramdiskaddr $fdtaddr" 498 499 #define CONFIG_NORBOOT \ 500 "setenv bootargs root=/dev/mtdblock3 rw " \ 501 "console=$consoledev,$baudrate rootfstype=jffs2 $othbootargs;" \ 502 "bootm $norbootaddr - $norfdtaddr" 503 504 #define CONFIG_RAMBOOTCOMMAND_TFTP \ 505 "setenv bootargs root=/dev/ram rw " \ 506 "console=$consoledev,$baudrate $othbootargs " \ 507 "ramdisk_size=$ramdisk_size;" \ 508 "tftp $ramdiskaddr $ramdiskfile;" \ 509 "tftp $loadaddr $bootfile;" \ 510 "tftp $fdtaddr $fdtfile;" \ 511 "bootm $loadaddr $ramdiskaddr $fdtaddr" 512 513 #define CONFIG_RAMBOOTCOMMAND \ 514 "setenv bootargs root=/dev/ram rw " \ 515 "console=$consoledev,$baudrate $othbootargs " \ 516 "ramdisk_size=$ramdisk_size;" \ 517 "bootm 0xefa80000 0xeeb80000 0xefe80000" 518 519 #define CONFIG_BOOTCOMMAND CONFIG_RAMBOOTCOMMAND 520 521 #endif /* __CONFIG_H */ 522