1 /* 2 * Copyright 2013 Freescale Semiconductor, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 /* 8 * QorIQ P1 Tower boards configuration file 9 */ 10 #ifndef __CONFIG_H 11 #define __CONFIG_H 12 13 #if defined(CONFIG_TWR_P1025) 14 #define CONFIG_BOARDNAME "TWR-P1025" 15 #define CONFIG_PHY_ATHEROS 16 #define CONFIG_QE 17 #define CONFIG_SYS_LBC_LBCR 0x00080000 /* Conversion of LBC addr */ 18 #define CONFIG_SYS_LBC_LCRR 0x80000002 /* LB clock ratio reg */ 19 #endif 20 21 #ifdef CONFIG_SDCARD 22 #define CONFIG_RAMBOOT_SDCARD 23 #define CONFIG_SYS_RAMBOOT 24 #define CONFIG_SYS_EXTRA_ENV_RELOC 25 #define CONFIG_SYS_TEXT_BASE 0x11000000 26 #define CONFIG_RESET_VECTOR_ADDRESS 0x110bfffc 27 #endif 28 29 #ifndef CONFIG_SYS_TEXT_BASE 30 #define CONFIG_SYS_TEXT_BASE 0xeff40000 31 #endif 32 33 #ifndef CONFIG_RESET_VECTOR_ADDRESS 34 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc 35 #endif 36 37 #ifndef CONFIG_SYS_MONITOR_BASE 38 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 39 #endif 40 41 #define CONFIG_MP 42 43 #define CONFIG_PCIE1 /* PCIE controller 1 (slot 1) */ 44 #define CONFIG_PCIE2 /* PCIE controller 2 (slot 2) */ 45 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ 46 #define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */ 47 #define CONFIG_FSL_PCIE_RESET /* need PCIe reset errata */ 48 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ 49 50 #define CONFIG_TSEC_ENET /* tsec ethernet support */ 51 #define CONFIG_ENV_OVERWRITE 52 53 #define CONFIG_CMD_SATA 54 #define CONFIG_SATA_SIL3114 55 #define CONFIG_SYS_SATA_MAX_DEVICE 2 56 #define CONFIG_LIBATA 57 #define CONFIG_LBA48 58 59 #ifndef __ASSEMBLY__ 60 extern unsigned long get_board_sys_clk(unsigned long dummy); 61 #endif 62 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk(0) /*sysclk for TWR-P1025 */ 63 64 #define CONFIG_DDR_CLK_FREQ 66666666 65 66 #define CONFIG_HWCONFIG 67 /* 68 * These can be toggled for performance analysis, otherwise use default. 69 */ 70 #define CONFIG_L2_CACHE 71 #define CONFIG_BTB 72 73 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ 74 #define CONFIG_SYS_MEMTEST_END 0x1fffffff 75 #define CONFIG_PANIC_HANG /* do not reset board on panic */ 76 77 #define CONFIG_SYS_CCSRBAR 0xffe00000 78 #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR 79 80 /* DDR Setup */ 81 82 #define CONFIG_SYS_SDRAM_SIZE_LAW LAW_SIZE_512M 83 #define CONFIG_CHIP_SELECTS_PER_CTRL 1 84 85 #define CONFIG_SYS_SDRAM_SIZE (1u << (CONFIG_SYS_SDRAM_SIZE_LAW - 19)) 86 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 87 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 88 89 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 90 91 /* Default settings for DDR3 */ 92 #define CONFIG_SYS_DDR_CS0_BNDS 0x0000001f 93 #define CONFIG_SYS_DDR_CS0_CONFIG 0x80014202 94 #define CONFIG_SYS_DDR_CS0_CONFIG_2 0x00000000 95 #define CONFIG_SYS_DDR_CS1_BNDS 0x00000000 96 #define CONFIG_SYS_DDR_CS1_CONFIG 0x00000000 97 #define CONFIG_SYS_DDR_CS1_CONFIG_2 0x00000000 98 99 #define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef 100 #define CONFIG_SYS_DDR_INIT_ADDR 0x00000000 101 #define CONFIG_SYS_DDR_INIT_EXT_ADDR 0x00000000 102 #define CONFIG_SYS_DDR_MODE_CONTROL 0x00000000 103 104 #define CONFIG_SYS_DDR_ZQ_CONTROL 0x89080600 105 #define CONFIG_SYS_DDR_WRLVL_CONTROL 0x8655a608 106 #define CONFIG_SYS_DDR_SR_CNTR 0x00000000 107 #define CONFIG_SYS_DDR_RCW_1 0x00000000 108 #define CONFIG_SYS_DDR_RCW_2 0x00000000 109 #define CONFIG_SYS_DDR_CONTROL 0xc70c0000 /* Type = DDR3 */ 110 #define CONFIG_SYS_DDR_CONTROL_2 0x04401050 111 #define CONFIG_SYS_DDR_TIMING_4 0x00220001 112 #define CONFIG_SYS_DDR_TIMING_5 0x03402400 113 114 #define CONFIG_SYS_DDR_TIMING_3 0x00020000 115 #define CONFIG_SYS_DDR_TIMING_0 0x00220004 116 #define CONFIG_SYS_DDR_TIMING_1 0x5c5b6544 117 #define CONFIG_SYS_DDR_TIMING_2 0x0fa880de 118 #define CONFIG_SYS_DDR_CLK_CTRL 0x03000000 119 #define CONFIG_SYS_DDR_MODE_1 0x80461320 120 #define CONFIG_SYS_DDR_MODE_2 0x00008000 121 #define CONFIG_SYS_DDR_INTERVAL 0x09480000 122 123 /* 124 * Memory map 125 * 126 * 0x0000_0000 0x1fff_ffff DDR Up to 512MB cacheable 127 * 0x8000_0000 0xdfff_ffff PCI Express Mem 1.5G non-cacheable(PCIe * 3) 128 * 0xffc0_0000 0xffc3_ffff PCI IO range 256k non-cacheable 129 * 130 * Localbus 131 * 0xe000_0000 0xe002_0000 SSD1289 128K non-cacheable 132 * 0xec00_0000 0xefff_ffff FLASH Up to 64M non-cacheable 133 * 134 * 0xff90_0000 0xff97_ffff L2 SRAM Up to 512K cacheable 135 * 0xffd0_0000 0xffd0_3fff init ram 16K Cacheable 136 * 0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable 137 */ 138 139 /* 140 * Local Bus Definitions 141 */ 142 #define CONFIG_SYS_MAX_FLASH_SECT 512 /* 64M */ 143 #define CONFIG_SYS_FLASH_BASE 0xec000000 144 145 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE 146 147 #define CONFIG_FLASH_BR_PRELIM (BR_PHYS_ADDR((CONFIG_SYS_FLASH_BASE_PHYS)) \ 148 | BR_PS_16 | BR_V) 149 150 #define CONFIG_FLASH_OR_PRELIM 0xfc0000b1 151 152 #define CONFIG_SYS_SSD_BASE 0xe0000000 153 #define CONFIG_SYS_SSD_BASE_PHYS CONFIG_SYS_SSD_BASE 154 #define CONFIG_SSD_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_SSD_BASE_PHYS) | \ 155 BR_PS_16 | BR_V) 156 #define CONFIG_SSD_OR_PRELIM (OR_AM_64KB | OR_GPCM_CSNT | OR_GPCM_XACS | \ 157 OR_GPCM_ACS_DIV2 | OR_GPCM_SCY | \ 158 OR_GPCM_TRLX | OR_GPCM_EHTR | OR_GPCM_EAD) 159 160 #define CONFIG_SYS_BR2_PRELIM CONFIG_SSD_BR_PRELIM 161 #define CONFIG_SYS_OR2_PRELIM CONFIG_SSD_OR_PRELIM 162 163 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS} 164 #define CONFIG_SYS_FLASH_QUIET_TEST 165 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 166 167 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ 168 169 #undef CONFIG_SYS_FLASH_CHECKSUM 170 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 171 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 172 173 #define CONFIG_FLASH_CFI_DRIVER 174 #define CONFIG_SYS_FLASH_CFI 175 #define CONFIG_SYS_FLASH_EMPTY_INFO 176 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 177 178 #define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */ 179 180 #define CONFIG_SYS_INIT_RAM_LOCK 181 #define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 182 /* Initial L1 address */ 183 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS CONFIG_SYS_INIT_RAM_ADDR 184 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0 185 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS 186 /* Size of used area in RAM */ 187 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 188 189 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ 190 GENERATED_GBL_DATA_SIZE) 191 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 192 193 #define CONFIG_SYS_MONITOR_LEN (768 * 1024) 194 #define CONFIG_SYS_MALLOC_LEN (1024 * 1024)/* Reserved for malloc */ 195 196 #define CONFIG_SYS_BR0_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */ 197 #define CONFIG_SYS_OR0_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */ 198 199 /* Serial Port 200 * open - index 2 201 * shorted - index 1 202 */ 203 #define CONFIG_CONS_INDEX 1 204 #undef CONFIG_SERIAL_SOFTWARE_FIFO 205 #define CONFIG_SYS_NS16550_SERIAL 206 #define CONFIG_SYS_NS16550_REG_SIZE 1 207 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) 208 209 #define CONFIG_SYS_BAUDRATE_TABLE \ 210 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} 211 212 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) 213 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) 214 215 /* I2C */ 216 #define CONFIG_SYS_I2C 217 #define CONFIG_SYS_I2C_FSL /* Use FSL common I2C driver */ 218 #define CONFIG_SYS_FSL_I2C_SPEED 400000 /* I2C spd and slave address */ 219 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 220 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 221 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x52 222 223 /* 224 * I2C2 EEPROM 225 */ 226 #define CONFIG_SYS_FSL_I2C2_SPEED 400000 /* I2C spd and slave address */ 227 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F 228 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100 229 230 #define CONFIG_SYS_I2C_PCA9555_ADDR 0x23 231 232 /* enable read and write access to EEPROM */ 233 #define CONFIG_CMD_EEPROM 234 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 235 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 236 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 237 238 /* 239 * eSPI - Enhanced SPI 240 */ 241 #define CONFIG_HARD_SPI 242 243 #if defined(CONFIG_PCI) 244 /* 245 * General PCI 246 * Memory space is mapped 1-1, but I/O space must start from 0. 247 */ 248 249 /* controller 2, direct to uli, tgtid 2, Base address 9000 */ 250 #define CONFIG_SYS_PCIE2_NAME "TWR-ELEV PCIe SLOT" 251 #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000 252 #define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000 253 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000 254 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */ 255 #define CONFIG_SYS_PCIE2_IO_VIRT 0xffc10000 256 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 257 #define CONFIG_SYS_PCIE2_IO_PHYS 0xffc10000 258 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ 259 260 /* controller 1, tgtid 1, Base address a000 */ 261 #define CONFIG_SYS_PCIE1_NAME "mini PCIe SLOT" 262 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 263 #define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000 264 #define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000 265 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ 266 #define CONFIG_SYS_PCIE1_IO_VIRT 0xffc00000 267 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 268 #define CONFIG_SYS_PCIE1_IO_PHYS 0xffc00000 269 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ 270 271 #define CONFIG_CMD_PCI 272 273 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 274 #endif /* CONFIG_PCI */ 275 276 #if defined(CONFIG_TSEC_ENET) 277 278 #define CONFIG_MII /* MII PHY management */ 279 #define CONFIG_TSEC1 280 #define CONFIG_TSEC1_NAME "eTSEC1" 281 #undef CONFIG_TSEC2 282 #undef CONFIG_TSEC2_NAME 283 #define CONFIG_TSEC3 284 #define CONFIG_TSEC3_NAME "eTSEC3" 285 286 #define TSEC1_PHY_ADDR 2 287 #define TSEC2_PHY_ADDR 0 288 #define TSEC3_PHY_ADDR 1 289 290 #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 291 #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 292 #define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 293 294 #define TSEC1_PHYIDX 0 295 #define TSEC2_PHYIDX 0 296 #define TSEC3_PHYIDX 0 297 298 #define CONFIG_ETHPRIME "eTSEC1" 299 300 #define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */ 301 302 #define CONFIG_HAS_ETH0 303 #define CONFIG_HAS_ETH1 304 #undef CONFIG_HAS_ETH2 305 #endif /* CONFIG_TSEC_ENET */ 306 307 #ifdef CONFIG_QE 308 /* QE microcode/firmware address */ 309 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR 310 #define CONFIG_SYS_QE_FW_ADDR 0xefec0000 311 #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 312 #endif /* CONFIG_QE */ 313 314 #ifdef CONFIG_TWR_P1025 315 /* 316 * QE UEC ethernet configuration 317 */ 318 #define CONFIG_MIIM_ADDRESS (CONFIG_SYS_CCSRBAR + 0x82120) 319 320 #undef CONFIG_UEC_ETH 321 #define CONFIG_PHY_MODE_NEED_CHANGE 322 323 #define CONFIG_UEC_ETH1 /* ETH1 */ 324 #define CONFIG_HAS_ETH0 325 326 #ifdef CONFIG_UEC_ETH1 327 #define CONFIG_SYS_UEC1_UCC_NUM 0 /* UCC1 */ 328 #define CONFIG_SYS_UEC1_RX_CLK QE_CLK12 /* CLK12 for MII */ 329 #define CONFIG_SYS_UEC1_TX_CLK QE_CLK9 /* CLK9 for MII */ 330 #define CONFIG_SYS_UEC1_ETH_TYPE FAST_ETH 331 #define CONFIG_SYS_UEC1_PHY_ADDR 0x18 /* 0x18 for MII */ 332 #define CONFIG_SYS_UEC1_INTERFACE_TYPE PHY_INTERFACE_MODE_MII 333 #define CONFIG_SYS_UEC1_INTERFACE_SPEED 100 334 #endif /* CONFIG_UEC_ETH1 */ 335 336 #define CONFIG_UEC_ETH5 /* ETH5 */ 337 #define CONFIG_HAS_ETH1 338 339 #ifdef CONFIG_UEC_ETH5 340 #define CONFIG_SYS_UEC5_UCC_NUM 4 /* UCC5 */ 341 #define CONFIG_SYS_UEC5_RX_CLK QE_CLK_NONE 342 #define CONFIG_SYS_UEC5_TX_CLK QE_CLK13 /* CLK 13 for RMII */ 343 #define CONFIG_SYS_UEC5_ETH_TYPE FAST_ETH 344 #define CONFIG_SYS_UEC5_PHY_ADDR 0x19 /* 0x19 for RMII */ 345 #define CONFIG_SYS_UEC5_INTERFACE_TYPE PHY_INTERFACE_MODE_RMII 346 #define CONFIG_SYS_UEC5_INTERFACE_SPEED 100 347 #endif /* CONFIG_UEC_ETH5 */ 348 #endif /* CONFIG_TWR-P1025 */ 349 350 /* 351 * Dynamic MTD Partition support with mtdparts 352 */ 353 #define CONFIG_MTD_DEVICE 354 #define CONFIG_MTD_PARTITIONS 355 #define CONFIG_CMD_MTDPARTS 356 #define CONFIG_FLASH_CFI_MTD 357 #define MTDIDS_DEFAULT "nor0=ec000000.nor" 358 #define MTDPARTS_DEFAULT "mtdparts=ec000000.nor:256k(vsc7385-firmware)," \ 359 "256k(dtb),5632k(kernel),57856k(fs)," \ 360 "256k(qe-ucode-firmware),1280k(u-boot)" 361 362 /* 363 * Environment 364 */ 365 #ifdef CONFIG_SYS_RAMBOOT 366 #ifdef CONFIG_RAMBOOT_SDCARD 367 #define CONFIG_ENV_IS_IN_MMC 368 #define CONFIG_ENV_SIZE 0x2000 369 #define CONFIG_SYS_MMC_ENV_DEV 0 370 #else 371 #define CONFIG_ENV_IS_NOWHERE /* Store ENV in memory only */ 372 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) 373 #define CONFIG_ENV_SIZE 0x2000 374 #endif 375 #else 376 #define CONFIG_ENV_IS_IN_FLASH 377 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) 378 #define CONFIG_ENV_SIZE 0x2000 379 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ 380 #endif 381 382 #define CONFIG_LOADS_ECHO /* echo on for serial download */ 383 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ 384 385 /* 386 * Command line configuration. 387 */ 388 #define CONFIG_CMD_IRQ 389 #define CONFIG_CMD_REGINFO 390 391 /* 392 * USB 393 */ 394 #define CONFIG_HAS_FSL_DR_USB 395 396 #if defined(CONFIG_HAS_FSL_DR_USB) 397 #define CONFIG_USB_EHCI 398 399 #ifdef CONFIG_USB_EHCI 400 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 401 #define CONFIG_USB_EHCI_FSL 402 #endif 403 #endif 404 405 #ifdef CONFIG_MMC 406 #define CONFIG_FSL_ESDHC 407 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR 408 #endif 409 410 #undef CONFIG_WATCHDOG /* watchdog disabled */ 411 412 /* 413 * Miscellaneous configurable options 414 */ 415 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 416 #define CONFIG_CMDLINE_EDITING /* Command-line editing */ 417 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 418 #if defined(CONFIG_CMD_KGDB) 419 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 420 #else 421 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 422 #endif 423 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) 424 /* Print Buffer Size */ 425 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 426 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */ 427 428 /* 429 * For booting Linux, the board info and command line data 430 * have to be in the first 64 MB of memory, since this is 431 * the maximum mapped by the Linux kernel during initialization. 432 */ 433 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory for Linux*/ 434 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 435 436 /* 437 * Environment Configuration 438 */ 439 #define CONFIG_HOSTNAME unknown 440 #define CONFIG_ROOTPATH "/opt/nfsroot" 441 #define CONFIG_BOOTFILE "uImage" 442 #define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */ 443 444 /* default location for tftp and bootm */ 445 #define CONFIG_LOADADDR 1000000 446 447 #define CONFIG_BOOTARGS /* the boot command will set bootargs */ 448 449 #define CONFIG_EXTRA_ENV_SETTINGS \ 450 "netdev=eth0\0" \ 451 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ 452 "loadaddr=1000000\0" \ 453 "bootfile=uImage\0" \ 454 "dtbfile=twr-p1025twr.dtb\0" \ 455 "ramdiskfile=rootfs.ext2.gz.uboot\0" \ 456 "qefirmwarefile=fsl_qe_ucode_1021_10_A.bin\0" \ 457 "tftpflash=tftpboot $loadaddr $uboot; " \ 458 "protect off " __stringify(CONFIG_SYS_TEXT_BASE) " +$filesize; " \ 459 "erase " __stringify(CONFIG_SYS_TEXT_BASE) " +$filesize; " \ 460 "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) " $filesize; " \ 461 "protect on " __stringify(CONFIG_SYS_TEXT_BASE) " +$filesize; " \ 462 "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) " $filesize\0" \ 463 "kernelflash=tftpboot $loadaddr $bootfile; " \ 464 "protect off 0xefa80000 +$filesize; " \ 465 "erase 0xefa80000 +$filesize; " \ 466 "cp.b $loadaddr 0xefa80000 $filesize; " \ 467 "protect on 0xefa80000 +$filesize; " \ 468 "cmp.b $loadaddr 0xefa80000 $filesize\0" \ 469 "dtbflash=tftpboot $loadaddr $dtbfile; " \ 470 "protect off 0xefe80000 +$filesize; " \ 471 "erase 0xefe80000 +$filesize; " \ 472 "cp.b $loadaddr 0xefe80000 $filesize; " \ 473 "protect on 0xefe80000 +$filesize; " \ 474 "cmp.b $loadaddr 0xefe80000 $filesize\0" \ 475 "ramdiskflash=tftpboot $loadaddr $ramdiskfile; " \ 476 "protect off 0xeeb80000 +$filesize; " \ 477 "erase 0xeeb80000 +$filesize; " \ 478 "cp.b $loadaddr 0xeeb80000 $filesize; " \ 479 "protect on 0xeeb80000 +$filesize; " \ 480 "cmp.b $loadaddr 0xeeb80000 $filesize\0" \ 481 "qefirmwareflash=tftpboot $loadaddr $qefirmwarefile; " \ 482 "protect off 0xefec0000 +$filesize; " \ 483 "erase 0xefec0000 +$filesize; " \ 484 "cp.b $loadaddr 0xefec0000 $filesize; " \ 485 "protect on 0xefec0000 +$filesize; " \ 486 "cmp.b $loadaddr 0xefec0000 $filesize\0" \ 487 "consoledev=ttyS0\0" \ 488 "ramdiskaddr=2000000\0" \ 489 "ramdiskfile=rootfs.ext2.gz.uboot\0" \ 490 "fdtaddr=1e00000\0" \ 491 "bdev=sda1\0" \ 492 "norbootaddr=ef080000\0" \ 493 "norfdtaddr=ef040000\0" \ 494 "ramdisk_size=120000\0" \ 495 "usbboot=setenv bootargs root=/dev/sda1 rw rootdelay=5 " \ 496 "console=$consoledev,$baudrate $othbootargs ; bootm 0xefa80000 - 0xefe80000" 497 498 #define CONFIG_NFSBOOTCOMMAND \ 499 "setenv bootargs root=/dev/nfs rw " \ 500 "nfsroot=$serverip:$rootpath " \ 501 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 502 "console=$consoledev,$baudrate $othbootargs;" \ 503 "tftp $loadaddr $bootfile&&" \ 504 "tftp $fdtaddr $fdtfile&&" \ 505 "bootm $loadaddr - $fdtaddr" 506 507 #define CONFIG_HDBOOT \ 508 "setenv bootargs root=/dev/$bdev rw rootdelay=30 " \ 509 "console=$consoledev,$baudrate $othbootargs;" \ 510 "usb start;" \ 511 "ext2load usb 0:1 $loadaddr /boot/$bootfile;" \ 512 "ext2load usb 0:1 $fdtaddr /boot/$fdtfile;" \ 513 "bootm $loadaddr - $fdtaddr" 514 515 #define CONFIG_USB_FAT_BOOT \ 516 "setenv bootargs root=/dev/ram rw " \ 517 "console=$consoledev,$baudrate $othbootargs " \ 518 "ramdisk_size=$ramdisk_size;" \ 519 "usb start;" \ 520 "fatload usb 0:2 $loadaddr $bootfile;" \ 521 "fatload usb 0:2 $fdtaddr $fdtfile;" \ 522 "fatload usb 0:2 $ramdiskaddr $ramdiskfile;" \ 523 "bootm $loadaddr $ramdiskaddr $fdtaddr" 524 525 #define CONFIG_USB_EXT2_BOOT \ 526 "setenv bootargs root=/dev/ram rw " \ 527 "console=$consoledev,$baudrate $othbootargs " \ 528 "ramdisk_size=$ramdisk_size;" \ 529 "usb start;" \ 530 "ext2load usb 0:4 $loadaddr $bootfile;" \ 531 "ext2load usb 0:4 $fdtaddr $fdtfile;" \ 532 "ext2load usb 0:4 $ramdiskaddr $ramdiskfile;" \ 533 "bootm $loadaddr $ramdiskaddr $fdtaddr" 534 535 #define CONFIG_NORBOOT \ 536 "setenv bootargs root=/dev/mtdblock3 rw " \ 537 "console=$consoledev,$baudrate rootfstype=jffs2 $othbootargs;" \ 538 "bootm $norbootaddr - $norfdtaddr" 539 540 #define CONFIG_RAMBOOTCOMMAND_TFTP \ 541 "setenv bootargs root=/dev/ram rw " \ 542 "console=$consoledev,$baudrate $othbootargs " \ 543 "ramdisk_size=$ramdisk_size;" \ 544 "tftp $ramdiskaddr $ramdiskfile;" \ 545 "tftp $loadaddr $bootfile;" \ 546 "tftp $fdtaddr $fdtfile;" \ 547 "bootm $loadaddr $ramdiskaddr $fdtaddr" 548 549 #define CONFIG_RAMBOOTCOMMAND \ 550 "setenv bootargs root=/dev/ram rw " \ 551 "console=$consoledev,$baudrate $othbootargs " \ 552 "ramdisk_size=$ramdisk_size;" \ 553 "bootm 0xefa80000 0xeeb80000 0xefe80000" 554 555 #define CONFIG_BOOTCOMMAND CONFIG_RAMBOOTCOMMAND 556 557 #endif /* __CONFIG_H */ 558