1 /* 2 * Copyright 2013 Freescale Semiconductor, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 /* 8 * QorIQ P1 Tower boards configuration file 9 */ 10 #ifndef __CONFIG_H 11 #define __CONFIG_H 12 13 #if defined(CONFIG_TWR_P1025) 14 #define CONFIG_BOARDNAME "TWR-P1025" 15 #define CONFIG_P1025 16 #define CONFIG_PHY_ATHEROS 17 #define CONFIG_QE 18 #define CONFIG_SYS_LBC_LBCR 0x00080000 /* Conversion of LBC addr */ 19 #define CONFIG_SYS_LBC_LCRR 0x80000002 /* LB clock ratio reg */ 20 #endif 21 22 #ifdef CONFIG_SDCARD 23 #define CONFIG_RAMBOOT_SDCARD 24 #define CONFIG_SYS_RAMBOOT 25 #define CONFIG_SYS_EXTRA_ENV_RELOC 26 #define CONFIG_SYS_TEXT_BASE 0x11000000 27 #define CONFIG_RESET_VECTOR_ADDRESS 0x110bfffc 28 #endif 29 30 #ifndef CONFIG_SYS_TEXT_BASE 31 #define CONFIG_SYS_TEXT_BASE 0xeff40000 32 #endif 33 34 #ifndef CONFIG_RESET_VECTOR_ADDRESS 35 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc 36 #endif 37 38 #ifndef CONFIG_SYS_MONITOR_BASE 39 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 40 #endif 41 42 /* High Level Configuration Options */ 43 #define CONFIG_BOOKE 44 #define CONFIG_E500 45 46 #define CONFIG_MP 47 48 #define CONFIG_FSL_ELBC 49 #define CONFIG_PCI 50 #define CONFIG_PCIE1 /* PCIE controler 1 (slot 1) */ 51 #define CONFIG_PCIE2 /* PCIE controler 2 (slot 2) */ 52 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ 53 #define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */ 54 #define CONFIG_FSL_PCIE_RESET /* need PCIe reset errata */ 55 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ 56 57 #define CONFIG_FSL_LAW 58 #define CONFIG_TSEC_ENET /* tsec ethernet support */ 59 #define CONFIG_ENV_OVERWRITE 60 61 #define CONFIG_CMD_SATA 62 #define CONFIG_SATA_SIL3114 63 #define CONFIG_SYS_SATA_MAX_DEVICE 2 64 #define CONFIG_LIBATA 65 #define CONFIG_LBA48 66 67 #ifndef __ASSEMBLY__ 68 extern unsigned long get_board_sys_clk(unsigned long dummy); 69 #endif 70 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk(0) /*sysclk for TWR-P1025 */ 71 72 #define CONFIG_DDR_CLK_FREQ 66666666 73 74 #define CONFIG_HWCONFIG 75 /* 76 * These can be toggled for performance analysis, otherwise use default. 77 */ 78 #define CONFIG_L2_CACHE 79 #define CONFIG_BTB 80 81 #define CONFIG_BOARD_EARLY_INIT_F /* Call board_pre_init */ 82 83 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ 84 #define CONFIG_SYS_MEMTEST_END 0x1fffffff 85 #define CONFIG_PANIC_HANG /* do not reset board on panic */ 86 87 #define CONFIG_SYS_CCSRBAR 0xffe00000 88 #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR 89 90 /* DDR Setup */ 91 #define CONFIG_SYS_FSL_DDR3 92 93 #define CONFIG_SYS_SDRAM_SIZE_LAW LAW_SIZE_512M 94 #define CONFIG_CHIP_SELECTS_PER_CTRL 1 95 96 #define CONFIG_SYS_SDRAM_SIZE (1u << (CONFIG_SYS_SDRAM_SIZE_LAW - 19)) 97 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 98 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 99 100 #define CONFIG_NUM_DDR_CONTROLLERS 1 101 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 102 103 /* Default settings for DDR3 */ 104 #define CONFIG_SYS_DDR_CS0_BNDS 0x0000001f 105 #define CONFIG_SYS_DDR_CS0_CONFIG 0x80014202 106 #define CONFIG_SYS_DDR_CS0_CONFIG_2 0x00000000 107 #define CONFIG_SYS_DDR_CS1_BNDS 0x00000000 108 #define CONFIG_SYS_DDR_CS1_CONFIG 0x00000000 109 #define CONFIG_SYS_DDR_CS1_CONFIG_2 0x00000000 110 111 #define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef 112 #define CONFIG_SYS_DDR_INIT_ADDR 0x00000000 113 #define CONFIG_SYS_DDR_INIT_EXT_ADDR 0x00000000 114 #define CONFIG_SYS_DDR_MODE_CONTROL 0x00000000 115 116 #define CONFIG_SYS_DDR_ZQ_CONTROL 0x89080600 117 #define CONFIG_SYS_DDR_WRLVL_CONTROL 0x8655a608 118 #define CONFIG_SYS_DDR_SR_CNTR 0x00000000 119 #define CONFIG_SYS_DDR_RCW_1 0x00000000 120 #define CONFIG_SYS_DDR_RCW_2 0x00000000 121 #define CONFIG_SYS_DDR_CONTROL 0xc70c0000 /* Type = DDR3 */ 122 #define CONFIG_SYS_DDR_CONTROL_2 0x04401050 123 #define CONFIG_SYS_DDR_TIMING_4 0x00220001 124 #define CONFIG_SYS_DDR_TIMING_5 0x03402400 125 126 #define CONFIG_SYS_DDR_TIMING_3 0x00020000 127 #define CONFIG_SYS_DDR_TIMING_0 0x00220004 128 #define CONFIG_SYS_DDR_TIMING_1 0x5c5b6544 129 #define CONFIG_SYS_DDR_TIMING_2 0x0fa880de 130 #define CONFIG_SYS_DDR_CLK_CTRL 0x03000000 131 #define CONFIG_SYS_DDR_MODE_1 0x80461320 132 #define CONFIG_SYS_DDR_MODE_2 0x00008000 133 #define CONFIG_SYS_DDR_INTERVAL 0x09480000 134 135 /* 136 * Memory map 137 * 138 * 0x0000_0000 0x1fff_ffff DDR Up to 512MB cacheable 139 * 0x8000_0000 0xdfff_ffff PCI Express Mem 1.5G non-cacheable(PCIe * 3) 140 * 0xffc0_0000 0xffc3_ffff PCI IO range 256k non-cacheable 141 * 142 * Localbus 143 * 0xe000_0000 0xe002_0000 SSD1289 128K non-cacheable 144 * 0xec00_0000 0xefff_ffff FLASH Up to 64M non-cacheable 145 * 146 * 0xff90_0000 0xff97_ffff L2 SRAM Up to 512K cacheable 147 * 0xffd0_0000 0xffd0_3fff init ram 16K Cacheable 148 * 0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable 149 */ 150 151 /* 152 * Local Bus Definitions 153 */ 154 #define CONFIG_SYS_MAX_FLASH_SECT 512 /* 64M */ 155 #define CONFIG_SYS_FLASH_BASE 0xec000000 156 157 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE 158 159 #define CONFIG_FLASH_BR_PRELIM (BR_PHYS_ADDR((CONFIG_SYS_FLASH_BASE_PHYS)) \ 160 | BR_PS_16 | BR_V) 161 162 #define CONFIG_FLASH_OR_PRELIM 0xfc0000b1 163 164 #define CONFIG_SYS_SSD_BASE 0xe0000000 165 #define CONFIG_SYS_SSD_BASE_PHYS CONFIG_SYS_SSD_BASE 166 #define CONFIG_SSD_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_SSD_BASE_PHYS) | \ 167 BR_PS_16 | BR_V) 168 #define CONFIG_SSD_OR_PRELIM (OR_AM_64KB | OR_GPCM_CSNT | OR_GPCM_XACS | \ 169 OR_GPCM_ACS_DIV2 | OR_GPCM_SCY | \ 170 OR_GPCM_TRLX | OR_GPCM_EHTR | OR_GPCM_EAD) 171 172 #define CONFIG_SYS_BR2_PRELIM CONFIG_SSD_BR_PRELIM 173 #define CONFIG_SYS_OR2_PRELIM CONFIG_SSD_OR_PRELIM 174 175 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS} 176 #define CONFIG_SYS_FLASH_QUIET_TEST 177 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 178 179 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ 180 181 #undef CONFIG_SYS_FLASH_CHECKSUM 182 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 183 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 184 185 #define CONFIG_FLASH_CFI_DRIVER 186 #define CONFIG_SYS_FLASH_CFI 187 #define CONFIG_SYS_FLASH_EMPTY_INFO 188 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 189 190 #define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */ 191 192 #define CONFIG_SYS_INIT_RAM_LOCK 193 #define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 194 /* Initial L1 address */ 195 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS CONFIG_SYS_INIT_RAM_ADDR 196 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0 197 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS 198 /* Size of used area in RAM */ 199 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 200 201 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ 202 GENERATED_GBL_DATA_SIZE) 203 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 204 205 #define CONFIG_SYS_MONITOR_LEN (512 * 1024)/* Reserve 512 kB for Mon */ 206 #define CONFIG_SYS_MALLOC_LEN (1024 * 1024)/* Reserved for malloc */ 207 208 #define CONFIG_SYS_BR0_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */ 209 #define CONFIG_SYS_OR0_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */ 210 211 /* Serial Port 212 * open - index 2 213 * shorted - index 1 214 */ 215 #define CONFIG_CONS_INDEX 1 216 #undef CONFIG_SERIAL_SOFTWARE_FIFO 217 #define CONFIG_SYS_NS16550 218 #define CONFIG_SYS_NS16550_SERIAL 219 #define CONFIG_SYS_NS16550_REG_SIZE 1 220 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) 221 222 #define CONFIG_SYS_BAUDRATE_TABLE \ 223 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} 224 225 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) 226 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) 227 228 /* Use the HUSH parser */ 229 #define CONFIG_SYS_HUSH_PARSER 230 #ifdef CONFIG_SYS_HUSH_PARSER 231 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> " 232 #endif 233 234 /* 235 * Pass open firmware flat tree 236 */ 237 #define CONFIG_OF_LIBFDT 238 #define CONFIG_OF_BOARD_SETUP 239 #define CONFIG_OF_STDOUT_VIA_ALIAS 240 241 /* new uImage format support */ 242 #define CONFIG_FIT 243 #define CONFIG_FIT_VERBOSE /* enable fit_format_{error,warning}() */ 244 245 /* I2C */ 246 #define CONFIG_SYS_I2C 247 #define CONFIG_SYS_I2C_FSL /* Use FSL common I2C driver */ 248 #define CONFIG_SYS_FSL_I2C_SPEED 400000 /* I2C spd and slave address */ 249 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 250 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 251 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x52 252 253 /* 254 * I2C2 EEPROM 255 */ 256 #define CONFIG_SYS_FSL_I2C2_SPEED 400000 /* I2C spd and slave address */ 257 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F 258 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100 259 260 #define CONFIG_SYS_I2C_PCA9555_ADDR 0x23 261 262 /* enable read and write access to EEPROM */ 263 #define CONFIG_CMD_EEPROM 264 #define CONFIG_SYS_I2C_MULTI_EEPROMS 265 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 266 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 267 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 268 269 /* 270 * eSPI - Enhanced SPI 271 */ 272 #define CONFIG_HARD_SPI 273 #define CONFIG_FSL_ESPI 274 275 #if defined(CONFIG_PCI) 276 /* 277 * General PCI 278 * Memory space is mapped 1-1, but I/O space must start from 0. 279 */ 280 281 /* controller 2, direct to uli, tgtid 2, Base address 9000 */ 282 #define CONFIG_SYS_PCIE2_NAME "TWR-ELEV PCIe SLOT" 283 #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000 284 #define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000 285 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000 286 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */ 287 #define CONFIG_SYS_PCIE2_IO_VIRT 0xffc10000 288 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 289 #define CONFIG_SYS_PCIE2_IO_PHYS 0xffc10000 290 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ 291 292 /* controller 1, tgtid 1, Base address a000 */ 293 #define CONFIG_SYS_PCIE1_NAME "mini PCIe SLOT" 294 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 295 #define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000 296 #define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000 297 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ 298 #define CONFIG_SYS_PCIE1_IO_VIRT 0xffc00000 299 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 300 #define CONFIG_SYS_PCIE1_IO_PHYS 0xffc00000 301 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ 302 303 #define CONFIG_NET_MULTI 304 #define CONFIG_PCI_PNP /* do pci plug-and-play */ 305 #define CONFIG_E1000 /* Defind e1000 pci Ethernet card*/ 306 #define CONFIG_CMD_PCI 307 #define CONFIG_CMD_NET 308 309 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 310 #define CONFIG_DOS_PARTITION 311 #endif /* CONFIG_PCI */ 312 313 #if defined(CONFIG_TSEC_ENET) 314 315 #ifndef CONFIG_NET_MULTI 316 #define CONFIG_NET_MULTI 317 #endif 318 319 #define CONFIG_MII /* MII PHY management */ 320 #define CONFIG_TSEC1 321 #define CONFIG_TSEC1_NAME "eTSEC1" 322 #undef CONFIG_TSEC2 323 #undef CONFIG_TSEC2_NAME 324 #define CONFIG_TSEC3 325 #define CONFIG_TSEC3_NAME "eTSEC3" 326 327 #define TSEC1_PHY_ADDR 2 328 #define TSEC2_PHY_ADDR 0 329 #define TSEC3_PHY_ADDR 1 330 331 #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 332 #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 333 #define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 334 335 #define TSEC1_PHYIDX 0 336 #define TSEC2_PHYIDX 0 337 #define TSEC3_PHYIDX 0 338 339 #define CONFIG_ETHPRIME "eTSEC1" 340 341 #define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */ 342 343 #define CONFIG_HAS_ETH0 344 #define CONFIG_HAS_ETH1 345 #undef CONFIG_HAS_ETH2 346 #endif /* CONFIG_TSEC_ENET */ 347 348 #ifdef CONFIG_QE 349 /* QE microcode/firmware address */ 350 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR 351 #define CONFIG_SYS_QE_FMAN_FW_ADDR 0xefec0000 352 #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 353 #endif /* CONFIG_QE */ 354 355 #ifdef CONFIG_TWR_P1025 356 /* 357 * QE UEC ethernet configuration 358 */ 359 #define CONFIG_MIIM_ADDRESS (CONFIG_SYS_CCSRBAR + 0x82120) 360 361 #undef CONFIG_UEC_ETH 362 #define CONFIG_PHY_MODE_NEED_CHANGE 363 364 #define CONFIG_UEC_ETH1 /* ETH1 */ 365 #define CONFIG_HAS_ETH0 366 367 #ifdef CONFIG_UEC_ETH1 368 #define CONFIG_SYS_UEC1_UCC_NUM 0 /* UCC1 */ 369 #define CONFIG_SYS_UEC1_RX_CLK QE_CLK12 /* CLK12 for MII */ 370 #define CONFIG_SYS_UEC1_TX_CLK QE_CLK9 /* CLK9 for MII */ 371 #define CONFIG_SYS_UEC1_ETH_TYPE FAST_ETH 372 #define CONFIG_SYS_UEC1_PHY_ADDR 0x18 /* 0x18 for MII */ 373 #define CONFIG_SYS_UEC1_INTERFACE_TYPE PHY_INTERFACE_MODE_MII 374 #define CONFIG_SYS_UEC1_INTERFACE_SPEED 100 375 #endif /* CONFIG_UEC_ETH1 */ 376 377 #define CONFIG_UEC_ETH5 /* ETH5 */ 378 #define CONFIG_HAS_ETH1 379 380 #ifdef CONFIG_UEC_ETH5 381 #define CONFIG_SYS_UEC5_UCC_NUM 4 /* UCC5 */ 382 #define CONFIG_SYS_UEC5_RX_CLK QE_CLK_NONE 383 #define CONFIG_SYS_UEC5_TX_CLK QE_CLK13 /* CLK 13 for RMII */ 384 #define CONFIG_SYS_UEC5_ETH_TYPE FAST_ETH 385 #define CONFIG_SYS_UEC5_PHY_ADDR 0x19 /* 0x19 for RMII */ 386 #define CONFIG_SYS_UEC5_INTERFACE_TYPE PHY_INTERFACE_MODE_RMII 387 #define CONFIG_SYS_UEC5_INTERFACE_SPEED 100 388 #endif /* CONFIG_UEC_ETH5 */ 389 #endif /* CONFIG_TWR-P1025 */ 390 391 /* 392 * Environment 393 */ 394 #ifdef CONFIG_SYS_RAMBOOT 395 #ifdef CONFIG_RAMBOOT_SDCARD 396 #define CONFIG_ENV_IS_IN_MMC 397 #define CONFIG_ENV_SIZE 0x2000 398 #define CONFIG_SYS_MMC_ENV_DEV 0 399 #else 400 #define CONFIG_ENV_IS_NOWHERE /* Store ENV in memory only */ 401 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) 402 #define CONFIG_ENV_SIZE 0x2000 403 #endif 404 #else 405 #define CONFIG_ENV_IS_IN_FLASH 406 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) 407 #define CONFIG_ENV_SIZE 0x2000 408 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ 409 #endif 410 411 #define CONFIG_LOADS_ECHO /* echo on for serial download */ 412 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ 413 414 /* 415 * Command line configuration. 416 */ 417 #include <config_cmd_default.h> 418 419 #define CONFIG_CMD_IRQ 420 #define CONFIG_CMD_PING 421 #define CONFIG_CMD_I2C 422 #define CONFIG_CMD_MII 423 #define CONFIG_CMD_ELF 424 #define CONFIG_CMD_SETEXPR 425 #define CONFIG_CMD_REGINFO 426 427 /* 428 * USB 429 */ 430 #define CONFIG_HAS_FSL_DR_USB 431 432 #if defined(CONFIG_HAS_FSL_DR_USB) 433 #define CONFIG_USB_EHCI 434 435 #ifdef CONFIG_USB_EHCI 436 #define CONFIG_CMD_USB 437 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 438 #define CONFIG_USB_EHCI_FSL 439 #define CONFIG_USB_STORAGE 440 #endif 441 #endif 442 443 #define CONFIG_MMC 444 445 #ifdef CONFIG_MMC 446 #define CONFIG_FSL_ESDHC 447 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR 448 #define CONFIG_CMD_MMC 449 #define CONFIG_GENERIC_MMC 450 #endif 451 452 #if defined(CONFIG_MMC) || defined(CONFIG_USB_EHCI) \ 453 || defined(CONFIG_FSL_SATA) 454 #define CONFIG_CMD_EXT2 455 #define CONFIG_CMD_FAT 456 #define CONFIG_DOS_PARTITION 457 #endif 458 459 #undef CONFIG_WATCHDOG /* watchdog disabled */ 460 461 /* 462 * Miscellaneous configurable options 463 */ 464 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 465 #define CONFIG_CMDLINE_EDITING /* Command-line editing */ 466 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 467 #if defined(CONFIG_CMD_KGDB) 468 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 469 #else 470 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 471 #endif 472 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) 473 /* Print Buffer Size */ 474 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 475 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */ 476 477 /* 478 * For booting Linux, the board info and command line data 479 * have to be in the first 64 MB of memory, since this is 480 * the maximum mapped by the Linux kernel during initialization. 481 */ 482 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory for Linux*/ 483 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 484 485 /* 486 * Environment Configuration 487 */ 488 #define CONFIG_HOSTNAME unknown 489 #define CONFIG_ROOTPATH "/opt/nfsroot" 490 #define CONFIG_BOOTFILE "uImage" 491 #define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */ 492 493 /* default location for tftp and bootm */ 494 #define CONFIG_LOADADDR 1000000 495 496 #define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */ 497 #define CONFIG_BOOTARGS /* the boot command will set bootargs */ 498 499 #define CONFIG_BAUDRATE 115200 500 501 #define CONFIG_EXTRA_ENV_SETTINGS \ 502 "netdev=eth0\0" \ 503 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ 504 "loadaddr=1000000\0" \ 505 "bootfile=uImage\0" \ 506 "dtbfile=twr-p1025twr.dtb\0" \ 507 "ramdiskfile=rootfs.ext2.gz.uboot\0" \ 508 "qefirmwarefile=fsl_qe_ucode_1021_10_A.bin\0" \ 509 "tftpflash=tftpboot $loadaddr $uboot; " \ 510 "protect off " __stringify(CONFIG_SYS_TEXT_BASE) " +$filesize; " \ 511 "erase " __stringify(CONFIG_SYS_TEXT_BASE) " +$filesize; " \ 512 "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) " $filesize; " \ 513 "protect on " __stringify(CONFIG_SYS_TEXT_BASE) " +$filesize; " \ 514 "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) " $filesize\0" \ 515 "kernelflash=tftpboot $loadaddr $bootfile; " \ 516 "protect off 0xefa80000 +$filesize; " \ 517 "erase 0xefa80000 +$filesize; " \ 518 "cp.b $loadaddr 0xefa80000 $filesize; " \ 519 "protect on 0xefa80000 +$filesize; " \ 520 "cmp.b $loadaddr 0xefa80000 $filesize\0" \ 521 "dtbflash=tftpboot $loadaddr $dtbfile; " \ 522 "protect off 0xefe80000 +$filesize; " \ 523 "erase 0xefe80000 +$filesize; " \ 524 "cp.b $loadaddr 0xefe80000 $filesize; " \ 525 "protect on 0xefe80000 +$filesize; " \ 526 "cmp.b $loadaddr 0xefe80000 $filesize\0" \ 527 "ramdiskflash=tftpboot $loadaddr $ramdiskfile; " \ 528 "protect off 0xeeb80000 +$filesize; " \ 529 "erase 0xeeb80000 +$filesize; " \ 530 "cp.b $loadaddr 0xeeb80000 $filesize; " \ 531 "protect on 0xeeb80000 +$filesize; " \ 532 "cmp.b $loadaddr 0xeeb80000 $filesize\0" \ 533 "qefirmwareflash=tftpboot $loadaddr $qefirmwarefile; " \ 534 "protect off 0xefec0000 +$filesize; " \ 535 "erase 0xefec0000 +$filesize; " \ 536 "cp.b $loadaddr 0xefec0000 $filesize; " \ 537 "protect on 0xefec0000 +$filesize; " \ 538 "cmp.b $loadaddr 0xefec0000 $filesize\0" \ 539 "consoledev=ttyS0\0" \ 540 "ramdiskaddr=2000000\0" \ 541 "ramdiskfile=rootfs.ext2.gz.uboot\0" \ 542 "fdtaddr=c00000\0" \ 543 "bdev=sda1\0" \ 544 "norbootaddr=ef080000\0" \ 545 "norfdtaddr=ef040000\0" \ 546 "ramdisk_size=120000\0" \ 547 "usbboot=setenv bootargs root=/dev/sda1 rw rootdelay=5 " \ 548 "console=$consoledev,$baudrate $othbootargs ; bootm 0xefa80000 - 0xefe80000" 549 550 #define CONFIG_NFSBOOTCOMMAND \ 551 "setenv bootargs root=/dev/nfs rw " \ 552 "nfsroot=$serverip:$rootpath " \ 553 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 554 "console=$consoledev,$baudrate $othbootargs;" \ 555 "tftp $loadaddr $bootfile&&" \ 556 "tftp $fdtaddr $fdtfile&&" \ 557 "bootm $loadaddr - $fdtaddr" 558 559 #define CONFIG_HDBOOT \ 560 "setenv bootargs root=/dev/$bdev rw rootdelay=30 " \ 561 "console=$consoledev,$baudrate $othbootargs;" \ 562 "usb start;" \ 563 "ext2load usb 0:1 $loadaddr /boot/$bootfile;" \ 564 "ext2load usb 0:1 $fdtaddr /boot/$fdtfile;" \ 565 "bootm $loadaddr - $fdtaddr" 566 567 #define CONFIG_USB_FAT_BOOT \ 568 "setenv bootargs root=/dev/ram rw " \ 569 "console=$consoledev,$baudrate $othbootargs " \ 570 "ramdisk_size=$ramdisk_size;" \ 571 "usb start;" \ 572 "fatload usb 0:2 $loadaddr $bootfile;" \ 573 "fatload usb 0:2 $fdtaddr $fdtfile;" \ 574 "fatload usb 0:2 $ramdiskaddr $ramdiskfile;" \ 575 "bootm $loadaddr $ramdiskaddr $fdtaddr" 576 577 #define CONFIG_USB_EXT2_BOOT \ 578 "setenv bootargs root=/dev/ram rw " \ 579 "console=$consoledev,$baudrate $othbootargs " \ 580 "ramdisk_size=$ramdisk_size;" \ 581 "usb start;" \ 582 "ext2load usb 0:4 $loadaddr $bootfile;" \ 583 "ext2load usb 0:4 $fdtaddr $fdtfile;" \ 584 "ext2load usb 0:4 $ramdiskaddr $ramdiskfile;" \ 585 "bootm $loadaddr $ramdiskaddr $fdtaddr" 586 587 #define CONFIG_NORBOOT \ 588 "setenv bootargs root=/dev/mtdblock3 rw " \ 589 "console=$consoledev,$baudrate rootfstype=jffs2 $othbootargs;" \ 590 "bootm $norbootaddr - $norfdtaddr" 591 592 #define CONFIG_RAMBOOTCOMMAND_TFTP \ 593 "setenv bootargs root=/dev/ram rw " \ 594 "console=$consoledev,$baudrate $othbootargs " \ 595 "ramdisk_size=$ramdisk_size;" \ 596 "tftp $ramdiskaddr $ramdiskfile;" \ 597 "tftp $loadaddr $bootfile;" \ 598 "tftp $fdtaddr $fdtfile;" \ 599 "bootm $loadaddr $ramdiskaddr $fdtaddr" 600 601 #define CONFIG_RAMBOOTCOMMAND \ 602 "setenv bootargs root=/dev/ram rw " \ 603 "console=$consoledev,$baudrate $othbootargs " \ 604 "ramdisk_size=$ramdisk_size;" \ 605 "bootm 0xefa80000 0xeeb80000 0xefe80000" 606 607 #define CONFIG_BOOTCOMMAND CONFIG_RAMBOOTCOMMAND 608 609 #endif /* __CONFIG_H */ 610