1 /*
2  * Copyright 2010-2011 Freescale Semiconductor, Inc.
3  *
4  * SPDX-License-Identifier:	GPL-2.0+
5  */
6 
7 /*
8  * QorIQ RDB boards configuration file
9  */
10 #ifndef __CONFIG_H
11 #define __CONFIG_H
12 
13 #if defined(CONFIG_TARGET_P1020MBG)
14 #define CONFIG_BOARDNAME "P1020MBG-PC"
15 #define CONFIG_VSC7385_ENET
16 #define CONFIG_SLIC
17 #define __SW_BOOT_MASK		0x03
18 #define __SW_BOOT_NOR		0xe4
19 #define __SW_BOOT_SD		0x54
20 #define CONFIG_SYS_L2_SIZE	(256 << 10)
21 #endif
22 
23 #if defined(CONFIG_TARGET_P1020UTM)
24 #define CONFIG_BOARDNAME "P1020UTM-PC"
25 #define __SW_BOOT_MASK		0x03
26 #define __SW_BOOT_NOR		0xe0
27 #define __SW_BOOT_SD		0x50
28 #define CONFIG_SYS_L2_SIZE	(256 << 10)
29 #endif
30 
31 #if defined(CONFIG_TARGET_P1020RDB_PC)
32 #define CONFIG_BOARDNAME "P1020RDB-PC"
33 #define CONFIG_NAND_FSL_ELBC
34 #define CONFIG_VSC7385_ENET
35 #define CONFIG_SLIC
36 #define __SW_BOOT_MASK		0x03
37 #define __SW_BOOT_NOR		0x5c
38 #define __SW_BOOT_SPI		0x1c
39 #define __SW_BOOT_SD		0x9c
40 #define __SW_BOOT_NAND		0xec
41 #define __SW_BOOT_PCIE		0x6c
42 #define CONFIG_SYS_L2_SIZE	(256 << 10)
43 #endif
44 
45 /*
46  * P1020RDB-PD board has user selectable switches for evaluating different
47  * frequency and boot options for the P1020 device. The table that
48  * follow describe the available options. The front six binary number was in
49  * accordance with SW3[1:6].
50  * 111101 533 533 267 667 NOR Core0 boot; Core1 hold-off
51  * 101101 667 667 333 667 NOR Core0 boot; Core1 hold-off
52  * 011001 800 800 400 667 NOR Core0 boot; Core1 hold-off
53  * 001001 800 800 400 667 SD/MMC Core0 boot; Core1 hold-off
54  * 001101 800 800 400 667 SPI Core0 boot; Core1 hold-off
55  * 010001 800 800 400 667 NAND Core0 boot; Core1 hold-off
56  * 011101 800 800 400 667 PCIe-2 Core0 boot; Core1 hold-off
57  */
58 #if defined(CONFIG_TARGET_P1020RDB_PD)
59 #define CONFIG_BOARDNAME "P1020RDB-PD"
60 #define CONFIG_NAND_FSL_ELBC
61 #define CONFIG_VSC7385_ENET
62 #define CONFIG_SLIC
63 #define __SW_BOOT_MASK		0x03
64 #define __SW_BOOT_NOR		0x64
65 #define __SW_BOOT_SPI		0x34
66 #define __SW_BOOT_SD		0x24
67 #define __SW_BOOT_NAND		0x44
68 #define __SW_BOOT_PCIE		0x74
69 #define CONFIG_SYS_L2_SIZE	(256 << 10)
70 /*
71  * Dynamic MTD Partition support with mtdparts
72  */
73 #define CONFIG_MTD_DEVICE
74 #define CONFIG_MTD_PARTITIONS
75 #define CONFIG_FLASH_CFI_MTD
76 #define MTDIDS_DEFAULT "nor0=ec000000.nor"
77 #define MTDPARTS_DEFAULT "mtdparts=ec000000.nor:128k(dtb),6016k(kernel)," \
78 			"57088k(fs),1m(vsc7385-firmware),1280k(u-boot)"
79 #endif
80 
81 #if defined(CONFIG_TARGET_P1021RDB)
82 #define CONFIG_BOARDNAME "P1021RDB-PC"
83 #define CONFIG_NAND_FSL_ELBC
84 #define CONFIG_QE
85 #define CONFIG_VSC7385_ENET
86 #define CONFIG_SYS_LBC_LBCR	0x00080000	/* Implement conversion of
87 						addresses in the LBC */
88 #define __SW_BOOT_MASK		0x03
89 #define __SW_BOOT_NOR		0x5c
90 #define __SW_BOOT_SPI		0x1c
91 #define __SW_BOOT_SD		0x9c
92 #define __SW_BOOT_NAND		0xec
93 #define __SW_BOOT_PCIE		0x6c
94 #define CONFIG_SYS_L2_SIZE	(256 << 10)
95 /*
96  * Dynamic MTD Partition support with mtdparts
97  */
98 #define CONFIG_MTD_DEVICE
99 #define CONFIG_MTD_PARTITIONS
100 #define CONFIG_FLASH_CFI_MTD
101 #ifdef CONFIG_PHYS_64BIT
102 #define MTDIDS_DEFAULT "nor0=fef000000.nor"
103 #define MTDPARTS_DEFAULT "mtdparts=fef000000.nor:256k(vsc7385-firmware)," \
104 			"256k(dtb),4608k(kernel),9728k(fs)," \
105 			"256k(qe-ucode-firmware),1280k(u-boot)"
106 #else
107 #define MTDIDS_DEFAULT "nor0=ef000000.nor"
108 #define MTDPARTS_DEFAULT "mtdparts=ef000000.nor:256k(vsc7385-firmware)," \
109 			"256k(dtb),4608k(kernel),9728k(fs)," \
110 			"256k(qe-ucode-firmware),1280k(u-boot)"
111 #endif
112 #endif
113 
114 #if defined(CONFIG_TARGET_P1024RDB)
115 #define CONFIG_BOARDNAME "P1024RDB"
116 #define CONFIG_NAND_FSL_ELBC
117 #define CONFIG_SLIC
118 #define __SW_BOOT_MASK		0xf3
119 #define __SW_BOOT_NOR		0x00
120 #define __SW_BOOT_SPI		0x08
121 #define __SW_BOOT_SD		0x04
122 #define __SW_BOOT_NAND		0x0c
123 #define CONFIG_SYS_L2_SIZE	(256 << 10)
124 #endif
125 
126 #if defined(CONFIG_TARGET_P1025RDB)
127 #define CONFIG_BOARDNAME "P1025RDB"
128 #define CONFIG_NAND_FSL_ELBC
129 #define CONFIG_QE
130 #define CONFIG_SLIC
131 
132 #define CONFIG_SYS_LBC_LBCR	0x00080000	/* Implement conversion of
133 						addresses in the LBC */
134 #define __SW_BOOT_MASK		0xf3
135 #define __SW_BOOT_NOR		0x00
136 #define __SW_BOOT_SPI		0x08
137 #define __SW_BOOT_SD		0x04
138 #define __SW_BOOT_NAND		0x0c
139 #define CONFIG_SYS_L2_SIZE	(256 << 10)
140 #endif
141 
142 #if defined(CONFIG_TARGET_P2020RDB)
143 #define CONFIG_BOARDNAME "P2020RDB-PC"
144 #define CONFIG_NAND_FSL_ELBC
145 #define CONFIG_VSC7385_ENET
146 #define __SW_BOOT_MASK		0x03
147 #define __SW_BOOT_NOR		0xc8
148 #define __SW_BOOT_SPI		0x28
149 #define __SW_BOOT_SD		0x68 /* or 0x18 */
150 #define __SW_BOOT_NAND		0xe8
151 #define __SW_BOOT_PCIE		0xa8
152 #define CONFIG_SYS_L2_SIZE	(512 << 10)
153 /*
154  * Dynamic MTD Partition support with mtdparts
155  */
156 #define CONFIG_MTD_DEVICE
157 #define CONFIG_MTD_PARTITIONS
158 #define CONFIG_FLASH_CFI_MTD
159 #ifdef CONFIG_PHYS_64BIT
160 #define MTDIDS_DEFAULT "nor0=fef000000.nor"
161 #define MTDPARTS_DEFAULT "mtdparts=fef000000.nor:256k(vsc7385-firmware)," \
162 			"256k(dtb),4608k(kernel),9984k(fs),1280k(u-boot)"
163 #else
164 #define MTDIDS_DEFAULT "nor0=ef000000.nor"
165 #define MTDPARTS_DEFAULT "mtdparts=ef000000.nor:256k(vsc7385-firmware)," \
166 			"256k(dtb),4608k(kernel),9984k(fs),1280k(u-boot)"
167 #endif
168 #endif
169 
170 #ifdef CONFIG_SDCARD
171 #define CONFIG_SPL_MMC_MINIMAL
172 #define CONFIG_SPL_FLUSH_IMAGE
173 #define CONFIG_SPL_TARGET		"u-boot-with-spl.bin"
174 #define CONFIG_SYS_TEXT_BASE		0x11001000
175 #define CONFIG_SPL_TEXT_BASE		0xf8f81000
176 #define CONFIG_SPL_PAD_TO		0x20000
177 #define CONFIG_SPL_MAX_SIZE		(128 * 1024)
178 #define CONFIG_SYS_MMC_U_BOOT_SIZE	(768 << 10)
179 #define CONFIG_SYS_MMC_U_BOOT_DST	(0x11000000)
180 #define CONFIG_SYS_MMC_U_BOOT_START	(0x11000000)
181 #define CONFIG_SYS_MMC_U_BOOT_OFFS	(128 << 10)
182 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
183 #define CONFIG_SYS_LDSCRIPT	"arch/powerpc/cpu/mpc85xx/u-boot.lds"
184 #define CONFIG_SPL_MMC_BOOT
185 #ifdef CONFIG_SPL_BUILD
186 #define CONFIG_SPL_COMMON_INIT_DDR
187 #endif
188 #endif
189 
190 #ifdef CONFIG_SPIFLASH
191 #define CONFIG_SPL_SPI_FLASH_MINIMAL
192 #define CONFIG_SPL_FLUSH_IMAGE
193 #define CONFIG_SPL_TARGET		"u-boot-with-spl.bin"
194 #define CONFIG_SYS_TEXT_BASE		0x11001000
195 #define CONFIG_SPL_TEXT_BASE		0xf8f81000
196 #define CONFIG_SPL_PAD_TO		0x20000
197 #define CONFIG_SPL_MAX_SIZE		(128 * 1024)
198 #define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE	(768 << 10)
199 #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST		(0x11000000)
200 #define CONFIG_SYS_SPI_FLASH_U_BOOT_START	(0x11000000)
201 #define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS	(128 << 10)
202 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
203 #define CONFIG_SYS_LDSCRIPT	"arch/powerpc/cpu/mpc85xx/u-boot.lds"
204 #define CONFIG_SPL_SPI_BOOT
205 #ifdef CONFIG_SPL_BUILD
206 #define CONFIG_SPL_COMMON_INIT_DDR
207 #endif
208 #endif
209 
210 #ifdef CONFIG_NAND
211 #ifdef CONFIG_TPL_BUILD
212 #define CONFIG_SPL_NAND_BOOT
213 #define CONFIG_SPL_FLUSH_IMAGE
214 #define CONFIG_SPL_NAND_INIT
215 #define CONFIG_SPL_COMMON_INIT_DDR
216 #define CONFIG_SPL_MAX_SIZE		(128 << 10)
217 #define CONFIG_SPL_TEXT_BASE		0xf8f81000
218 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
219 #define CONFIG_SYS_NAND_U_BOOT_SIZE	(832 << 10)
220 #define CONFIG_SYS_NAND_U_BOOT_DST	(0x11000000)
221 #define CONFIG_SYS_NAND_U_BOOT_START	(0x11000000)
222 #define CONFIG_SYS_NAND_U_BOOT_OFFS	((128 + 128) << 10)
223 #elif defined(CONFIG_SPL_BUILD)
224 #define CONFIG_SPL_INIT_MINIMAL
225 #define CONFIG_SPL_FLUSH_IMAGE
226 #define CONFIG_SPL_TARGET		"u-boot-with-spl.bin"
227 #define CONFIG_SPL_TEXT_BASE		0xff800000
228 #define CONFIG_SPL_MAX_SIZE		4096
229 #define CONFIG_SYS_NAND_U_BOOT_SIZE	(128 << 10)
230 #define CONFIG_SYS_NAND_U_BOOT_DST	0xf8f80000
231 #define CONFIG_SYS_NAND_U_BOOT_START	0xf8f80000
232 #define CONFIG_SYS_NAND_U_BOOT_OFFS	(128 << 10)
233 #endif /* not CONFIG_TPL_BUILD */
234 
235 #define CONFIG_SPL_PAD_TO		0x20000
236 #define CONFIG_TPL_PAD_TO		0x20000
237 #define CONFIG_SPL_TARGET		"u-boot-with-spl.bin"
238 #define CONFIG_SYS_TEXT_BASE		0x11001000
239 #define CONFIG_SYS_LDSCRIPT	"arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
240 #endif
241 
242 #ifndef CONFIG_SYS_TEXT_BASE
243 #define CONFIG_SYS_TEXT_BASE		0xeff40000
244 #endif
245 
246 #ifndef CONFIG_RESET_VECTOR_ADDRESS
247 #define CONFIG_RESET_VECTOR_ADDRESS	0xeffffffc
248 #endif
249 
250 #ifndef CONFIG_SYS_MONITOR_BASE
251 #ifdef CONFIG_SPL_BUILD
252 #define CONFIG_SYS_MONITOR_BASE	CONFIG_SPL_TEXT_BASE
253 #else
254 #define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_TEXT_BASE	/* start of monitor */
255 #endif
256 #endif
257 
258 #define CONFIG_MP
259 
260 #define CONFIG_PCIE1	/* PCIE controller 1 (slot 1) */
261 #define CONFIG_PCIE2	/* PCIE controller 2 (slot 2) */
262 #define CONFIG_FSL_PCI_INIT	/* Use common FSL init code */
263 #define CONFIG_PCI_INDIRECT_BRIDGE	/* indirect PCI bridge support */
264 #define CONFIG_FSL_PCIE_RESET	/* need PCIe reset errata */
265 #define CONFIG_SYS_PCI_64BIT	/* enable 64-bit PCI resources */
266 
267 #define CONFIG_TSEC_ENET	/* tsec ethernet support */
268 #define CONFIG_ENV_OVERWRITE
269 
270 #define CONFIG_SATA_SIL
271 #define CONFIG_SYS_SATA_MAX_DEVICE	2
272 #define CONFIG_LIBATA
273 #define CONFIG_LBA48
274 
275 #if defined(CONFIG_TARGET_P2020RDB)
276 #define CONFIG_SYS_CLK_FREQ	100000000
277 #else
278 #define CONFIG_SYS_CLK_FREQ	66666666
279 #endif
280 #define CONFIG_DDR_CLK_FREQ	66666666
281 
282 #define CONFIG_HWCONFIG
283 /*
284  * These can be toggled for performance analysis, otherwise use default.
285  */
286 #define CONFIG_L2_CACHE
287 #define CONFIG_BTB
288 
289 #define CONFIG_ENABLE_36BIT_PHYS
290 
291 #ifdef CONFIG_PHYS_64BIT
292 #define CONFIG_ADDR_MAP			1
293 #define CONFIG_SYS_NUM_ADDR_MAP		16	/* number of TLB1 entries */
294 #endif
295 
296 #define CONFIG_SYS_MEMTEST_START	0x00200000	/* memtest works on */
297 #define CONFIG_SYS_MEMTEST_END		0x1fffffff
298 #define CONFIG_PANIC_HANG	/* do not reset board on panic */
299 
300 #define CONFIG_SYS_CCSRBAR		0xffe00000
301 #define CONFIG_SYS_CCSRBAR_PHYS_LOW	CONFIG_SYS_CCSRBAR
302 
303 /* IN case of NAND bootloader relocate CCSRBAR in RAMboot code not in the 4k
304        SPL code*/
305 #ifdef CONFIG_SPL_BUILD
306 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
307 #endif
308 
309 /* DDR Setup */
310 #define CONFIG_SYS_DDR_RAW_TIMING
311 #define CONFIG_DDR_SPD
312 #define CONFIG_SYS_SPD_BUS_NUM 1
313 #define SPD_EEPROM_ADDRESS 0x52
314 #undef CONFIG_FSL_DDR_INTERACTIVE
315 
316 #if (defined(CONFIG_TARGET_P1020MBG) || defined(CONFIG_TARGET_P1020RDB_PD))
317 #define CONFIG_SYS_SDRAM_SIZE_LAW	LAW_SIZE_2G
318 #define CONFIG_CHIP_SELECTS_PER_CTRL	2
319 #else
320 #define CONFIG_SYS_SDRAM_SIZE_LAW	LAW_SIZE_1G
321 #define CONFIG_CHIP_SELECTS_PER_CTRL	1
322 #endif
323 #define CONFIG_SYS_SDRAM_SIZE		(1u << (CONFIG_SYS_SDRAM_SIZE_LAW - 19))
324 #define CONFIG_SYS_DDR_SDRAM_BASE	0x00000000
325 #define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_DDR_SDRAM_BASE
326 
327 #define CONFIG_DIMM_SLOTS_PER_CTLR	1
328 
329 /* Default settings for DDR3 */
330 #ifndef CONFIG_TARGET_P2020RDB
331 #define CONFIG_SYS_DDR_CS0_BNDS		0x0000003f
332 #define CONFIG_SYS_DDR_CS0_CONFIG	0x80014302
333 #define CONFIG_SYS_DDR_CS0_CONFIG_2	0x00000000
334 #define CONFIG_SYS_DDR_CS1_BNDS		0x0040007f
335 #define CONFIG_SYS_DDR_CS1_CONFIG	0x80014302
336 #define CONFIG_SYS_DDR_CS1_CONFIG_2	0x00000000
337 
338 #define CONFIG_SYS_DDR_DATA_INIT	0xdeadbeef
339 #define CONFIG_SYS_DDR_INIT_ADDR	0x00000000
340 #define CONFIG_SYS_DDR_INIT_EXT_ADDR	0x00000000
341 #define CONFIG_SYS_DDR_MODE_CONTROL	0x00000000
342 
343 #define CONFIG_SYS_DDR_ZQ_CONTROL	0x89080600
344 #define CONFIG_SYS_DDR_WRLVL_CONTROL	0x8655A608
345 #define CONFIG_SYS_DDR_SR_CNTR		0x00000000
346 #define CONFIG_SYS_DDR_RCW_1		0x00000000
347 #define CONFIG_SYS_DDR_RCW_2		0x00000000
348 #define CONFIG_SYS_DDR_CONTROL		0xC70C0000	/* Type = DDR3	*/
349 #define CONFIG_SYS_DDR_CONTROL_2	0x04401050
350 #define CONFIG_SYS_DDR_TIMING_4		0x00220001
351 #define CONFIG_SYS_DDR_TIMING_5		0x03402400
352 
353 #define CONFIG_SYS_DDR_TIMING_3		0x00020000
354 #define CONFIG_SYS_DDR_TIMING_0		0x00330004
355 #define CONFIG_SYS_DDR_TIMING_1		0x6f6B4846
356 #define CONFIG_SYS_DDR_TIMING_2		0x0FA8C8CF
357 #define CONFIG_SYS_DDR_CLK_CTRL		0x03000000
358 #define CONFIG_SYS_DDR_MODE_1		0x40461520
359 #define CONFIG_SYS_DDR_MODE_2		0x8000c000
360 #define CONFIG_SYS_DDR_INTERVAL		0x0C300000
361 #endif
362 
363 #undef CONFIG_CLOCKS_IN_MHZ
364 
365 /*
366  * Memory map
367  *
368  * 0x0000_0000 0x7fff_ffff	DDR		Up to 2GB cacheable
369  * 0x8000_0000 0xdfff_ffff	PCI Express Mem	1.5G non-cacheable(PCIe * 3)
370  * 0xec00_0000 0xefff_ffff	NOR flash	Up to 64M non-cacheable	CS0/1
371  * 0xf8f8_0000 0xf8ff_ffff	L2 SRAM		Up to 512K cacheable
372  *   (early boot only)
373  * 0xff80_0000 0xff80_7fff	NAND flash	32K non-cacheable	CS1/0
374  * 0xff98_0000 0xff98_ffff	PMC		64K non-cacheable	CS2
375  * 0xffa0_0000 0xffaf_ffff	CPLD		1M non-cacheable	CS3
376  * 0xffb0_0000 0xffbf_ffff	VSC7385 switch  1M non-cacheable	CS2
377  * 0xffc0_0000 0xffc3_ffff	PCI IO range	256k non-cacheable
378  * 0xffd0_0000 0xffd0_3fff	L1 for stack	16K cacheable
379  * 0xffe0_0000 0xffef_ffff	CCSR		1M non-cacheable
380  */
381 
382 /*
383  * Local Bus Definitions
384  */
385 #if (defined(CONFIG_TARGET_P1020MBG) || defined(CONFIG_TARGET_P1020RDB_PD))
386 #define CONFIG_SYS_MAX_FLASH_SECT	512	/* 64M */
387 #define CONFIG_SYS_FLASH_BASE		0xec000000
388 #elif defined(CONFIG_TARGET_P1020UTM)
389 #define CONFIG_SYS_MAX_FLASH_SECT	256	/* 32M */
390 #define CONFIG_SYS_FLASH_BASE		0xee000000
391 #else
392 #define CONFIG_SYS_MAX_FLASH_SECT	128	/* 16M */
393 #define CONFIG_SYS_FLASH_BASE		0xef000000
394 #endif
395 
396 #ifdef CONFIG_PHYS_64BIT
397 #define CONFIG_SYS_FLASH_BASE_PHYS	(0xf00000000ull | CONFIG_SYS_FLASH_BASE)
398 #else
399 #define CONFIG_SYS_FLASH_BASE_PHYS	CONFIG_SYS_FLASH_BASE
400 #endif
401 
402 #define CONFIG_FLASH_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) \
403 	| BR_PS_16 | BR_V)
404 
405 #define CONFIG_FLASH_OR_PRELIM	0xfc000ff7
406 
407 #define CONFIG_SYS_FLASH_BANKS_LIST	{CONFIG_SYS_FLASH_BASE_PHYS}
408 #define CONFIG_SYS_FLASH_QUIET_TEST
409 #define CONFIG_FLASH_SHOW_PROGRESS	45	/* count down from 45/5: 9..1 */
410 
411 #define CONFIG_SYS_MAX_FLASH_BANKS	1	/* number of banks */
412 
413 #undef CONFIG_SYS_FLASH_CHECKSUM
414 #define CONFIG_SYS_FLASH_ERASE_TOUT	60000	/* Flash Erase Timeout (ms) */
415 #define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (ms) */
416 
417 #define CONFIG_FLASH_CFI_DRIVER
418 #define CONFIG_SYS_FLASH_CFI
419 #define CONFIG_SYS_FLASH_EMPTY_INFO
420 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
421 
422 /* Nand Flash */
423 #ifdef CONFIG_NAND_FSL_ELBC
424 #define CONFIG_SYS_NAND_BASE		0xff800000
425 #ifdef CONFIG_PHYS_64BIT
426 #define CONFIG_SYS_NAND_BASE_PHYS	0xfff800000ull
427 #else
428 #define CONFIG_SYS_NAND_BASE_PHYS	CONFIG_SYS_NAND_BASE
429 #endif
430 
431 #define CONFIG_SYS_NAND_BASE_LIST	{ CONFIG_SYS_NAND_BASE }
432 #define CONFIG_SYS_MAX_NAND_DEVICE	1
433 #define CONFIG_CMD_NAND
434 #if defined(CONFIG_TARGET_P1020RDB_PD)
435 #define CONFIG_SYS_NAND_BLOCK_SIZE	(128 * 1024)
436 #else
437 #define CONFIG_SYS_NAND_BLOCK_SIZE	(16 * 1024)
438 #endif
439 
440 #define CONFIG_SYS_NAND_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
441 	| (2<<BR_DECC_SHIFT)	/* Use HW ECC */ \
442 	| BR_PS_8	/* Port Size = 8 bit */ \
443 	| BR_MS_FCM	/* MSEL = FCM */ \
444 	| BR_V)	/* valid */
445 #if defined(CONFIG_TARGET_P1020RDB_PD)
446 #define CONFIG_SYS_NAND_OR_PRELIM	(OR_AM_32KB \
447 	| OR_FCM_PGS	/* Large Page*/ \
448 	| OR_FCM_CSCT \
449 	| OR_FCM_CST \
450 	| OR_FCM_CHT \
451 	| OR_FCM_SCY_1 \
452 	| OR_FCM_TRLX \
453 	| OR_FCM_EHTR)
454 #else
455 #define CONFIG_SYS_NAND_OR_PRELIM	(OR_AM_32KB	/* small page */ \
456 	| OR_FCM_CSCT \
457 	| OR_FCM_CST \
458 	| OR_FCM_CHT \
459 	| OR_FCM_SCY_1 \
460 	| OR_FCM_TRLX \
461 	| OR_FCM_EHTR)
462 #endif
463 #endif /* CONFIG_NAND_FSL_ELBC */
464 
465 #define CONFIG_BOARD_EARLY_INIT_R	/* call board_early_init_r function */
466 
467 #define CONFIG_SYS_INIT_RAM_LOCK
468 #define CONFIG_SYS_INIT_RAM_ADDR	0xffd00000 /* stack in RAM */
469 #ifdef CONFIG_PHYS_64BIT
470 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
471 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR
472 /* The assembler doesn't like typecast */
473 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
474 	((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
475 	  CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
476 #else
477 /* Initial L1 address */
478 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS	CONFIG_SYS_INIT_RAM_ADDR
479 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0
480 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS
481 #endif
482 /* Size of used area in RAM */
483 #define CONFIG_SYS_INIT_RAM_SIZE	0x00004000
484 
485 #define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - \
486 					GENERATED_GBL_DATA_SIZE)
487 #define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
488 
489 #define CONFIG_SYS_MONITOR_LEN	(768 * 1024)
490 #define CONFIG_SYS_MALLOC_LEN	(1024 * 1024)/* Reserved for malloc */
491 
492 #define CONFIG_SYS_CPLD_BASE	0xffa00000
493 #ifdef CONFIG_PHYS_64BIT
494 #define CONFIG_SYS_CPLD_BASE_PHYS	0xfffa00000ull
495 #else
496 #define CONFIG_SYS_CPLD_BASE_PHYS	CONFIG_SYS_CPLD_BASE
497 #endif
498 /* CPLD config size: 1Mb */
499 #define CONFIG_CPLD_BR_PRELIM	(BR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE_PHYS) | \
500 					BR_PS_8 | BR_V)
501 #define CONFIG_CPLD_OR_PRELIM	(0xfff009f7)
502 
503 #define CONFIG_SYS_PMC_BASE	0xff980000
504 #define CONFIG_SYS_PMC_BASE_PHYS	CONFIG_SYS_PMC_BASE
505 #define CONFIG_PMC_BR_PRELIM	(BR_PHYS_ADDR(CONFIG_SYS_PMC_BASE_PHYS) | \
506 					BR_PS_8 | BR_V)
507 #define CONFIG_PMC_OR_PRELIM	(OR_AM_64KB | OR_GPCM_CSNT | OR_GPCM_XACS | \
508 				 OR_GPCM_SCY | OR_GPCM_TRLX | OR_GPCM_EHTR | \
509 				 OR_GPCM_EAD)
510 
511 #ifdef CONFIG_NAND
512 #define CONFIG_SYS_BR0_PRELIM	CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Addr */
513 #define CONFIG_SYS_OR0_PRELIM	CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
514 #define CONFIG_SYS_BR1_PRELIM	CONFIG_FLASH_BR_PRELIM	/* NOR Base Address */
515 #define CONFIG_SYS_OR1_PRELIM	CONFIG_FLASH_OR_PRELIM	/* NOR Options */
516 #else
517 #define CONFIG_SYS_BR0_PRELIM	CONFIG_FLASH_BR_PRELIM	/* NOR Base Address */
518 #define CONFIG_SYS_OR0_PRELIM	CONFIG_FLASH_OR_PRELIM	/* NOR Options */
519 #ifdef CONFIG_NAND_FSL_ELBC
520 #define CONFIG_SYS_BR1_PRELIM	CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Addr */
521 #define CONFIG_SYS_OR1_PRELIM	CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
522 #endif
523 #endif
524 #define CONFIG_SYS_BR3_PRELIM	CONFIG_CPLD_BR_PRELIM	/* CPLD Base Address */
525 #define CONFIG_SYS_OR3_PRELIM	CONFIG_CPLD_OR_PRELIM	/* CPLD Options */
526 
527 /* Vsc7385 switch */
528 #ifdef CONFIG_VSC7385_ENET
529 #define CONFIG_SYS_VSC7385_BASE		0xffb00000
530 
531 #ifdef CONFIG_PHYS_64BIT
532 #define CONFIG_SYS_VSC7385_BASE_PHYS	0xfffb00000ull
533 #else
534 #define CONFIG_SYS_VSC7385_BASE_PHYS	CONFIG_SYS_VSC7385_BASE
535 #endif
536 
537 #define CONFIG_SYS_VSC7385_BR_PRELIM	\
538 	(BR_PHYS_ADDR(CONFIG_SYS_VSC7385_BASE_PHYS) | BR_PS_8 | BR_V)
539 #define CONFIG_SYS_VSC7385_OR_PRELIM	(OR_AM_128KB | OR_GPCM_CSNT | \
540 			OR_GPCM_XACS |  OR_GPCM_SCY_15 | OR_GPCM_SETA | \
541 			OR_GPCM_TRLX |  OR_GPCM_EHTR | OR_GPCM_EAD)
542 
543 #define CONFIG_SYS_BR2_PRELIM	CONFIG_SYS_VSC7385_BR_PRELIM
544 #define CONFIG_SYS_OR2_PRELIM	CONFIG_SYS_VSC7385_OR_PRELIM
545 
546 /* The size of the VSC7385 firmware image */
547 #define CONFIG_VSC7385_IMAGE_SIZE	8192
548 #endif
549 
550 /*
551  * Config the L2 Cache as L2 SRAM
552 */
553 #if defined(CONFIG_SPL_BUILD)
554 #if defined(CONFIG_SDCARD) || defined(CONFIG_SPIFLASH)
555 #define CONFIG_SYS_INIT_L2_ADDR		0xf8f80000
556 #define CONFIG_SYS_INIT_L2_ADDR_PHYS	CONFIG_SYS_INIT_L2_ADDR
557 #define CONFIG_SYS_INIT_L2_END	(CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
558 #define CONFIG_SPL_RELOC_TEXT_BASE	0xf8f81000
559 #define CONFIG_SPL_GD_ADDR		(CONFIG_SYS_INIT_L2_ADDR + 112 * 1024)
560 #define CONFIG_SPL_RELOC_STACK		(CONFIG_SYS_INIT_L2_ADDR + 116 * 1024)
561 #define CONFIG_SPL_RELOC_STACK_SIZE	(32 << 10)
562 #define CONFIG_SPL_RELOC_MALLOC_ADDR	(CONFIG_SYS_INIT_L2_ADDR + 148 * 1024)
563 #if defined(CONFIG_TARGET_P2020RDB)
564 #define CONFIG_SPL_RELOC_MALLOC_SIZE	(364 << 10)
565 #else
566 #define CONFIG_SPL_RELOC_MALLOC_SIZE	(108 << 10)
567 #endif
568 #elif defined(CONFIG_NAND)
569 #ifdef CONFIG_TPL_BUILD
570 #define CONFIG_SYS_INIT_L2_ADDR		0xf8f80000
571 #define CONFIG_SYS_INIT_L2_ADDR_PHYS	CONFIG_SYS_INIT_L2_ADDR
572 #define CONFIG_SYS_INIT_L2_END	(CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
573 #define CONFIG_SPL_RELOC_TEXT_BASE	0xf8f81000
574 #define CONFIG_SPL_RELOC_STACK		(CONFIG_SYS_INIT_L2_ADDR + 192 * 1024)
575 #define CONFIG_SPL_RELOC_MALLOC_ADDR	(CONFIG_SYS_INIT_L2_ADDR + 208 * 1024)
576 #define CONFIG_SPL_RELOC_MALLOC_SIZE	(48 << 10)
577 #define CONFIG_SPL_GD_ADDR		(CONFIG_SYS_INIT_L2_ADDR + 176 * 1024)
578 #else
579 #define CONFIG_SYS_INIT_L2_ADDR		0xf8f80000
580 #define CONFIG_SYS_INIT_L2_ADDR_PHYS	CONFIG_SYS_INIT_L2_ADDR
581 #define CONFIG_SYS_INIT_L2_END	(CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
582 #define CONFIG_SPL_RELOC_TEXT_BASE	(CONFIG_SYS_INIT_L2_END - 0x2000)
583 #define CONFIG_SPL_RELOC_STACK		((CONFIG_SYS_INIT_L2_END - 1) & ~0xF)
584 #endif /* CONFIG_TPL_BUILD */
585 #endif
586 #endif
587 
588 /* Serial Port - controlled on board with jumper J8
589  * open - index 2
590  * shorted - index 1
591  */
592 #define CONFIG_CONS_INDEX		1
593 #undef CONFIG_SERIAL_SOFTWARE_FIFO
594 #define CONFIG_SYS_NS16550_SERIAL
595 #define CONFIG_SYS_NS16550_REG_SIZE	1
596 #define CONFIG_SYS_NS16550_CLK		get_bus_freq(0)
597 #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_INIT_MINIMAL)
598 #define CONFIG_NS16550_MIN_FUNCTIONS
599 #endif
600 
601 #define CONFIG_SYS_BAUDRATE_TABLE	\
602 	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
603 
604 #define CONFIG_SYS_NS16550_COM1	(CONFIG_SYS_CCSRBAR+0x4500)
605 #define CONFIG_SYS_NS16550_COM2	(CONFIG_SYS_CCSRBAR+0x4600)
606 
607 /* I2C */
608 #define CONFIG_SYS_I2C
609 #define CONFIG_SYS_I2C_FSL
610 #define CONFIG_SYS_FSL_I2C_SPEED	400000
611 #define CONFIG_SYS_FSL_I2C_SLAVE	0x7F
612 #define CONFIG_SYS_FSL_I2C_OFFSET	0x3000
613 #define CONFIG_SYS_FSL_I2C2_SPEED	400000
614 #define CONFIG_SYS_FSL_I2C2_SLAVE	0x7F
615 #define CONFIG_SYS_FSL_I2C2_OFFSET	0x3100
616 #define CONFIG_SYS_I2C_NOPROBES		{ {0, 0x29} }
617 #define CONFIG_SYS_I2C_EEPROM_ADDR	0x52
618 #define CONFIG_SYS_SPD_BUS_NUM		1 /* For rom_loc and flash bank */
619 
620 /*
621  * I2C2 EEPROM
622  */
623 #undef CONFIG_ID_EEPROM
624 
625 #define CONFIG_RTC_PT7C4338
626 #define CONFIG_SYS_I2C_RTC_ADDR		0x68
627 #define CONFIG_SYS_I2C_PCA9557_ADDR	0x18
628 
629 /* enable read and write access to EEPROM */
630 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
631 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
632 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
633 
634 /*
635  * eSPI - Enhanced SPI
636  */
637 #define CONFIG_HARD_SPI
638 
639 #if defined(CONFIG_SPI_FLASH)
640 #define CONFIG_SF_DEFAULT_SPEED	10000000
641 #define CONFIG_SF_DEFAULT_MODE	0
642 #endif
643 
644 #if defined(CONFIG_PCI)
645 /*
646  * General PCI
647  * Memory space is mapped 1-1, but I/O space must start from 0.
648  */
649 
650 /* controller 2, direct to uli, tgtid 2, Base address 9000 */
651 #define CONFIG_SYS_PCIE2_NAME		"PCIe SLOT"
652 #define CONFIG_SYS_PCIE2_MEM_VIRT	0xa0000000
653 #ifdef CONFIG_PHYS_64BIT
654 #define CONFIG_SYS_PCIE2_MEM_BUS	0xc0000000
655 #define CONFIG_SYS_PCIE2_MEM_PHYS	0xc20000000ull
656 #else
657 #define CONFIG_SYS_PCIE2_MEM_BUS	0xa0000000
658 #define CONFIG_SYS_PCIE2_MEM_PHYS	0xa0000000
659 #endif
660 #define CONFIG_SYS_PCIE2_MEM_SIZE	0x20000000	/* 512M */
661 #define CONFIG_SYS_PCIE2_IO_VIRT	0xffc10000
662 #define CONFIG_SYS_PCIE2_IO_BUS		0x00000000
663 #ifdef CONFIG_PHYS_64BIT
664 #define CONFIG_SYS_PCIE2_IO_PHYS	0xfffc10000ull
665 #else
666 #define CONFIG_SYS_PCIE2_IO_PHYS	0xffc10000
667 #endif
668 #define CONFIG_SYS_PCIE2_IO_SIZE	0x00010000	/* 64k */
669 
670 /* controller 1, Slot 2, tgtid 1, Base address a000 */
671 #define CONFIG_SYS_PCIE1_NAME		"mini PCIe SLOT"
672 #define CONFIG_SYS_PCIE1_MEM_VIRT	0x80000000
673 #ifdef CONFIG_PHYS_64BIT
674 #define CONFIG_SYS_PCIE1_MEM_BUS	0x80000000
675 #define CONFIG_SYS_PCIE1_MEM_PHYS	0xc00000000ull
676 #else
677 #define CONFIG_SYS_PCIE1_MEM_BUS	0x80000000
678 #define CONFIG_SYS_PCIE1_MEM_PHYS	0x80000000
679 #endif
680 #define CONFIG_SYS_PCIE1_MEM_SIZE	0x20000000	/* 512M */
681 #define CONFIG_SYS_PCIE1_IO_VIRT	0xffc00000
682 #define CONFIG_SYS_PCIE1_IO_BUS		0x00000000
683 #ifdef CONFIG_PHYS_64BIT
684 #define CONFIG_SYS_PCIE1_IO_PHYS	0xfffc00000ull
685 #else
686 #define CONFIG_SYS_PCIE1_IO_PHYS	0xffc00000
687 #endif
688 #define CONFIG_SYS_PCIE1_IO_SIZE	0x00010000	/* 64k */
689 
690 #define CONFIG_CMD_PCI
691 
692 #define CONFIG_PCI_SCAN_SHOW	/* show pci devices on startup */
693 #endif /* CONFIG_PCI */
694 
695 #if defined(CONFIG_TSEC_ENET)
696 #define CONFIG_MII		/* MII PHY management */
697 #define CONFIG_TSEC1
698 #define CONFIG_TSEC1_NAME	"eTSEC1"
699 #define CONFIG_TSEC2
700 #define CONFIG_TSEC2_NAME	"eTSEC2"
701 #define CONFIG_TSEC3
702 #define CONFIG_TSEC3_NAME	"eTSEC3"
703 
704 #define TSEC1_PHY_ADDR	2
705 #define TSEC2_PHY_ADDR	0
706 #define TSEC3_PHY_ADDR	1
707 
708 #define TSEC1_FLAGS	(TSEC_GIGABIT | TSEC_REDUCED)
709 #define TSEC2_FLAGS	(TSEC_GIGABIT | TSEC_REDUCED)
710 #define TSEC3_FLAGS	(TSEC_GIGABIT | TSEC_REDUCED)
711 
712 #define TSEC1_PHYIDX	0
713 #define TSEC2_PHYIDX	0
714 #define TSEC3_PHYIDX	0
715 
716 #define CONFIG_ETHPRIME	"eTSEC1"
717 
718 #define CONFIG_PHY_GIGE	1	/* Include GbE speed/duplex detection */
719 
720 #define CONFIG_HAS_ETH0
721 #define CONFIG_HAS_ETH1
722 #define CONFIG_HAS_ETH2
723 #endif /* CONFIG_TSEC_ENET */
724 
725 #ifdef CONFIG_QE
726 /* QE microcode/firmware address */
727 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR
728 #define CONFIG_SYS_QE_FW_ADDR	0xefec0000
729 #define CONFIG_SYS_QE_FMAN_FW_LENGTH	0x10000
730 #endif /* CONFIG_QE */
731 
732 #ifdef CONFIG_TARGET_P1025RDB
733 /*
734  * QE UEC ethernet configuration
735  */
736 #define CONFIG_MIIM_ADDRESS	(CONFIG_SYS_CCSRBAR + 0x82120)
737 
738 #undef CONFIG_UEC_ETH
739 #define CONFIG_PHY_MODE_NEED_CHANGE
740 
741 #define CONFIG_UEC_ETH1	/* ETH1 */
742 #define CONFIG_HAS_ETH0
743 
744 #ifdef CONFIG_UEC_ETH1
745 #define CONFIG_SYS_UEC1_UCC_NUM	0	/* UCC1 */
746 #define CONFIG_SYS_UEC1_RX_CLK	QE_CLK12 /* CLK12 for MII */
747 #define CONFIG_SYS_UEC1_TX_CLK	QE_CLK9 /* CLK9 for MII */
748 #define CONFIG_SYS_UEC1_ETH_TYPE	FAST_ETH
749 #define CONFIG_SYS_UEC1_PHY_ADDR	0x0	/* 0x0 for MII */
750 #define CONFIG_SYS_UEC1_INTERFACE_TYPE PHY_INTERFACE_MODE_RMII
751 #define CONFIG_SYS_UEC1_INTERFACE_SPEED	100
752 #endif /* CONFIG_UEC_ETH1 */
753 
754 #define CONFIG_UEC_ETH5	/* ETH5 */
755 #define CONFIG_HAS_ETH1
756 
757 #ifdef CONFIG_UEC_ETH5
758 #define CONFIG_SYS_UEC5_UCC_NUM	4	/* UCC5 */
759 #define CONFIG_SYS_UEC5_RX_CLK	QE_CLK_NONE
760 #define CONFIG_SYS_UEC5_TX_CLK	QE_CLK13 /* CLK 13 for RMII */
761 #define CONFIG_SYS_UEC5_ETH_TYPE	FAST_ETH
762 #define CONFIG_SYS_UEC5_PHY_ADDR	0x3	/* 0x3 for RMII */
763 #define CONFIG_SYS_UEC5_INTERFACE_TYPE PHY_INTERFACE_MODE_RMII
764 #define CONFIG_SYS_UEC5_INTERFACE_SPEED	100
765 #endif /* CONFIG_UEC_ETH5 */
766 #endif /* CONFIG_TARGET_P1025RDB */
767 
768 /*
769  * Environment
770  */
771 #ifdef CONFIG_SPIFLASH
772 #define CONFIG_ENV_SPI_BUS	0
773 #define CONFIG_ENV_SPI_CS	0
774 #define CONFIG_ENV_SPI_MAX_HZ	10000000
775 #define CONFIG_ENV_SPI_MODE	0
776 #define CONFIG_ENV_SIZE		0x2000	/* 8KB */
777 #define CONFIG_ENV_OFFSET	0x100000	/* 1MB */
778 #define CONFIG_ENV_SECT_SIZE	0x10000
779 #elif defined(CONFIG_SDCARD)
780 #define CONFIG_FSL_FIXED_MMC_LOCATION
781 #define CONFIG_ENV_SIZE		0x2000
782 #define CONFIG_SYS_MMC_ENV_DEV	0
783 #elif defined(CONFIG_NAND)
784 #ifdef CONFIG_TPL_BUILD
785 #define CONFIG_ENV_SIZE		0x2000
786 #define CONFIG_ENV_ADDR		(CONFIG_SYS_INIT_L2_ADDR + (160 << 10))
787 #else
788 #define CONFIG_ENV_SIZE		CONFIG_SYS_NAND_BLOCK_SIZE
789 #endif
790 #define CONFIG_ENV_OFFSET	(1024 * 1024)
791 #define CONFIG_ENV_RANGE	(3 * CONFIG_ENV_SIZE)
792 #elif defined(CONFIG_SYS_RAMBOOT)
793 #define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE - 0x1000)
794 #define CONFIG_ENV_SIZE		0x2000
795 #else
796 #define CONFIG_ENV_ADDR	(CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
797 #define CONFIG_ENV_SIZE		0x2000
798 #define CONFIG_ENV_SECT_SIZE	0x20000 /* 128K (one sector) */
799 #endif
800 
801 #define CONFIG_LOADS_ECHO		/* echo on for serial download */
802 #define CONFIG_SYS_LOADS_BAUD_CHANGE	/* allow baudrate change */
803 
804 /*
805  * Command line configuration.
806  */
807 #define CONFIG_CMD_REGINFO
808 
809 /*
810  * USB
811  */
812 #define CONFIG_HAS_FSL_DR_USB
813 
814 #if defined(CONFIG_HAS_FSL_DR_USB)
815 #ifdef CONFIG_USB_EHCI_HCD
816 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
817 #define CONFIG_USB_EHCI_FSL
818 #endif
819 #endif
820 
821 #if defined(CONFIG_TARGET_P1020RDB_PD)
822 #define CONFIG_USB_MAX_CONTROLLER_COUNT	1
823 #endif
824 
825 #ifdef CONFIG_MMC
826 #define CONFIG_FSL_ESDHC
827 #define CONFIG_SYS_FSL_ESDHC_ADDR	CONFIG_SYS_MPC85xx_ESDHC_ADDR
828 #endif
829 
830 #undef CONFIG_WATCHDOG	/* watchdog disabled */
831 
832 /*
833  * Miscellaneous configurable options
834  */
835 #define CONFIG_SYS_LONGHELP			/* undef to save memory */
836 #define CONFIG_CMDLINE_EDITING			/* Command-line editing */
837 #define CONFIG_SYS_LOAD_ADDR	0x2000000	/* default load address */
838 #if defined(CONFIG_CMD_KGDB)
839 #define CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size */
840 #else
841 #define CONFIG_SYS_CBSIZE	256		/* Console I/O Buffer Size */
842 #endif
843 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
844 	/* Print Buffer Size */
845 #define CONFIG_SYS_MAXARGS	16	/* max number of command args */
846 #define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */
847 
848 /*
849  * For booting Linux, the board info and command line data
850  * have to be in the first 64 MB of memory, since this is
851  * the maximum mapped by the Linux kernel during initialization.
852  */
853 #define CONFIG_SYS_BOOTMAPSZ	(64 << 20)	/* Initial Memory for Linux*/
854 #define CONFIG_SYS_BOOTM_LEN	(64 << 20)	/* Increase max gunzip size */
855 
856 #if defined(CONFIG_CMD_KGDB)
857 #define CONFIG_KGDB_BAUDRATE	230400	/* speed to run kgdb serial port */
858 #endif
859 
860 /*
861  * Environment Configuration
862  */
863 #define CONFIG_HOSTNAME		unknown
864 #define CONFIG_ROOTPATH		"/opt/nfsroot"
865 #define CONFIG_BOOTFILE		"uImage"
866 #define CONFIG_UBOOTPATH	u-boot.bin /* U-Boot image on TFTP server */
867 
868 /* default location for tftp and bootm */
869 #define CONFIG_LOADADDR	1000000
870 
871 #define CONFIG_BOOTARGS	/* the boot command will set bootargs */
872 
873 #ifdef __SW_BOOT_NOR
874 #define __NOR_RST_CMD	\
875 norboot=i2c dev 1; i2c mw 18 1 __SW_BOOT_NOR 1; \
876 i2c mw 18 3 __SW_BOOT_MASK 1; reset
877 #endif
878 #ifdef __SW_BOOT_SPI
879 #define __SPI_RST_CMD	\
880 spiboot=i2c dev 1; i2c mw 18 1 __SW_BOOT_SPI 1; \
881 i2c mw 18 3 __SW_BOOT_MASK 1; reset
882 #endif
883 #ifdef __SW_BOOT_SD
884 #define __SD_RST_CMD	\
885 sdboot=i2c dev 1; i2c mw 18 1 __SW_BOOT_SD 1; \
886 i2c mw 18 3 __SW_BOOT_MASK 1; reset
887 #endif
888 #ifdef __SW_BOOT_NAND
889 #define __NAND_RST_CMD	\
890 nandboot=i2c dev 1; i2c mw 18 1 __SW_BOOT_NAND 1; \
891 i2c mw 18 3 __SW_BOOT_MASK 1; reset
892 #endif
893 #ifdef __SW_BOOT_PCIE
894 #define __PCIE_RST_CMD	\
895 pciboot=i2c dev 1; i2c mw 18 1 __SW_BOOT_PCIE 1; \
896 i2c mw 18 3 __SW_BOOT_MASK 1; reset
897 #endif
898 
899 #define	CONFIG_EXTRA_ENV_SETTINGS	\
900 "netdev=eth0\0"	\
901 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0"	\
902 "loadaddr=1000000\0"	\
903 "bootfile=uImage\0"	\
904 "tftpflash=tftpboot $loadaddr $uboot; "	\
905 	"protect off " __stringify(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
906 	"erase " __stringify(CONFIG_SYS_TEXT_BASE) " +$filesize; "	\
907 	"cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) " $filesize; " \
908 	"protect on " __stringify(CONFIG_SYS_TEXT_BASE) " +$filesize; "	\
909 	"cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) " $filesize\0" \
910 "hwconfig=usb1:dr_mode=host,phy_type=ulpi\0"    \
911 "consoledev=ttyS0\0"	\
912 "ramdiskaddr=2000000\0"	\
913 "ramdiskfile=rootfs.ext2.gz.uboot\0"	\
914 "fdtaddr=1e00000\0"	\
915 "bdev=sda1\0" \
916 "jffs2nor=mtdblock3\0"	\
917 "norbootaddr=ef080000\0"	\
918 "norfdtaddr=ef040000\0"	\
919 "jffs2nand=mtdblock9\0"	\
920 "nandbootaddr=100000\0"	\
921 "nandfdtaddr=80000\0"		\
922 "ramdisk_size=120000\0"	\
923 "map_lowernorbank=i2c dev 1; i2c mw 18 1 02 1; i2c mw 18 3 fd 1\0" \
924 "map_uppernorbank=i2c dev 1; i2c mw 18 1 00 1; i2c mw 18 3 fd 1\0" \
925 __stringify(__NOR_RST_CMD)"\0" \
926 __stringify(__SPI_RST_CMD)"\0" \
927 __stringify(__SD_RST_CMD)"\0" \
928 __stringify(__NAND_RST_CMD)"\0" \
929 __stringify(__PCIE_RST_CMD)"\0"
930 
931 #define CONFIG_NFSBOOTCOMMAND	\
932 "setenv bootargs root=/dev/nfs rw "	\
933 "nfsroot=$serverip:$rootpath "	\
934 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
935 "console=$consoledev,$baudrate $othbootargs;" \
936 "tftp $loadaddr $bootfile;"	\
937 "tftp $fdtaddr $fdtfile;"	\
938 "bootm $loadaddr - $fdtaddr"
939 
940 #define CONFIG_HDBOOT	\
941 "setenv bootargs root=/dev/$bdev rw rootdelay=30 "	\
942 "console=$consoledev,$baudrate $othbootargs;" \
943 "usb start;"	\
944 "ext2load usb 0:1 $loadaddr /boot/$bootfile;"	\
945 "ext2load usb 0:1 $fdtaddr /boot/$fdtfile;"	\
946 "bootm $loadaddr - $fdtaddr"
947 
948 #define CONFIG_USB_FAT_BOOT	\
949 "setenv bootargs root=/dev/ram rw "	\
950 "console=$consoledev,$baudrate $othbootargs " \
951 "ramdisk_size=$ramdisk_size;"	\
952 "usb start;"	\
953 "fatload usb 0:2 $loadaddr $bootfile;"	\
954 "fatload usb 0:2 $fdtaddr $fdtfile;"	\
955 "fatload usb 0:2 $ramdiskaddr $ramdiskfile;"	\
956 "bootm $loadaddr $ramdiskaddr $fdtaddr"
957 
958 #define CONFIG_USB_EXT2_BOOT	\
959 "setenv bootargs root=/dev/ram rw "	\
960 "console=$consoledev,$baudrate $othbootargs " \
961 "ramdisk_size=$ramdisk_size;"	\
962 "usb start;"	\
963 "ext2load usb 0:4 $loadaddr $bootfile;"	\
964 "ext2load usb 0:4 $fdtaddr $fdtfile;" \
965 "ext2load usb 0:4 $ramdiskaddr $ramdiskfile;" \
966 "bootm $loadaddr $ramdiskaddr $fdtaddr"
967 
968 #define CONFIG_NORBOOT	\
969 "setenv bootargs root=/dev/$jffs2nor rw "	\
970 "console=$consoledev,$baudrate rootfstype=jffs2 $othbootargs;"	\
971 "bootm $norbootaddr - $norfdtaddr"
972 
973 #define CONFIG_RAMBOOTCOMMAND	\
974 "setenv bootargs root=/dev/ram rw "	\
975 "console=$consoledev,$baudrate $othbootargs " \
976 "ramdisk_size=$ramdisk_size;"	\
977 "tftp $ramdiskaddr $ramdiskfile;"	\
978 "tftp $loadaddr $bootfile;"	\
979 "tftp $fdtaddr $fdtfile;"	\
980 "bootm $loadaddr $ramdiskaddr $fdtaddr"
981 
982 #define CONFIG_BOOTCOMMAND	CONFIG_HDBOOT
983 
984 #endif /* __CONFIG_H */
985