1 /* 2 * Copyright 2010-2011 Freescale Semiconductor, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 /* 8 * QorIQ RDB boards configuration file 9 */ 10 #ifndef __CONFIG_H 11 #define __CONFIG_H 12 13 #ifdef CONFIG_36BIT 14 #define CONFIG_PHYS_64BIT 15 #endif 16 17 #if defined(CONFIG_P1020MBG) 18 #define CONFIG_BOARDNAME "P1020MBG-PC" 19 #define CONFIG_P1020 20 #define CONFIG_VSC7385_ENET 21 #define CONFIG_SLIC 22 #define __SW_BOOT_MASK 0x03 23 #define __SW_BOOT_NOR 0xe4 24 #define __SW_BOOT_SD 0x54 25 #define CONFIG_SYS_L2_SIZE (256 << 10) 26 #endif 27 28 #if defined(CONFIG_P1020UTM) 29 #define CONFIG_BOARDNAME "P1020UTM-PC" 30 #define CONFIG_P1020 31 #define __SW_BOOT_MASK 0x03 32 #define __SW_BOOT_NOR 0xe0 33 #define __SW_BOOT_SD 0x50 34 #define CONFIG_SYS_L2_SIZE (256 << 10) 35 #endif 36 37 #if defined(CONFIG_P1020RDB_PC) 38 #define CONFIG_BOARDNAME "P1020RDB-PC" 39 #define CONFIG_NAND_FSL_ELBC 40 #define CONFIG_P1020 41 #define CONFIG_SPI_FLASH 42 #define CONFIG_VSC7385_ENET 43 #define CONFIG_SLIC 44 #define __SW_BOOT_MASK 0x03 45 #define __SW_BOOT_NOR 0x5c 46 #define __SW_BOOT_SPI 0x1c 47 #define __SW_BOOT_SD 0x9c 48 #define __SW_BOOT_NAND 0xec 49 #define __SW_BOOT_PCIE 0x6c 50 #define CONFIG_SYS_L2_SIZE (256 << 10) 51 #endif 52 53 /* 54 * P1020RDB-PD board has user selectable switches for evaluating different 55 * frequency and boot options for the P1020 device. The table that 56 * follow describe the available options. The front six binary number was in 57 * accordance with SW3[1:6]. 58 * 111101 533 533 267 667 NOR Core0 boot; Core1 hold-off 59 * 101101 667 667 333 667 NOR Core0 boot; Core1 hold-off 60 * 011001 800 800 400 667 NOR Core0 boot; Core1 hold-off 61 * 001001 800 800 400 667 SD/MMC Core0 boot; Core1 hold-off 62 * 001101 800 800 400 667 SPI Core0 boot; Core1 hold-off 63 * 010001 800 800 400 667 NAND Core0 boot; Core1 hold-off 64 * 011101 800 800 400 667 PCIe-2 Core0 boot; Core1 hold-off 65 */ 66 #if defined(CONFIG_P1020RDB_PD) 67 #define CONFIG_BOARDNAME "P1020RDB-PD" 68 #define CONFIG_NAND_FSL_ELBC 69 #define CONFIG_P1020 70 #define CONFIG_SPI_FLASH 71 #define CONFIG_VSC7385_ENET 72 #define CONFIG_SLIC 73 #define __SW_BOOT_MASK 0x03 74 #define __SW_BOOT_NOR 0x64 75 #define __SW_BOOT_SPI 0x34 76 #define __SW_BOOT_SD 0x24 77 #define __SW_BOOT_NAND 0x44 78 #define __SW_BOOT_PCIE 0x74 79 #define CONFIG_SYS_L2_SIZE (256 << 10) 80 #endif 81 82 #if defined(CONFIG_P1021RDB) 83 #define CONFIG_BOARDNAME "P1021RDB-PC" 84 #define CONFIG_NAND_FSL_ELBC 85 #define CONFIG_P1021 86 #define CONFIG_QE 87 #define CONFIG_SPI_FLASH 88 #define CONFIG_VSC7385_ENET 89 #define CONFIG_SYS_LBC_LBCR 0x00080000 /* Implement conversion of 90 addresses in the LBC */ 91 #define __SW_BOOT_MASK 0x03 92 #define __SW_BOOT_NOR 0x5c 93 #define __SW_BOOT_SPI 0x1c 94 #define __SW_BOOT_SD 0x9c 95 #define __SW_BOOT_NAND 0xec 96 #define __SW_BOOT_PCIE 0x6c 97 #define CONFIG_SYS_L2_SIZE (256 << 10) 98 #endif 99 100 #if defined(CONFIG_P1024RDB) 101 #define CONFIG_BOARDNAME "P1024RDB" 102 #define CONFIG_NAND_FSL_ELBC 103 #define CONFIG_P1024 104 #define CONFIG_SLIC 105 #define CONFIG_SPI_FLASH 106 #define __SW_BOOT_MASK 0xf3 107 #define __SW_BOOT_NOR 0x00 108 #define __SW_BOOT_SPI 0x08 109 #define __SW_BOOT_SD 0x04 110 #define __SW_BOOT_NAND 0x0c 111 #define CONFIG_SYS_L2_SIZE (256 << 10) 112 #endif 113 114 #if defined(CONFIG_P1025RDB) 115 #define CONFIG_BOARDNAME "P1025RDB" 116 #define CONFIG_NAND_FSL_ELBC 117 #define CONFIG_P1025 118 #define CONFIG_QE 119 #define CONFIG_SLIC 120 #define CONFIG_SPI_FLASH 121 122 #define CONFIG_SYS_LBC_LBCR 0x00080000 /* Implement conversion of 123 addresses in the LBC */ 124 #define __SW_BOOT_MASK 0xf3 125 #define __SW_BOOT_NOR 0x00 126 #define __SW_BOOT_SPI 0x08 127 #define __SW_BOOT_SD 0x04 128 #define __SW_BOOT_NAND 0x0c 129 #define CONFIG_SYS_L2_SIZE (256 << 10) 130 #endif 131 132 #if defined(CONFIG_P2020RDB) 133 #define CONFIG_BOARDNAME "P2020RDB-PCA" 134 #define CONFIG_NAND_FSL_ELBC 135 #define CONFIG_P2020 136 #define CONFIG_SPI_FLASH 137 #define CONFIG_VSC7385_ENET 138 #define __SW_BOOT_MASK 0x03 139 #define __SW_BOOT_NOR 0xc8 140 #define __SW_BOOT_SPI 0x28 141 #define __SW_BOOT_SD 0x68 /* or 0x18 */ 142 #define __SW_BOOT_NAND 0xe8 143 #define __SW_BOOT_PCIE 0xa8 144 #define CONFIG_SYS_L2_SIZE (512 << 10) 145 #endif 146 147 #if CONFIG_SYS_L2_SIZE >= (512 << 10) 148 /* must be 32-bit */ 149 #define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000 150 #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR 151 #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) 152 #endif 153 154 #ifdef CONFIG_SDCARD 155 #define CONFIG_RAMBOOT_SDCARD 156 #define CONFIG_SYS_RAMBOOT 157 #define CONFIG_SYS_EXTRA_ENV_RELOC 158 #define CONFIG_SYS_TEXT_BASE 0x11000000 159 #define CONFIG_RESET_VECTOR_ADDRESS 0x1107fffc 160 #endif 161 162 #ifdef CONFIG_SPIFLASH 163 #define CONFIG_RAMBOOT_SPIFLASH 164 #define CONFIG_SYS_RAMBOOT 165 #define CONFIG_SYS_EXTRA_ENV_RELOC 166 #define CONFIG_SYS_TEXT_BASE 0x11000000 167 #define CONFIG_RESET_VECTOR_ADDRESS 0x1107fffc 168 #endif 169 170 #ifdef CONFIG_NAND 171 #define CONFIG_SPL 172 #define CONFIG_SPL_INIT_MINIMAL 173 #define CONFIG_SPL_SERIAL_SUPPORT 174 #define CONFIG_SPL_NAND_SUPPORT 175 #define CONFIG_SPL_NAND_MINIMAL 176 #define CONFIG_SPL_FLUSH_IMAGE 177 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 178 179 #define CONFIG_SPL_TEXT_BASE 0xfffff000 180 #define CONFIG_SPL_MAX_SIZE 4096 181 182 #ifdef CONFIG_SYS_INIT_L2_ADDR 183 /* We multiply CONFIG_SPL_MAX_SIZE by two to leave some room for BSS. */ 184 #define CONFIG_SYS_TEXT_BASE 0xf8f82000 185 #define CONFIG_SPL_RELOC_TEXT_BASE \ 186 (CONFIG_SYS_INIT_L2_END - CONFIG_SPL_MAX_SIZE * 2) 187 #define CONFIG_SPL_RELOC_STACK \ 188 (CONFIG_SYS_INIT_L2_END - CONFIG_SPL_MAX_SIZE * 2) 189 #define CONFIG_SYS_NAND_U_BOOT_DST (CONFIG_SYS_INIT_L2_ADDR) 190 #define CONFIG_SYS_NAND_U_BOOT_START \ 191 (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SPL_MAX_SIZE) 192 #else 193 #define CONFIG_SYS_TEXT_BASE 0x00201000 194 #define CONFIG_SPL_RELOC_TEXT_BASE 0x00100000 195 #define CONFIG_SPL_RELOC_STACK 0x00100000 196 #define CONFIG_SYS_NAND_U_BOOT_DST (0x00200000 - CONFIG_SPL_MAX_SIZE) 197 #define CONFIG_SYS_NAND_U_BOOT_START 0x00200000 198 #endif 199 200 #define CONFIG_SYS_NAND_U_BOOT_SIZE ((512 << 10) - 0x2000) 201 #define CONFIG_SYS_NAND_U_BOOT_OFFS 0 202 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds" 203 #endif 204 205 #ifndef CONFIG_SYS_TEXT_BASE 206 #define CONFIG_SYS_TEXT_BASE 0xeff80000 207 #endif 208 209 #ifndef CONFIG_RESET_VECTOR_ADDRESS 210 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc 211 #endif 212 213 #ifndef CONFIG_SYS_MONITOR_BASE 214 #ifdef CONFIG_SPL_BUILD 215 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE 216 #else 217 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 218 #endif 219 #endif 220 221 /* High Level Configuration Options */ 222 #define CONFIG_BOOKE 223 #define CONFIG_E500 224 #define CONFIG_MPC85xx 225 226 #define CONFIG_MP 227 228 #define CONFIG_FSL_ELBC 229 #define CONFIG_PCI 230 #define CONFIG_PCIE1 /* PCIE controler 1 (slot 1) */ 231 #define CONFIG_PCIE2 /* PCIE controler 2 (slot 2) */ 232 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ 233 #define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */ 234 #define CONFIG_FSL_PCIE_RESET /* need PCIe reset errata */ 235 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ 236 237 #define CONFIG_FSL_LAW 238 #define CONFIG_TSEC_ENET /* tsec ethernet support */ 239 #define CONFIG_ENV_OVERWRITE 240 241 #define CONFIG_CMD_SATA 242 #define CONFIG_SATA_SIL 243 #define CONFIG_SYS_SATA_MAX_DEVICE 2 244 #define CONFIG_LIBATA 245 #define CONFIG_LBA48 246 247 #if defined(CONFIG_P2020RDB) 248 #define CONFIG_SYS_CLK_FREQ 100000000 249 #else 250 #define CONFIG_SYS_CLK_FREQ 66666666 251 #endif 252 #define CONFIG_DDR_CLK_FREQ 66666666 253 254 #define CONFIG_HWCONFIG 255 /* 256 * These can be toggled for performance analysis, otherwise use default. 257 */ 258 #define CONFIG_L2_CACHE 259 #define CONFIG_BTB 260 261 #define CONFIG_BOARD_EARLY_INIT_F /* Call board_pre_init */ 262 263 #define CONFIG_ENABLE_36BIT_PHYS 264 265 #ifdef CONFIG_PHYS_64BIT 266 #define CONFIG_ADDR_MAP 1 267 #define CONFIG_SYS_NUM_ADDR_MAP 16 /* number of TLB1 entries */ 268 #endif 269 270 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ 271 #define CONFIG_SYS_MEMTEST_END 0x1fffffff 272 #define CONFIG_PANIC_HANG /* do not reset board on panic */ 273 274 #define CONFIG_SYS_CCSRBAR 0xffe00000 275 #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR 276 277 /* IN case of NAND bootloader relocate CCSRBAR in RAMboot code not in the 4k 278 SPL code*/ 279 #ifdef CONFIG_SPL_BUILD 280 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE 281 #endif 282 283 /* DDR Setup */ 284 #define CONFIG_FSL_DDR3 285 #define CONFIG_SYS_DDR_RAW_TIMING 286 #define CONFIG_DDR_SPD 287 #define CONFIG_SYS_SPD_BUS_NUM 1 288 #define SPD_EEPROM_ADDRESS 0x52 289 #undef CONFIG_FSL_DDR_INTERACTIVE 290 291 #if (defined(CONFIG_P1020MBG) || defined(CONFIG_P1020RDB_PD)) 292 #define CONFIG_SYS_SDRAM_SIZE_LAW LAW_SIZE_2G 293 #define CONFIG_CHIP_SELECTS_PER_CTRL 2 294 #else 295 #define CONFIG_SYS_SDRAM_SIZE_LAW LAW_SIZE_1G 296 #define CONFIG_CHIP_SELECTS_PER_CTRL 1 297 #endif 298 #define CONFIG_SYS_SDRAM_SIZE (1u << (CONFIG_SYS_SDRAM_SIZE_LAW - 19)) 299 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 300 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 301 302 #define CONFIG_NUM_DDR_CONTROLLERS 1 303 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 304 305 /* Default settings for DDR3 */ 306 #ifndef CONFIG_P2020RDB 307 #define CONFIG_SYS_DDR_CS0_BNDS 0x0000003f 308 #define CONFIG_SYS_DDR_CS0_CONFIG 0x80014302 309 #define CONFIG_SYS_DDR_CS0_CONFIG_2 0x00000000 310 #define CONFIG_SYS_DDR_CS1_BNDS 0x0040007f 311 #define CONFIG_SYS_DDR_CS1_CONFIG 0x80014302 312 #define CONFIG_SYS_DDR_CS1_CONFIG_2 0x00000000 313 314 #define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef 315 #define CONFIG_SYS_DDR_INIT_ADDR 0x00000000 316 #define CONFIG_SYS_DDR_INIT_EXT_ADDR 0x00000000 317 #define CONFIG_SYS_DDR_MODE_CONTROL 0x00000000 318 319 #define CONFIG_SYS_DDR_ZQ_CONTROL 0x89080600 320 #define CONFIG_SYS_DDR_WRLVL_CONTROL 0x8655A608 321 #define CONFIG_SYS_DDR_SR_CNTR 0x00000000 322 #define CONFIG_SYS_DDR_RCW_1 0x00000000 323 #define CONFIG_SYS_DDR_RCW_2 0x00000000 324 #define CONFIG_SYS_DDR_CONTROL 0xC70C0000 /* Type = DDR3 */ 325 #define CONFIG_SYS_DDR_CONTROL_2 0x04401050 326 #define CONFIG_SYS_DDR_TIMING_4 0x00220001 327 #define CONFIG_SYS_DDR_TIMING_5 0x03402400 328 329 #define CONFIG_SYS_DDR_TIMING_3 0x00020000 330 #define CONFIG_SYS_DDR_TIMING_0 0x00330004 331 #define CONFIG_SYS_DDR_TIMING_1 0x6f6B4846 332 #define CONFIG_SYS_DDR_TIMING_2 0x0FA8C8CF 333 #define CONFIG_SYS_DDR_CLK_CTRL 0x03000000 334 #define CONFIG_SYS_DDR_MODE_1 0x40461520 335 #define CONFIG_SYS_DDR_MODE_2 0x8000c000 336 #define CONFIG_SYS_DDR_INTERVAL 0x0C300000 337 #endif 338 339 #undef CONFIG_CLOCKS_IN_MHZ 340 341 /* 342 * Memory map 343 * 344 * 0x0000_0000 0x7fff_ffff DDR Up to 2GB cacheable 345 * 0x8000_0000 0xdfff_ffff PCI Express Mem 1.5G non-cacheable(PCIe * 3) 346 * 0xec00_0000 0xefff_ffff NOR flash Up to 64M non-cacheable CS0/1 347 * 0xf8f8_0000 0xf8ff_ffff L2 SRAM Up to 512K cacheable 348 * (early boot only) 349 * 0xff80_0000 0xff80_7fff NAND flash 32K non-cacheable CS1/0 350 * 0xff98_0000 0xff98_ffff PMC 64K non-cacheable CS2 351 * 0xffa0_0000 0xffaf_ffff CPLD 1M non-cacheable CS3 352 * 0xffb0_0000 0xffbf_ffff VSC7385 switch 1M non-cacheable CS2 353 * 0xffc0_0000 0xffc3_ffff PCI IO range 256k non-cacheable 354 * 0xffd0_0000 0xffd0_3fff L1 for stack 16K cacheable 355 * 0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable 356 */ 357 358 359 /* 360 * Local Bus Definitions 361 */ 362 #if (defined(CONFIG_P1020MBG) || defined(CONFIG_P1020RDB_PD)) 363 #define CONFIG_SYS_MAX_FLASH_SECT 512 /* 64M */ 364 #define CONFIG_SYS_FLASH_BASE 0xec000000 365 #elif defined(CONFIG_P1020UTM) 366 #define CONFIG_SYS_MAX_FLASH_SECT 256 /* 32M */ 367 #define CONFIG_SYS_FLASH_BASE 0xee000000 368 #else 369 #define CONFIG_SYS_MAX_FLASH_SECT 128 /* 16M */ 370 #define CONFIG_SYS_FLASH_BASE 0xef000000 371 #endif 372 373 374 #ifdef CONFIG_PHYS_64BIT 375 #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE) 376 #else 377 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE 378 #endif 379 380 #define CONFIG_FLASH_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) \ 381 | BR_PS_16 | BR_V) 382 383 #define CONFIG_FLASH_OR_PRELIM 0xfc000ff7 384 385 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS} 386 #define CONFIG_SYS_FLASH_QUIET_TEST 387 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 388 389 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ 390 391 #undef CONFIG_SYS_FLASH_CHECKSUM 392 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 393 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 394 395 #define CONFIG_FLASH_CFI_DRIVER 396 #define CONFIG_SYS_FLASH_CFI 397 #define CONFIG_SYS_FLASH_EMPTY_INFO 398 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 399 400 /* Nand Flash */ 401 #ifdef CONFIG_NAND_FSL_ELBC 402 #define CONFIG_SYS_NAND_BASE 0xff800000 403 #ifdef CONFIG_PHYS_64BIT 404 #define CONFIG_SYS_NAND_BASE_PHYS 0xfff800000ull 405 #else 406 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE 407 #endif 408 409 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } 410 #define CONFIG_SYS_MAX_NAND_DEVICE 1 411 #define CONFIG_MTD_NAND_VERIFY_WRITE 412 #define CONFIG_CMD_NAND 413 #if defined(CONFIG_P1020RDB_PD) 414 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) 415 #else 416 #define CONFIG_SYS_NAND_BLOCK_SIZE (16 * 1024) 417 #endif 418 419 #define CONFIG_SYS_NAND_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 420 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ 421 | BR_PS_8 /* Port Size = 8 bit */ \ 422 | BR_MS_FCM /* MSEL = FCM */ \ 423 | BR_V) /* valid */ 424 #if defined(CONFIG_P1020RDB_PD) 425 #define CONFIG_SYS_NAND_OR_PRELIM (OR_AM_32KB \ 426 | OR_FCM_PGS /* Large Page*/ \ 427 | OR_FCM_CSCT \ 428 | OR_FCM_CST \ 429 | OR_FCM_CHT \ 430 | OR_FCM_SCY_1 \ 431 | OR_FCM_TRLX \ 432 | OR_FCM_EHTR) 433 #else 434 #define CONFIG_SYS_NAND_OR_PRELIM (OR_AM_32KB /* small page */ \ 435 | OR_FCM_CSCT \ 436 | OR_FCM_CST \ 437 | OR_FCM_CHT \ 438 | OR_FCM_SCY_1 \ 439 | OR_FCM_TRLX \ 440 | OR_FCM_EHTR) 441 #endif 442 #endif /* CONFIG_NAND_FSL_ELBC */ 443 444 #define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */ 445 446 #define CONFIG_SYS_INIT_RAM_LOCK 447 #define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* stack in RAM */ 448 #ifdef CONFIG_PHYS_64BIT 449 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf 450 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR 451 /* The assembler doesn't like typecast */ 452 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \ 453 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \ 454 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) 455 #else 456 /* Initial L1 address */ 457 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS CONFIG_SYS_INIT_RAM_ADDR 458 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0 459 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS 460 #endif 461 /* Size of used area in RAM */ 462 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 463 464 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ 465 GENERATED_GBL_DATA_SIZE) 466 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 467 468 #define CONFIG_SYS_MONITOR_LEN (256 * 1024)/* Reserve 256 kB for Mon */ 469 #define CONFIG_SYS_MALLOC_LEN (1024 * 1024)/* Reserved for malloc */ 470 471 #define CONFIG_SYS_CPLD_BASE 0xffa00000 472 #ifdef CONFIG_PHYS_64BIT 473 #define CONFIG_SYS_CPLD_BASE_PHYS 0xfffa00000ull 474 #else 475 #define CONFIG_SYS_CPLD_BASE_PHYS CONFIG_SYS_CPLD_BASE 476 #endif 477 /* CPLD config size: 1Mb */ 478 #define CONFIG_CPLD_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE_PHYS) | \ 479 BR_PS_8 | BR_V) 480 #define CONFIG_CPLD_OR_PRELIM (0xfff009f7) 481 482 #define CONFIG_SYS_PMC_BASE 0xff980000 483 #define CONFIG_SYS_PMC_BASE_PHYS CONFIG_SYS_PMC_BASE 484 #define CONFIG_PMC_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_PMC_BASE_PHYS) | \ 485 BR_PS_8 | BR_V) 486 #define CONFIG_PMC_OR_PRELIM (OR_AM_64KB | OR_GPCM_CSNT | OR_GPCM_XACS | \ 487 OR_GPCM_SCY | OR_GPCM_TRLX | OR_GPCM_EHTR | \ 488 OR_GPCM_EAD) 489 490 #ifdef CONFIG_NAND 491 #define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Addr */ 492 #define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */ 493 #define CONFIG_SYS_BR1_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */ 494 #define CONFIG_SYS_OR1_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */ 495 #else 496 #define CONFIG_SYS_BR0_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */ 497 #define CONFIG_SYS_OR0_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */ 498 #ifdef CONFIG_NAND_FSL_ELBC 499 #define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Addr */ 500 #define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */ 501 #endif 502 #endif 503 #define CONFIG_SYS_BR3_PRELIM CONFIG_CPLD_BR_PRELIM /* CPLD Base Address */ 504 #define CONFIG_SYS_OR3_PRELIM CONFIG_CPLD_OR_PRELIM /* CPLD Options */ 505 506 507 /* Vsc7385 switch */ 508 #ifdef CONFIG_VSC7385_ENET 509 #define CONFIG_SYS_VSC7385_BASE 0xffb00000 510 511 #ifdef CONFIG_PHYS_64BIT 512 #define CONFIG_SYS_VSC7385_BASE_PHYS 0xfffb00000ull 513 #else 514 #define CONFIG_SYS_VSC7385_BASE_PHYS CONFIG_SYS_VSC7385_BASE 515 #endif 516 517 #define CONFIG_SYS_VSC7385_BR_PRELIM \ 518 (BR_PHYS_ADDR(CONFIG_SYS_VSC7385_BASE_PHYS) | BR_PS_8 | BR_V) 519 #define CONFIG_SYS_VSC7385_OR_PRELIM (OR_AM_128KB | OR_GPCM_CSNT | \ 520 OR_GPCM_XACS | OR_GPCM_SCY_15 | OR_GPCM_SETA | \ 521 OR_GPCM_TRLX | OR_GPCM_EHTR | OR_GPCM_EAD) 522 523 #define CONFIG_SYS_BR2_PRELIM CONFIG_SYS_VSC7385_BR_PRELIM 524 #define CONFIG_SYS_OR2_PRELIM CONFIG_SYS_VSC7385_OR_PRELIM 525 526 /* The size of the VSC7385 firmware image */ 527 #define CONFIG_VSC7385_IMAGE_SIZE 8192 528 #endif 529 530 /* Serial Port - controlled on board with jumper J8 531 * open - index 2 532 * shorted - index 1 533 */ 534 #define CONFIG_CONS_INDEX 1 535 #undef CONFIG_SERIAL_SOFTWARE_FIFO 536 #define CONFIG_SYS_NS16550 537 #define CONFIG_SYS_NS16550_SERIAL 538 #define CONFIG_SYS_NS16550_REG_SIZE 1 539 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) 540 #ifdef CONFIG_SPL_BUILD 541 #define CONFIG_NS16550_MIN_FUNCTIONS 542 #endif 543 544 #define CONFIG_SYS_BAUDRATE_TABLE \ 545 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} 546 547 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) 548 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) 549 550 /* Use the HUSH parser */ 551 #define CONFIG_SYS_HUSH_PARSER 552 553 /* 554 * Pass open firmware flat tree 555 */ 556 #define CONFIG_OF_LIBFDT 557 #define CONFIG_OF_BOARD_SETUP 558 #define CONFIG_OF_STDOUT_VIA_ALIAS 559 560 /* new uImage format support */ 561 #define CONFIG_FIT 562 #define CONFIG_FIT_VERBOSE /* enable fit_format_{error,warning}() */ 563 564 /* I2C */ 565 #define CONFIG_SYS_I2C 566 #define CONFIG_SYS_I2C_FSL 567 #define CONFIG_SYS_FSL_I2C_SPEED 400000 568 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 569 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 570 #define CONFIG_SYS_FSL_I2C2_SPEED 400000 571 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F 572 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100 573 #define CONFIG_SYS_I2C_NOPROBES { {0, 0x29} } 574 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x52 575 #define CONFIG_SYS_SPD_BUS_NUM 1 /* For rom_loc and flash bank */ 576 577 /* 578 * I2C2 EEPROM 579 */ 580 #undef CONFIG_ID_EEPROM 581 582 #define CONFIG_RTC_PT7C4338 583 #define CONFIG_SYS_I2C_RTC_ADDR 0x68 584 #define CONFIG_SYS_I2C_PCA9557_ADDR 0x18 585 586 /* enable read and write access to EEPROM */ 587 #define CONFIG_CMD_EEPROM 588 #define CONFIG_SYS_I2C_MULTI_EEPROMS 589 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 590 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 591 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 592 593 /* 594 * eSPI - Enhanced SPI 595 */ 596 #define CONFIG_HARD_SPI 597 #define CONFIG_FSL_ESPI 598 599 #if defined(CONFIG_SPI_FLASH) 600 #define CONFIG_SPI_FLASH_SPANSION 601 #define CONFIG_CMD_SF 602 #define CONFIG_SF_DEFAULT_SPEED 10000000 603 #define CONFIG_SF_DEFAULT_MODE 0 604 #endif 605 606 #if defined(CONFIG_PCI) 607 /* 608 * General PCI 609 * Memory space is mapped 1-1, but I/O space must start from 0. 610 */ 611 612 /* controller 2, direct to uli, tgtid 2, Base address 9000 */ 613 #define CONFIG_SYS_PCIE2_NAME "PCIe SLOT" 614 #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000 615 #ifdef CONFIG_PHYS_64BIT 616 #define CONFIG_SYS_PCIE2_MEM_BUS 0xc0000000 617 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull 618 #else 619 #define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000 620 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000 621 #endif 622 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */ 623 #define CONFIG_SYS_PCIE2_IO_VIRT 0xffc10000 624 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 625 #ifdef CONFIG_PHYS_64BIT 626 #define CONFIG_SYS_PCIE2_IO_PHYS 0xfffc10000ull 627 #else 628 #define CONFIG_SYS_PCIE2_IO_PHYS 0xffc10000 629 #endif 630 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ 631 632 /* controller 1, Slot 2, tgtid 1, Base address a000 */ 633 #define CONFIG_SYS_PCIE1_NAME "mini PCIe SLOT" 634 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 635 #ifdef CONFIG_PHYS_64BIT 636 #define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000 637 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull 638 #else 639 #define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000 640 #define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000 641 #endif 642 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ 643 #define CONFIG_SYS_PCIE1_IO_VIRT 0xffc00000 644 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 645 #ifdef CONFIG_PHYS_64BIT 646 #define CONFIG_SYS_PCIE1_IO_PHYS 0xfffc00000ull 647 #else 648 #define CONFIG_SYS_PCIE1_IO_PHYS 0xffc00000 649 #endif 650 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ 651 652 #define CONFIG_PCI_PNP /* do pci plug-and-play */ 653 #define CONFIG_E1000 /* Defind e1000 pci Ethernet card*/ 654 #define CONFIG_CMD_PCI 655 #define CONFIG_CMD_NET 656 657 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 658 #define CONFIG_DOS_PARTITION 659 #endif /* CONFIG_PCI */ 660 661 #if defined(CONFIG_TSEC_ENET) 662 #define CONFIG_MII /* MII PHY management */ 663 #define CONFIG_TSEC1 664 #define CONFIG_TSEC1_NAME "eTSEC1" 665 #define CONFIG_TSEC2 666 #define CONFIG_TSEC2_NAME "eTSEC2" 667 #define CONFIG_TSEC3 668 #define CONFIG_TSEC3_NAME "eTSEC3" 669 670 #define TSEC1_PHY_ADDR 2 671 #define TSEC2_PHY_ADDR 0 672 #define TSEC3_PHY_ADDR 1 673 674 #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 675 #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 676 #define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 677 678 #define TSEC1_PHYIDX 0 679 #define TSEC2_PHYIDX 0 680 #define TSEC3_PHYIDX 0 681 682 #define CONFIG_ETHPRIME "eTSEC1" 683 684 #define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */ 685 686 #define CONFIG_HAS_ETH0 687 #define CONFIG_HAS_ETH1 688 #define CONFIG_HAS_ETH2 689 #endif /* CONFIG_TSEC_ENET */ 690 691 #ifdef CONFIG_QE 692 /* QE microcode/firmware address */ 693 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR 694 #define CONFIG_SYS_QE_FMAN_FW_ADDR 0xefec0000 695 #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 696 #endif /* CONFIG_QE */ 697 698 #ifdef CONFIG_P1025RDB 699 /* 700 * QE UEC ethernet configuration 701 */ 702 #define CONFIG_MIIM_ADDRESS (CONFIG_SYS_CCSRBAR + 0x82120) 703 704 #undef CONFIG_UEC_ETH 705 #define CONFIG_PHY_MODE_NEED_CHANGE 706 707 #define CONFIG_UEC_ETH1 /* ETH1 */ 708 #define CONFIG_HAS_ETH0 709 710 #ifdef CONFIG_UEC_ETH1 711 #define CONFIG_SYS_UEC1_UCC_NUM 0 /* UCC1 */ 712 #define CONFIG_SYS_UEC1_RX_CLK QE_CLK12 /* CLK12 for MII */ 713 #define CONFIG_SYS_UEC1_TX_CLK QE_CLK9 /* CLK9 for MII */ 714 #define CONFIG_SYS_UEC1_ETH_TYPE FAST_ETH 715 #define CONFIG_SYS_UEC1_PHY_ADDR 0x0 /* 0x0 for MII */ 716 #define CONFIG_SYS_UEC1_INTERFACE_TYPE PHY_INTERFACE_MODE_RMII 717 #define CONFIG_SYS_UEC1_INTERFACE_SPEED 100 718 #endif /* CONFIG_UEC_ETH1 */ 719 720 #define CONFIG_UEC_ETH5 /* ETH5 */ 721 #define CONFIG_HAS_ETH1 722 723 #ifdef CONFIG_UEC_ETH5 724 #define CONFIG_SYS_UEC5_UCC_NUM 4 /* UCC5 */ 725 #define CONFIG_SYS_UEC5_RX_CLK QE_CLK_NONE 726 #define CONFIG_SYS_UEC5_TX_CLK QE_CLK13 /* CLK 13 for RMII */ 727 #define CONFIG_SYS_UEC5_ETH_TYPE FAST_ETH 728 #define CONFIG_SYS_UEC5_PHY_ADDR 0x3 /* 0x3 for RMII */ 729 #define CONFIG_SYS_UEC5_INTERFACE_TYPE PHY_INTERFACE_MODE_RMII 730 #define CONFIG_SYS_UEC5_INTERFACE_SPEED 100 731 #endif /* CONFIG_UEC_ETH5 */ 732 #endif /* CONFIG_P1025RDB */ 733 734 /* 735 * Environment 736 */ 737 #ifdef CONFIG_RAMBOOT_SPIFLASH 738 #define CONFIG_ENV_IS_IN_SPI_FLASH 739 #define CONFIG_ENV_SPI_BUS 0 740 #define CONFIG_ENV_SPI_CS 0 741 #define CONFIG_ENV_SPI_MAX_HZ 10000000 742 #define CONFIG_ENV_SPI_MODE 0 743 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */ 744 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ 745 #define CONFIG_ENV_SECT_SIZE 0x10000 746 #elif defined(CONFIG_RAMBOOT_SDCARD) 747 #define CONFIG_ENV_IS_IN_MMC 748 #define CONFIG_FSL_FIXED_MMC_LOCATION 749 #define CONFIG_ENV_SIZE 0x2000 750 #define CONFIG_SYS_MMC_ENV_DEV 0 751 #elif defined(CONFIG_NAND) 752 #define CONFIG_ENV_IS_IN_NAND 753 #define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE 754 #define CONFIG_ENV_OFFSET ((512 * 1024) + CONFIG_SYS_NAND_BLOCK_SIZE) 755 #define CONFIG_ENV_RANGE (3 * CONFIG_ENV_SIZE) 756 #elif defined(CONFIG_SYS_RAMBOOT) 757 #define CONFIG_ENV_IS_NOWHERE /* Store ENV in memory only */ 758 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) 759 #define CONFIG_ENV_SIZE 0x2000 760 #else 761 #define CONFIG_ENV_IS_IN_FLASH 762 #if CONFIG_SYS_MONITOR_BASE > 0xfff80000 763 #define CONFIG_ENV_ADDR 0xfff80000 764 #else 765 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) 766 #endif 767 #define CONFIG_ENV_SIZE 0x2000 768 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ 769 #endif 770 771 #define CONFIG_LOADS_ECHO /* echo on for serial download */ 772 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ 773 774 /* 775 * Command line configuration. 776 */ 777 #include <config_cmd_default.h> 778 779 #define CONFIG_CMD_IRQ 780 #define CONFIG_CMD_PING 781 #define CONFIG_CMD_I2C 782 #define CONFIG_CMD_MII 783 #define CONFIG_CMD_DATE 784 #define CONFIG_CMD_ELF 785 #define CONFIG_CMD_SETEXPR 786 #define CONFIG_CMD_REGINFO 787 788 /* 789 * USB 790 */ 791 #define CONFIG_HAS_FSL_DR_USB 792 793 #if defined(CONFIG_HAS_FSL_DR_USB) 794 #define CONFIG_USB_EHCI 795 796 #ifdef CONFIG_USB_EHCI 797 #define CONFIG_CMD_USB 798 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 799 #define CONFIG_USB_EHCI_FSL 800 #define CONFIG_USB_STORAGE 801 #endif 802 #endif 803 804 #define CONFIG_MMC 805 806 #ifdef CONFIG_MMC 807 #define CONFIG_FSL_ESDHC 808 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR 809 #define CONFIG_CMD_MMC 810 #define CONFIG_GENERIC_MMC 811 #endif 812 813 #if defined(CONFIG_MMC) || defined(CONFIG_USB_EHCI) \ 814 || defined(CONFIG_FSL_SATA) 815 #define CONFIG_CMD_EXT2 816 #define CONFIG_CMD_FAT 817 #define CONFIG_DOS_PARTITION 818 #endif 819 820 #undef CONFIG_WATCHDOG /* watchdog disabled */ 821 822 /* 823 * Miscellaneous configurable options 824 */ 825 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 826 #define CONFIG_CMDLINE_EDITING /* Command-line editing */ 827 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 828 #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ 829 #if defined(CONFIG_CMD_KGDB) 830 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 831 #else 832 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 833 #endif 834 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) 835 /* Print Buffer Size */ 836 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 837 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */ 838 #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms tick */ 839 840 /* 841 * For booting Linux, the board info and command line data 842 * have to be in the first 64 MB of memory, since this is 843 * the maximum mapped by the Linux kernel during initialization. 844 */ 845 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory for Linux*/ 846 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 847 848 #if defined(CONFIG_CMD_KGDB) 849 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 850 #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ 851 #endif 852 853 /* 854 * Environment Configuration 855 */ 856 #define CONFIG_HOSTNAME unknown 857 #define CONFIG_ROOTPATH "/opt/nfsroot" 858 #define CONFIG_BOOTFILE "uImage" 859 #define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */ 860 861 /* default location for tftp and bootm */ 862 #define CONFIG_LOADADDR 1000000 863 864 #define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */ 865 #define CONFIG_BOOTARGS /* the boot command will set bootargs */ 866 867 #define CONFIG_BAUDRATE 115200 868 869 #ifdef __SW_BOOT_NOR 870 #define __NOR_RST_CMD \ 871 norboot=i2c dev 1; i2c mw 18 1 __SW_BOOT_NOR 1; \ 872 i2c mw 18 3 __SW_BOOT_MASK 1; reset 873 #endif 874 #ifdef __SW_BOOT_SPI 875 #define __SPI_RST_CMD \ 876 spiboot=i2c dev 1; i2c mw 18 1 __SW_BOOT_SPI 1; \ 877 i2c mw 18 3 __SW_BOOT_MASK 1; reset 878 #endif 879 #ifdef __SW_BOOT_SD 880 #define __SD_RST_CMD \ 881 sdboot=i2c dev 1; i2c mw 18 1 __SW_BOOT_SD 1; \ 882 i2c mw 18 3 __SW_BOOT_MASK 1; reset 883 #endif 884 #ifdef __SW_BOOT_NAND 885 #define __NAND_RST_CMD \ 886 nandboot=i2c dev 1; i2c mw 18 1 __SW_BOOT_NAND 1; \ 887 i2c mw 18 3 __SW_BOOT_MASK 1; reset 888 #endif 889 #ifdef __SW_BOOT_PCIE 890 #define __PCIE_RST_CMD \ 891 pciboot=i2c dev 1; i2c mw 18 1 __SW_BOOT_PCIE 1; \ 892 i2c mw 18 3 __SW_BOOT_MASK 1; reset 893 #endif 894 895 #define CONFIG_EXTRA_ENV_SETTINGS \ 896 "netdev=eth0\0" \ 897 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ 898 "loadaddr=1000000\0" \ 899 "bootfile=uImage\0" \ 900 "tftpflash=tftpboot $loadaddr $uboot; " \ 901 "protect off " __stringify(CONFIG_SYS_TEXT_BASE) " +$filesize; " \ 902 "erase " __stringify(CONFIG_SYS_TEXT_BASE) " +$filesize; " \ 903 "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) " $filesize; " \ 904 "protect on " __stringify(CONFIG_SYS_TEXT_BASE) " +$filesize; " \ 905 "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) " $filesize\0" \ 906 "hwconfig=usb1:dr_mode=host,phy_type=ulpi\0" \ 907 "consoledev=ttyS0\0" \ 908 "ramdiskaddr=2000000\0" \ 909 "ramdiskfile=rootfs.ext2.gz.uboot\0" \ 910 "fdtaddr=c00000\0" \ 911 "bdev=sda1\0" \ 912 "jffs2nor=mtdblock3\0" \ 913 "norbootaddr=ef080000\0" \ 914 "norfdtaddr=ef040000\0" \ 915 "jffs2nand=mtdblock9\0" \ 916 "nandbootaddr=100000\0" \ 917 "nandfdtaddr=80000\0" \ 918 "ramdisk_size=120000\0" \ 919 "map_lowernorbank=i2c dev 1; i2c mw 18 1 02 1; i2c mw 18 3 fd 1\0" \ 920 "map_uppernorbank=i2c dev 1; i2c mw 18 1 00 1; i2c mw 18 3 fd 1\0" \ 921 __stringify(__NOR_RST_CMD)"\0" \ 922 __stringify(__SPI_RST_CMD)"\0" \ 923 __stringify(__SD_RST_CMD)"\0" \ 924 __stringify(__NAND_RST_CMD)"\0" \ 925 __stringify(__PCIE_RST_CMD)"\0" 926 927 #define CONFIG_NFSBOOTCOMMAND \ 928 "setenv bootargs root=/dev/nfs rw " \ 929 "nfsroot=$serverip:$rootpath " \ 930 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 931 "console=$consoledev,$baudrate $othbootargs;" \ 932 "tftp $loadaddr $bootfile;" \ 933 "tftp $fdtaddr $fdtfile;" \ 934 "bootm $loadaddr - $fdtaddr" 935 936 #define CONFIG_HDBOOT \ 937 "setenv bootargs root=/dev/$bdev rw rootdelay=30 " \ 938 "console=$consoledev,$baudrate $othbootargs;" \ 939 "usb start;" \ 940 "ext2load usb 0:1 $loadaddr /boot/$bootfile;" \ 941 "ext2load usb 0:1 $fdtaddr /boot/$fdtfile;" \ 942 "bootm $loadaddr - $fdtaddr" 943 944 #define CONFIG_USB_FAT_BOOT \ 945 "setenv bootargs root=/dev/ram rw " \ 946 "console=$consoledev,$baudrate $othbootargs " \ 947 "ramdisk_size=$ramdisk_size;" \ 948 "usb start;" \ 949 "fatload usb 0:2 $loadaddr $bootfile;" \ 950 "fatload usb 0:2 $fdtaddr $fdtfile;" \ 951 "fatload usb 0:2 $ramdiskaddr $ramdiskfile;" \ 952 "bootm $loadaddr $ramdiskaddr $fdtaddr" 953 954 #define CONFIG_USB_EXT2_BOOT \ 955 "setenv bootargs root=/dev/ram rw " \ 956 "console=$consoledev,$baudrate $othbootargs " \ 957 "ramdisk_size=$ramdisk_size;" \ 958 "usb start;" \ 959 "ext2load usb 0:4 $loadaddr $bootfile;" \ 960 "ext2load usb 0:4 $fdtaddr $fdtfile;" \ 961 "ext2load usb 0:4 $ramdiskaddr $ramdiskfile;" \ 962 "bootm $loadaddr $ramdiskaddr $fdtaddr" 963 964 #define CONFIG_NORBOOT \ 965 "setenv bootargs root=/dev/$jffs2nor rw " \ 966 "console=$consoledev,$baudrate rootfstype=jffs2 $othbootargs;" \ 967 "bootm $norbootaddr - $norfdtaddr" 968 969 #define CONFIG_RAMBOOTCOMMAND \ 970 "setenv bootargs root=/dev/ram rw " \ 971 "console=$consoledev,$baudrate $othbootargs " \ 972 "ramdisk_size=$ramdisk_size;" \ 973 "tftp $ramdiskaddr $ramdiskfile;" \ 974 "tftp $loadaddr $bootfile;" \ 975 "tftp $fdtaddr $fdtfile;" \ 976 "bootm $loadaddr $ramdiskaddr $fdtaddr" 977 978 #define CONFIG_BOOTCOMMAND CONFIG_HDBOOT 979 980 #endif /* __CONFIG_H */ 981