1 /* 2 * Copyright 2010-2011 Freescale Semiconductor, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 /* 8 * QorIQ RDB boards configuration file 9 */ 10 #ifndef __CONFIG_H 11 #define __CONFIG_H 12 13 #define CONFIG_DISPLAY_BOARDINFO 14 15 #ifdef CONFIG_36BIT 16 #define CONFIG_PHYS_64BIT 17 #endif 18 19 #if defined(CONFIG_P1020MBG) 20 #define CONFIG_BOARDNAME "P1020MBG-PC" 21 #define CONFIG_P1020 22 #define CONFIG_VSC7385_ENET 23 #define CONFIG_SLIC 24 #define __SW_BOOT_MASK 0x03 25 #define __SW_BOOT_NOR 0xe4 26 #define __SW_BOOT_SD 0x54 27 #define CONFIG_SYS_L2_SIZE (256 << 10) 28 #endif 29 30 #if defined(CONFIG_P1020UTM) 31 #define CONFIG_BOARDNAME "P1020UTM-PC" 32 #define CONFIG_P1020 33 #define __SW_BOOT_MASK 0x03 34 #define __SW_BOOT_NOR 0xe0 35 #define __SW_BOOT_SD 0x50 36 #define CONFIG_SYS_L2_SIZE (256 << 10) 37 #endif 38 39 #if defined(CONFIG_P1020RDB_PC) 40 #define CONFIG_BOARDNAME "P1020RDB-PC" 41 #define CONFIG_NAND_FSL_ELBC 42 #define CONFIG_P1020 43 #define CONFIG_VSC7385_ENET 44 #define CONFIG_SLIC 45 #define __SW_BOOT_MASK 0x03 46 #define __SW_BOOT_NOR 0x5c 47 #define __SW_BOOT_SPI 0x1c 48 #define __SW_BOOT_SD 0x9c 49 #define __SW_BOOT_NAND 0xec 50 #define __SW_BOOT_PCIE 0x6c 51 #define CONFIG_SYS_L2_SIZE (256 << 10) 52 #endif 53 54 /* 55 * P1020RDB-PD board has user selectable switches for evaluating different 56 * frequency and boot options for the P1020 device. The table that 57 * follow describe the available options. The front six binary number was in 58 * accordance with SW3[1:6]. 59 * 111101 533 533 267 667 NOR Core0 boot; Core1 hold-off 60 * 101101 667 667 333 667 NOR Core0 boot; Core1 hold-off 61 * 011001 800 800 400 667 NOR Core0 boot; Core1 hold-off 62 * 001001 800 800 400 667 SD/MMC Core0 boot; Core1 hold-off 63 * 001101 800 800 400 667 SPI Core0 boot; Core1 hold-off 64 * 010001 800 800 400 667 NAND Core0 boot; Core1 hold-off 65 * 011101 800 800 400 667 PCIe-2 Core0 boot; Core1 hold-off 66 */ 67 #if defined(CONFIG_P1020RDB_PD) 68 #define CONFIG_BOARDNAME "P1020RDB-PD" 69 #define CONFIG_NAND_FSL_ELBC 70 #define CONFIG_P1020 71 #define CONFIG_VSC7385_ENET 72 #define CONFIG_SLIC 73 #define __SW_BOOT_MASK 0x03 74 #define __SW_BOOT_NOR 0x64 75 #define __SW_BOOT_SPI 0x34 76 #define __SW_BOOT_SD 0x24 77 #define __SW_BOOT_NAND 0x44 78 #define __SW_BOOT_PCIE 0x74 79 #define CONFIG_SYS_L2_SIZE (256 << 10) 80 /* 81 * Dynamic MTD Partition support with mtdparts 82 */ 83 #define CONFIG_MTD_DEVICE 84 #define CONFIG_MTD_PARTITIONS 85 #define CONFIG_CMD_MTDPARTS 86 #define CONFIG_FLASH_CFI_MTD 87 #define MTDIDS_DEFAULT "nor0=ec000000.nor" 88 #define MTDPARTS_DEFAULT "mtdparts=ec000000.nor:128k(dtb),6016k(kernel)," \ 89 "57088k(fs),1m(vsc7385-firmware),1280k(u-boot)" 90 #endif 91 92 #if defined(CONFIG_P1021RDB) 93 #define CONFIG_BOARDNAME "P1021RDB-PC" 94 #define CONFIG_NAND_FSL_ELBC 95 #define CONFIG_P1021 96 #define CONFIG_QE 97 #define CONFIG_VSC7385_ENET 98 #define CONFIG_SYS_LBC_LBCR 0x00080000 /* Implement conversion of 99 addresses in the LBC */ 100 #define __SW_BOOT_MASK 0x03 101 #define __SW_BOOT_NOR 0x5c 102 #define __SW_BOOT_SPI 0x1c 103 #define __SW_BOOT_SD 0x9c 104 #define __SW_BOOT_NAND 0xec 105 #define __SW_BOOT_PCIE 0x6c 106 #define CONFIG_SYS_L2_SIZE (256 << 10) 107 /* 108 * Dynamic MTD Partition support with mtdparts 109 */ 110 #define CONFIG_MTD_DEVICE 111 #define CONFIG_MTD_PARTITIONS 112 #define CONFIG_CMD_MTDPARTS 113 #define CONFIG_FLASH_CFI_MTD 114 #ifdef CONFIG_PHYS_64BIT 115 #define MTDIDS_DEFAULT "nor0=fef000000.nor" 116 #define MTDPARTS_DEFAULT "mtdparts=fef000000.nor:256k(vsc7385-firmware)," \ 117 "256k(dtb),4608k(kernel),9728k(fs)," \ 118 "256k(qe-ucode-firmware),1280k(u-boot)" 119 #else 120 #define MTDIDS_DEFAULT "nor0=ef000000.nor" 121 #define MTDPARTS_DEFAULT "mtdparts=ef000000.nor:256k(vsc7385-firmware)," \ 122 "256k(dtb),4608k(kernel),9728k(fs)," \ 123 "256k(qe-ucode-firmware),1280k(u-boot)" 124 #endif 125 #endif 126 127 #if defined(CONFIG_P1024RDB) 128 #define CONFIG_BOARDNAME "P1024RDB" 129 #define CONFIG_NAND_FSL_ELBC 130 #define CONFIG_P1024 131 #define CONFIG_SLIC 132 #define __SW_BOOT_MASK 0xf3 133 #define __SW_BOOT_NOR 0x00 134 #define __SW_BOOT_SPI 0x08 135 #define __SW_BOOT_SD 0x04 136 #define __SW_BOOT_NAND 0x0c 137 #define CONFIG_SYS_L2_SIZE (256 << 10) 138 #endif 139 140 #if defined(CONFIG_P1025RDB) 141 #define CONFIG_BOARDNAME "P1025RDB" 142 #define CONFIG_NAND_FSL_ELBC 143 #define CONFIG_P1025 144 #define CONFIG_QE 145 #define CONFIG_SLIC 146 147 #define CONFIG_SYS_LBC_LBCR 0x00080000 /* Implement conversion of 148 addresses in the LBC */ 149 #define __SW_BOOT_MASK 0xf3 150 #define __SW_BOOT_NOR 0x00 151 #define __SW_BOOT_SPI 0x08 152 #define __SW_BOOT_SD 0x04 153 #define __SW_BOOT_NAND 0x0c 154 #define CONFIG_SYS_L2_SIZE (256 << 10) 155 #endif 156 157 #if defined(CONFIG_P2020RDB) 158 #define CONFIG_BOARDNAME "P2020RDB-PCA" 159 #define CONFIG_NAND_FSL_ELBC 160 #define CONFIG_P2020 161 #define CONFIG_VSC7385_ENET 162 #define __SW_BOOT_MASK 0x03 163 #define __SW_BOOT_NOR 0xc8 164 #define __SW_BOOT_SPI 0x28 165 #define __SW_BOOT_SD 0x68 /* or 0x18 */ 166 #define __SW_BOOT_NAND 0xe8 167 #define __SW_BOOT_PCIE 0xa8 168 #define CONFIG_SYS_L2_SIZE (512 << 10) 169 /* 170 * Dynamic MTD Partition support with mtdparts 171 */ 172 #define CONFIG_MTD_DEVICE 173 #define CONFIG_MTD_PARTITIONS 174 #define CONFIG_CMD_MTDPARTS 175 #define CONFIG_FLASH_CFI_MTD 176 #ifdef CONFIG_PHYS_64BIT 177 #define MTDIDS_DEFAULT "nor0=fef000000.nor" 178 #define MTDPARTS_DEFAULT "mtdparts=fef000000.nor:256k(vsc7385-firmware)," \ 179 "256k(dtb),4608k(kernel),9984k(fs),1280k(u-boot)" 180 #else 181 #define MTDIDS_DEFAULT "nor0=ef000000.nor" 182 #define MTDPARTS_DEFAULT "mtdparts=ef000000.nor:256k(vsc7385-firmware)," \ 183 "256k(dtb),4608k(kernel),9984k(fs),1280k(u-boot)" 184 #endif 185 #endif 186 187 #ifdef CONFIG_SDCARD 188 #define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT 189 #define CONFIG_SPL_ENV_SUPPORT 190 #define CONFIG_SPL_SERIAL_SUPPORT 191 #define CONFIG_SPL_MMC_SUPPORT 192 #define CONFIG_SPL_MMC_MINIMAL 193 #define CONFIG_SPL_FLUSH_IMAGE 194 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 195 #define CONFIG_SPL_LIBGENERIC_SUPPORT 196 #define CONFIG_SPL_LIBCOMMON_SUPPORT 197 #define CONFIG_SPL_I2C_SUPPORT 198 #define CONFIG_FSL_LAW /* Use common FSL init code */ 199 #define CONFIG_SYS_TEXT_BASE 0x11001000 200 #define CONFIG_SPL_TEXT_BASE 0xf8f81000 201 #define CONFIG_SPL_PAD_TO 0x20000 202 #define CONFIG_SPL_MAX_SIZE (128 * 1024) 203 #define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10) 204 #define CONFIG_SYS_MMC_U_BOOT_DST (0x11000000) 205 #define CONFIG_SYS_MMC_U_BOOT_START (0x11000000) 206 #define CONFIG_SYS_MMC_U_BOOT_OFFS (128 << 10) 207 #define CONFIG_SYS_MPC85XX_NO_RESETVEC 208 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds" 209 #define CONFIG_SPL_MMC_BOOT 210 #ifdef CONFIG_SPL_BUILD 211 #define CONFIG_SPL_COMMON_INIT_DDR 212 #endif 213 #endif 214 215 #ifdef CONFIG_SPIFLASH 216 #define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT 217 #define CONFIG_SPL_ENV_SUPPORT 218 #define CONFIG_SPL_SERIAL_SUPPORT 219 #define CONFIG_SPL_SPI_SUPPORT 220 #define CONFIG_SPL_SPI_FLASH_SUPPORT 221 #define CONFIG_SPL_SPI_FLASH_MINIMAL 222 #define CONFIG_SPL_FLUSH_IMAGE 223 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 224 #define CONFIG_SPL_LIBGENERIC_SUPPORT 225 #define CONFIG_SPL_LIBCOMMON_SUPPORT 226 #define CONFIG_SPL_I2C_SUPPORT 227 #define CONFIG_FSL_LAW /* Use common FSL init code */ 228 #define CONFIG_SYS_TEXT_BASE 0x11001000 229 #define CONFIG_SPL_TEXT_BASE 0xf8f81000 230 #define CONFIG_SPL_PAD_TO 0x20000 231 #define CONFIG_SPL_MAX_SIZE (128 * 1024) 232 #define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (768 << 10) 233 #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x11000000) 234 #define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x11000000) 235 #define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (128 << 10) 236 #define CONFIG_SYS_MPC85XX_NO_RESETVEC 237 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds" 238 #define CONFIG_SPL_SPI_BOOT 239 #ifdef CONFIG_SPL_BUILD 240 #define CONFIG_SPL_COMMON_INIT_DDR 241 #endif 242 #endif 243 244 #ifdef CONFIG_NAND 245 #ifdef CONFIG_TPL_BUILD 246 #define CONFIG_SPL_NAND_BOOT 247 #define CONFIG_SPL_FLUSH_IMAGE 248 #define CONFIG_SPL_ENV_SUPPORT 249 #define CONFIG_SPL_NAND_INIT 250 #define CONFIG_SPL_SERIAL_SUPPORT 251 #define CONFIG_SPL_LIBGENERIC_SUPPORT 252 #define CONFIG_SPL_LIBCOMMON_SUPPORT 253 #define CONFIG_SPL_I2C_SUPPORT 254 #define CONFIG_SPL_NAND_SUPPORT 255 #define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT 256 #define CONFIG_SPL_COMMON_INIT_DDR 257 #define CONFIG_SPL_MAX_SIZE (128 << 10) 258 #define CONFIG_SPL_TEXT_BASE 0xf8f81000 259 #define CONFIG_SYS_MPC85XX_NO_RESETVEC 260 #define CONFIG_SYS_NAND_U_BOOT_SIZE (832 << 10) 261 #define CONFIG_SYS_NAND_U_BOOT_DST (0x11000000) 262 #define CONFIG_SYS_NAND_U_BOOT_START (0x11000000) 263 #define CONFIG_SYS_NAND_U_BOOT_OFFS ((128 + 128) << 10) 264 #elif defined(CONFIG_SPL_BUILD) 265 #define CONFIG_SPL_INIT_MINIMAL 266 #define CONFIG_SPL_SERIAL_SUPPORT 267 #define CONFIG_SPL_NAND_SUPPORT 268 #define CONFIG_SPL_FLUSH_IMAGE 269 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 270 #define CONFIG_SPL_TEXT_BASE 0xff800000 271 #define CONFIG_SPL_MAX_SIZE 4096 272 #define CONFIG_SYS_NAND_U_BOOT_SIZE (128 << 10) 273 #define CONFIG_SYS_NAND_U_BOOT_DST 0xf8f80000 274 #define CONFIG_SYS_NAND_U_BOOT_START 0xf8f80000 275 #define CONFIG_SYS_NAND_U_BOOT_OFFS (128 << 10) 276 #endif /* not CONFIG_TPL_BUILD */ 277 278 #define CONFIG_SPL_PAD_TO 0x20000 279 #define CONFIG_TPL_PAD_TO 0x20000 280 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 281 #define CONFIG_SYS_TEXT_BASE 0x11001000 282 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds" 283 #endif 284 285 #ifndef CONFIG_SYS_TEXT_BASE 286 #define CONFIG_SYS_TEXT_BASE 0xeff40000 287 #endif 288 289 #ifndef CONFIG_RESET_VECTOR_ADDRESS 290 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc 291 #endif 292 293 #ifndef CONFIG_SYS_MONITOR_BASE 294 #ifdef CONFIG_SPL_BUILD 295 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE 296 #else 297 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 298 #endif 299 #endif 300 301 /* High Level Configuration Options */ 302 #define CONFIG_BOOKE 303 #define CONFIG_E500 304 305 #define CONFIG_MP 306 307 #define CONFIG_FSL_ELBC 308 #define CONFIG_PCI 309 #define CONFIG_PCIE1 /* PCIE controller 1 (slot 1) */ 310 #define CONFIG_PCIE2 /* PCIE controller 2 (slot 2) */ 311 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ 312 #define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */ 313 #define CONFIG_FSL_PCIE_RESET /* need PCIe reset errata */ 314 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ 315 316 #define CONFIG_FSL_LAW 317 #define CONFIG_TSEC_ENET /* tsec ethernet support */ 318 #define CONFIG_ENV_OVERWRITE 319 320 #define CONFIG_CMD_SATA 321 #define CONFIG_SATA_SIL 322 #define CONFIG_SYS_SATA_MAX_DEVICE 2 323 #define CONFIG_LIBATA 324 #define CONFIG_LBA48 325 326 #if defined(CONFIG_P2020RDB) 327 #define CONFIG_SYS_CLK_FREQ 100000000 328 #else 329 #define CONFIG_SYS_CLK_FREQ 66666666 330 #endif 331 #define CONFIG_DDR_CLK_FREQ 66666666 332 333 #define CONFIG_HWCONFIG 334 /* 335 * These can be toggled for performance analysis, otherwise use default. 336 */ 337 #define CONFIG_L2_CACHE 338 #define CONFIG_BTB 339 340 #define CONFIG_BOARD_EARLY_INIT_F /* Call board_pre_init */ 341 342 #define CONFIG_ENABLE_36BIT_PHYS 343 344 #ifdef CONFIG_PHYS_64BIT 345 #define CONFIG_ADDR_MAP 1 346 #define CONFIG_SYS_NUM_ADDR_MAP 16 /* number of TLB1 entries */ 347 #endif 348 349 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ 350 #define CONFIG_SYS_MEMTEST_END 0x1fffffff 351 #define CONFIG_PANIC_HANG /* do not reset board on panic */ 352 353 #define CONFIG_SYS_CCSRBAR 0xffe00000 354 #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR 355 356 /* IN case of NAND bootloader relocate CCSRBAR in RAMboot code not in the 4k 357 SPL code*/ 358 #ifdef CONFIG_SPL_BUILD 359 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE 360 #endif 361 362 /* DDR Setup */ 363 #define CONFIG_SYS_FSL_DDR3 364 #define CONFIG_SYS_DDR_RAW_TIMING 365 #define CONFIG_DDR_SPD 366 #define CONFIG_SYS_SPD_BUS_NUM 1 367 #define SPD_EEPROM_ADDRESS 0x52 368 #undef CONFIG_FSL_DDR_INTERACTIVE 369 370 #if (defined(CONFIG_P1020MBG) || defined(CONFIG_P1020RDB_PD)) 371 #define CONFIG_SYS_SDRAM_SIZE_LAW LAW_SIZE_2G 372 #define CONFIG_CHIP_SELECTS_PER_CTRL 2 373 #else 374 #define CONFIG_SYS_SDRAM_SIZE_LAW LAW_SIZE_1G 375 #define CONFIG_CHIP_SELECTS_PER_CTRL 1 376 #endif 377 #define CONFIG_SYS_SDRAM_SIZE (1u << (CONFIG_SYS_SDRAM_SIZE_LAW - 19)) 378 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 379 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 380 381 #define CONFIG_NUM_DDR_CONTROLLERS 1 382 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 383 384 /* Default settings for DDR3 */ 385 #ifndef CONFIG_P2020RDB 386 #define CONFIG_SYS_DDR_CS0_BNDS 0x0000003f 387 #define CONFIG_SYS_DDR_CS0_CONFIG 0x80014302 388 #define CONFIG_SYS_DDR_CS0_CONFIG_2 0x00000000 389 #define CONFIG_SYS_DDR_CS1_BNDS 0x0040007f 390 #define CONFIG_SYS_DDR_CS1_CONFIG 0x80014302 391 #define CONFIG_SYS_DDR_CS1_CONFIG_2 0x00000000 392 393 #define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef 394 #define CONFIG_SYS_DDR_INIT_ADDR 0x00000000 395 #define CONFIG_SYS_DDR_INIT_EXT_ADDR 0x00000000 396 #define CONFIG_SYS_DDR_MODE_CONTROL 0x00000000 397 398 #define CONFIG_SYS_DDR_ZQ_CONTROL 0x89080600 399 #define CONFIG_SYS_DDR_WRLVL_CONTROL 0x8655A608 400 #define CONFIG_SYS_DDR_SR_CNTR 0x00000000 401 #define CONFIG_SYS_DDR_RCW_1 0x00000000 402 #define CONFIG_SYS_DDR_RCW_2 0x00000000 403 #define CONFIG_SYS_DDR_CONTROL 0xC70C0000 /* Type = DDR3 */ 404 #define CONFIG_SYS_DDR_CONTROL_2 0x04401050 405 #define CONFIG_SYS_DDR_TIMING_4 0x00220001 406 #define CONFIG_SYS_DDR_TIMING_5 0x03402400 407 408 #define CONFIG_SYS_DDR_TIMING_3 0x00020000 409 #define CONFIG_SYS_DDR_TIMING_0 0x00330004 410 #define CONFIG_SYS_DDR_TIMING_1 0x6f6B4846 411 #define CONFIG_SYS_DDR_TIMING_2 0x0FA8C8CF 412 #define CONFIG_SYS_DDR_CLK_CTRL 0x03000000 413 #define CONFIG_SYS_DDR_MODE_1 0x40461520 414 #define CONFIG_SYS_DDR_MODE_2 0x8000c000 415 #define CONFIG_SYS_DDR_INTERVAL 0x0C300000 416 #endif 417 418 #undef CONFIG_CLOCKS_IN_MHZ 419 420 /* 421 * Memory map 422 * 423 * 0x0000_0000 0x7fff_ffff DDR Up to 2GB cacheable 424 * 0x8000_0000 0xdfff_ffff PCI Express Mem 1.5G non-cacheable(PCIe * 3) 425 * 0xec00_0000 0xefff_ffff NOR flash Up to 64M non-cacheable CS0/1 426 * 0xf8f8_0000 0xf8ff_ffff L2 SRAM Up to 512K cacheable 427 * (early boot only) 428 * 0xff80_0000 0xff80_7fff NAND flash 32K non-cacheable CS1/0 429 * 0xff98_0000 0xff98_ffff PMC 64K non-cacheable CS2 430 * 0xffa0_0000 0xffaf_ffff CPLD 1M non-cacheable CS3 431 * 0xffb0_0000 0xffbf_ffff VSC7385 switch 1M non-cacheable CS2 432 * 0xffc0_0000 0xffc3_ffff PCI IO range 256k non-cacheable 433 * 0xffd0_0000 0xffd0_3fff L1 for stack 16K cacheable 434 * 0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable 435 */ 436 437 /* 438 * Local Bus Definitions 439 */ 440 #if (defined(CONFIG_P1020MBG) || defined(CONFIG_P1020RDB_PD)) 441 #define CONFIG_SYS_MAX_FLASH_SECT 512 /* 64M */ 442 #define CONFIG_SYS_FLASH_BASE 0xec000000 443 #elif defined(CONFIG_P1020UTM) 444 #define CONFIG_SYS_MAX_FLASH_SECT 256 /* 32M */ 445 #define CONFIG_SYS_FLASH_BASE 0xee000000 446 #else 447 #define CONFIG_SYS_MAX_FLASH_SECT 128 /* 16M */ 448 #define CONFIG_SYS_FLASH_BASE 0xef000000 449 #endif 450 451 #ifdef CONFIG_PHYS_64BIT 452 #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE) 453 #else 454 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE 455 #endif 456 457 #define CONFIG_FLASH_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) \ 458 | BR_PS_16 | BR_V) 459 460 #define CONFIG_FLASH_OR_PRELIM 0xfc000ff7 461 462 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS} 463 #define CONFIG_SYS_FLASH_QUIET_TEST 464 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 465 466 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ 467 468 #undef CONFIG_SYS_FLASH_CHECKSUM 469 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 470 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 471 472 #define CONFIG_FLASH_CFI_DRIVER 473 #define CONFIG_SYS_FLASH_CFI 474 #define CONFIG_SYS_FLASH_EMPTY_INFO 475 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 476 477 /* Nand Flash */ 478 #ifdef CONFIG_NAND_FSL_ELBC 479 #define CONFIG_SYS_NAND_BASE 0xff800000 480 #ifdef CONFIG_PHYS_64BIT 481 #define CONFIG_SYS_NAND_BASE_PHYS 0xfff800000ull 482 #else 483 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE 484 #endif 485 486 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } 487 #define CONFIG_SYS_MAX_NAND_DEVICE 1 488 #define CONFIG_CMD_NAND 489 #if defined(CONFIG_P1020RDB_PD) 490 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) 491 #else 492 #define CONFIG_SYS_NAND_BLOCK_SIZE (16 * 1024) 493 #endif 494 495 #define CONFIG_SYS_NAND_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 496 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ 497 | BR_PS_8 /* Port Size = 8 bit */ \ 498 | BR_MS_FCM /* MSEL = FCM */ \ 499 | BR_V) /* valid */ 500 #if defined(CONFIG_P1020RDB_PD) 501 #define CONFIG_SYS_NAND_OR_PRELIM (OR_AM_32KB \ 502 | OR_FCM_PGS /* Large Page*/ \ 503 | OR_FCM_CSCT \ 504 | OR_FCM_CST \ 505 | OR_FCM_CHT \ 506 | OR_FCM_SCY_1 \ 507 | OR_FCM_TRLX \ 508 | OR_FCM_EHTR) 509 #else 510 #define CONFIG_SYS_NAND_OR_PRELIM (OR_AM_32KB /* small page */ \ 511 | OR_FCM_CSCT \ 512 | OR_FCM_CST \ 513 | OR_FCM_CHT \ 514 | OR_FCM_SCY_1 \ 515 | OR_FCM_TRLX \ 516 | OR_FCM_EHTR) 517 #endif 518 #endif /* CONFIG_NAND_FSL_ELBC */ 519 520 #define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */ 521 522 #define CONFIG_SYS_INIT_RAM_LOCK 523 #define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* stack in RAM */ 524 #ifdef CONFIG_PHYS_64BIT 525 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf 526 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR 527 /* The assembler doesn't like typecast */ 528 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \ 529 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \ 530 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) 531 #else 532 /* Initial L1 address */ 533 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS CONFIG_SYS_INIT_RAM_ADDR 534 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0 535 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS 536 #endif 537 /* Size of used area in RAM */ 538 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 539 540 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ 541 GENERATED_GBL_DATA_SIZE) 542 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 543 544 #define CONFIG_SYS_MONITOR_LEN (768 * 1024) 545 #define CONFIG_SYS_MALLOC_LEN (1024 * 1024)/* Reserved for malloc */ 546 547 #define CONFIG_SYS_CPLD_BASE 0xffa00000 548 #ifdef CONFIG_PHYS_64BIT 549 #define CONFIG_SYS_CPLD_BASE_PHYS 0xfffa00000ull 550 #else 551 #define CONFIG_SYS_CPLD_BASE_PHYS CONFIG_SYS_CPLD_BASE 552 #endif 553 /* CPLD config size: 1Mb */ 554 #define CONFIG_CPLD_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE_PHYS) | \ 555 BR_PS_8 | BR_V) 556 #define CONFIG_CPLD_OR_PRELIM (0xfff009f7) 557 558 #define CONFIG_SYS_PMC_BASE 0xff980000 559 #define CONFIG_SYS_PMC_BASE_PHYS CONFIG_SYS_PMC_BASE 560 #define CONFIG_PMC_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_PMC_BASE_PHYS) | \ 561 BR_PS_8 | BR_V) 562 #define CONFIG_PMC_OR_PRELIM (OR_AM_64KB | OR_GPCM_CSNT | OR_GPCM_XACS | \ 563 OR_GPCM_SCY | OR_GPCM_TRLX | OR_GPCM_EHTR | \ 564 OR_GPCM_EAD) 565 566 #ifdef CONFIG_NAND 567 #define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Addr */ 568 #define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */ 569 #define CONFIG_SYS_BR1_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */ 570 #define CONFIG_SYS_OR1_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */ 571 #else 572 #define CONFIG_SYS_BR0_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */ 573 #define CONFIG_SYS_OR0_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */ 574 #ifdef CONFIG_NAND_FSL_ELBC 575 #define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Addr */ 576 #define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */ 577 #endif 578 #endif 579 #define CONFIG_SYS_BR3_PRELIM CONFIG_CPLD_BR_PRELIM /* CPLD Base Address */ 580 #define CONFIG_SYS_OR3_PRELIM CONFIG_CPLD_OR_PRELIM /* CPLD Options */ 581 582 /* Vsc7385 switch */ 583 #ifdef CONFIG_VSC7385_ENET 584 #define CONFIG_SYS_VSC7385_BASE 0xffb00000 585 586 #ifdef CONFIG_PHYS_64BIT 587 #define CONFIG_SYS_VSC7385_BASE_PHYS 0xfffb00000ull 588 #else 589 #define CONFIG_SYS_VSC7385_BASE_PHYS CONFIG_SYS_VSC7385_BASE 590 #endif 591 592 #define CONFIG_SYS_VSC7385_BR_PRELIM \ 593 (BR_PHYS_ADDR(CONFIG_SYS_VSC7385_BASE_PHYS) | BR_PS_8 | BR_V) 594 #define CONFIG_SYS_VSC7385_OR_PRELIM (OR_AM_128KB | OR_GPCM_CSNT | \ 595 OR_GPCM_XACS | OR_GPCM_SCY_15 | OR_GPCM_SETA | \ 596 OR_GPCM_TRLX | OR_GPCM_EHTR | OR_GPCM_EAD) 597 598 #define CONFIG_SYS_BR2_PRELIM CONFIG_SYS_VSC7385_BR_PRELIM 599 #define CONFIG_SYS_OR2_PRELIM CONFIG_SYS_VSC7385_OR_PRELIM 600 601 /* The size of the VSC7385 firmware image */ 602 #define CONFIG_VSC7385_IMAGE_SIZE 8192 603 #endif 604 605 /* 606 * Config the L2 Cache as L2 SRAM 607 */ 608 #if defined(CONFIG_SPL_BUILD) 609 #if defined(CONFIG_SDCARD) || defined(CONFIG_SPIFLASH) 610 #define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000 611 #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR 612 #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) 613 #define CONFIG_SPL_RELOC_TEXT_BASE 0xf8f81000 614 #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L2_ADDR + 112 * 1024) 615 #define CONFIG_SPL_RELOC_STACK (CONFIG_SYS_INIT_L2_ADDR + 116 * 1024) 616 #define CONFIG_SPL_RELOC_STACK_SIZE (32 << 10) 617 #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SYS_INIT_L2_ADDR + 148 * 1024) 618 #if defined(CONFIG_P2020RDB) 619 #define CONFIG_SPL_RELOC_MALLOC_SIZE (364 << 10) 620 #else 621 #define CONFIG_SPL_RELOC_MALLOC_SIZE (108 << 10) 622 #endif 623 #elif defined(CONFIG_NAND) 624 #ifdef CONFIG_TPL_BUILD 625 #define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000 626 #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR 627 #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) 628 #define CONFIG_SPL_RELOC_TEXT_BASE 0xf8f81000 629 #define CONFIG_SPL_RELOC_STACK (CONFIG_SYS_INIT_L2_ADDR + 192 * 1024) 630 #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SYS_INIT_L2_ADDR + 208 * 1024) 631 #define CONFIG_SPL_RELOC_MALLOC_SIZE (48 << 10) 632 #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L2_ADDR + 176 * 1024) 633 #else 634 #define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000 635 #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR 636 #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) 637 #define CONFIG_SPL_RELOC_TEXT_BASE (CONFIG_SYS_INIT_L2_END - 0x2000) 638 #define CONFIG_SPL_RELOC_STACK ((CONFIG_SYS_INIT_L2_END - 1) & ~0xF) 639 #endif /* CONFIG_TPL_BUILD */ 640 #endif 641 #endif 642 643 /* Serial Port - controlled on board with jumper J8 644 * open - index 2 645 * shorted - index 1 646 */ 647 #define CONFIG_CONS_INDEX 1 648 #undef CONFIG_SERIAL_SOFTWARE_FIFO 649 #define CONFIG_SYS_NS16550_SERIAL 650 #define CONFIG_SYS_NS16550_REG_SIZE 1 651 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) 652 #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_INIT_MINIMAL) 653 #define CONFIG_NS16550_MIN_FUNCTIONS 654 #endif 655 656 #define CONFIG_SYS_BAUDRATE_TABLE \ 657 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} 658 659 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) 660 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) 661 662 /* I2C */ 663 #define CONFIG_SYS_I2C 664 #define CONFIG_SYS_I2C_FSL 665 #define CONFIG_SYS_FSL_I2C_SPEED 400000 666 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 667 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 668 #define CONFIG_SYS_FSL_I2C2_SPEED 400000 669 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F 670 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100 671 #define CONFIG_SYS_I2C_NOPROBES { {0, 0x29} } 672 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x52 673 #define CONFIG_SYS_SPD_BUS_NUM 1 /* For rom_loc and flash bank */ 674 675 /* 676 * I2C2 EEPROM 677 */ 678 #undef CONFIG_ID_EEPROM 679 680 #define CONFIG_RTC_PT7C4338 681 #define CONFIG_SYS_I2C_RTC_ADDR 0x68 682 #define CONFIG_SYS_I2C_PCA9557_ADDR 0x18 683 684 /* enable read and write access to EEPROM */ 685 #define CONFIG_CMD_EEPROM 686 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 687 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 688 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 689 690 /* 691 * eSPI - Enhanced SPI 692 */ 693 #define CONFIG_HARD_SPI 694 695 #if defined(CONFIG_SPI_FLASH) 696 #define CONFIG_SF_DEFAULT_SPEED 10000000 697 #define CONFIG_SF_DEFAULT_MODE 0 698 #endif 699 700 #if defined(CONFIG_PCI) 701 /* 702 * General PCI 703 * Memory space is mapped 1-1, but I/O space must start from 0. 704 */ 705 706 /* controller 2, direct to uli, tgtid 2, Base address 9000 */ 707 #define CONFIG_SYS_PCIE2_NAME "PCIe SLOT" 708 #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000 709 #ifdef CONFIG_PHYS_64BIT 710 #define CONFIG_SYS_PCIE2_MEM_BUS 0xc0000000 711 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull 712 #else 713 #define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000 714 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000 715 #endif 716 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */ 717 #define CONFIG_SYS_PCIE2_IO_VIRT 0xffc10000 718 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 719 #ifdef CONFIG_PHYS_64BIT 720 #define CONFIG_SYS_PCIE2_IO_PHYS 0xfffc10000ull 721 #else 722 #define CONFIG_SYS_PCIE2_IO_PHYS 0xffc10000 723 #endif 724 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ 725 726 /* controller 1, Slot 2, tgtid 1, Base address a000 */ 727 #define CONFIG_SYS_PCIE1_NAME "mini PCIe SLOT" 728 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 729 #ifdef CONFIG_PHYS_64BIT 730 #define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000 731 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull 732 #else 733 #define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000 734 #define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000 735 #endif 736 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ 737 #define CONFIG_SYS_PCIE1_IO_VIRT 0xffc00000 738 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 739 #ifdef CONFIG_PHYS_64BIT 740 #define CONFIG_SYS_PCIE1_IO_PHYS 0xfffc00000ull 741 #else 742 #define CONFIG_SYS_PCIE1_IO_PHYS 0xffc00000 743 #endif 744 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ 745 746 #define CONFIG_PCI_PNP /* do pci plug-and-play */ 747 #define CONFIG_CMD_PCI 748 749 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 750 #define CONFIG_DOS_PARTITION 751 #endif /* CONFIG_PCI */ 752 753 #if defined(CONFIG_TSEC_ENET) 754 #define CONFIG_MII /* MII PHY management */ 755 #define CONFIG_TSEC1 756 #define CONFIG_TSEC1_NAME "eTSEC1" 757 #define CONFIG_TSEC2 758 #define CONFIG_TSEC2_NAME "eTSEC2" 759 #define CONFIG_TSEC3 760 #define CONFIG_TSEC3_NAME "eTSEC3" 761 762 #define TSEC1_PHY_ADDR 2 763 #define TSEC2_PHY_ADDR 0 764 #define TSEC3_PHY_ADDR 1 765 766 #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 767 #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 768 #define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 769 770 #define TSEC1_PHYIDX 0 771 #define TSEC2_PHYIDX 0 772 #define TSEC3_PHYIDX 0 773 774 #define CONFIG_ETHPRIME "eTSEC1" 775 776 #define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */ 777 778 #define CONFIG_HAS_ETH0 779 #define CONFIG_HAS_ETH1 780 #define CONFIG_HAS_ETH2 781 #endif /* CONFIG_TSEC_ENET */ 782 783 #ifdef CONFIG_QE 784 /* QE microcode/firmware address */ 785 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR 786 #define CONFIG_SYS_QE_FW_ADDR 0xefec0000 787 #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 788 #endif /* CONFIG_QE */ 789 790 #ifdef CONFIG_P1025RDB 791 /* 792 * QE UEC ethernet configuration 793 */ 794 #define CONFIG_MIIM_ADDRESS (CONFIG_SYS_CCSRBAR + 0x82120) 795 796 #undef CONFIG_UEC_ETH 797 #define CONFIG_PHY_MODE_NEED_CHANGE 798 799 #define CONFIG_UEC_ETH1 /* ETH1 */ 800 #define CONFIG_HAS_ETH0 801 802 #ifdef CONFIG_UEC_ETH1 803 #define CONFIG_SYS_UEC1_UCC_NUM 0 /* UCC1 */ 804 #define CONFIG_SYS_UEC1_RX_CLK QE_CLK12 /* CLK12 for MII */ 805 #define CONFIG_SYS_UEC1_TX_CLK QE_CLK9 /* CLK9 for MII */ 806 #define CONFIG_SYS_UEC1_ETH_TYPE FAST_ETH 807 #define CONFIG_SYS_UEC1_PHY_ADDR 0x0 /* 0x0 for MII */ 808 #define CONFIG_SYS_UEC1_INTERFACE_TYPE PHY_INTERFACE_MODE_RMII 809 #define CONFIG_SYS_UEC1_INTERFACE_SPEED 100 810 #endif /* CONFIG_UEC_ETH1 */ 811 812 #define CONFIG_UEC_ETH5 /* ETH5 */ 813 #define CONFIG_HAS_ETH1 814 815 #ifdef CONFIG_UEC_ETH5 816 #define CONFIG_SYS_UEC5_UCC_NUM 4 /* UCC5 */ 817 #define CONFIG_SYS_UEC5_RX_CLK QE_CLK_NONE 818 #define CONFIG_SYS_UEC5_TX_CLK QE_CLK13 /* CLK 13 for RMII */ 819 #define CONFIG_SYS_UEC5_ETH_TYPE FAST_ETH 820 #define CONFIG_SYS_UEC5_PHY_ADDR 0x3 /* 0x3 for RMII */ 821 #define CONFIG_SYS_UEC5_INTERFACE_TYPE PHY_INTERFACE_MODE_RMII 822 #define CONFIG_SYS_UEC5_INTERFACE_SPEED 100 823 #endif /* CONFIG_UEC_ETH5 */ 824 #endif /* CONFIG_P1025RDB */ 825 826 /* 827 * Environment 828 */ 829 #ifdef CONFIG_SPIFLASH 830 #define CONFIG_ENV_IS_IN_SPI_FLASH 831 #define CONFIG_ENV_SPI_BUS 0 832 #define CONFIG_ENV_SPI_CS 0 833 #define CONFIG_ENV_SPI_MAX_HZ 10000000 834 #define CONFIG_ENV_SPI_MODE 0 835 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */ 836 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ 837 #define CONFIG_ENV_SECT_SIZE 0x10000 838 #elif defined(CONFIG_SDCARD) 839 #define CONFIG_ENV_IS_IN_MMC 840 #define CONFIG_FSL_FIXED_MMC_LOCATION 841 #define CONFIG_ENV_SIZE 0x2000 842 #define CONFIG_SYS_MMC_ENV_DEV 0 843 #elif defined(CONFIG_NAND) 844 #ifdef CONFIG_TPL_BUILD 845 #define CONFIG_ENV_SIZE 0x2000 846 #define CONFIG_ENV_ADDR (CONFIG_SYS_INIT_L2_ADDR + (160 << 10)) 847 #else 848 #define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE 849 #endif 850 #define CONFIG_ENV_IS_IN_NAND 851 #define CONFIG_ENV_OFFSET (1024 * 1024) 852 #define CONFIG_ENV_RANGE (3 * CONFIG_ENV_SIZE) 853 #elif defined(CONFIG_SYS_RAMBOOT) 854 #define CONFIG_ENV_IS_NOWHERE /* Store ENV in memory only */ 855 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) 856 #define CONFIG_ENV_SIZE 0x2000 857 #else 858 #define CONFIG_ENV_IS_IN_FLASH 859 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) 860 #define CONFIG_ENV_SIZE 0x2000 861 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ 862 #endif 863 864 #define CONFIG_LOADS_ECHO /* echo on for serial download */ 865 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ 866 867 /* 868 * Command line configuration. 869 */ 870 #define CONFIG_CMD_IRQ 871 #define CONFIG_CMD_DATE 872 #define CONFIG_CMD_REGINFO 873 874 /* 875 * USB 876 */ 877 #define CONFIG_HAS_FSL_DR_USB 878 879 #if defined(CONFIG_HAS_FSL_DR_USB) 880 #define CONFIG_USB_EHCI 881 882 #ifdef CONFIG_USB_EHCI 883 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 884 #define CONFIG_USB_EHCI_FSL 885 #define CONFIG_USB_STORAGE 886 #endif 887 #endif 888 889 #if defined(CONFIG_P1020RDB_PD) 890 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1 891 #endif 892 893 #define CONFIG_MMC 894 895 #ifdef CONFIG_MMC 896 #define CONFIG_FSL_ESDHC 897 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR 898 #define CONFIG_GENERIC_MMC 899 #endif 900 901 #if defined(CONFIG_MMC) || defined(CONFIG_USB_EHCI) \ 902 || defined(CONFIG_FSL_SATA) 903 #define CONFIG_DOS_PARTITION 904 #endif 905 906 #undef CONFIG_WATCHDOG /* watchdog disabled */ 907 908 /* 909 * Miscellaneous configurable options 910 */ 911 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 912 #define CONFIG_CMDLINE_EDITING /* Command-line editing */ 913 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 914 #if defined(CONFIG_CMD_KGDB) 915 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 916 #else 917 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 918 #endif 919 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) 920 /* Print Buffer Size */ 921 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 922 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */ 923 924 /* 925 * For booting Linux, the board info and command line data 926 * have to be in the first 64 MB of memory, since this is 927 * the maximum mapped by the Linux kernel during initialization. 928 */ 929 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory for Linux*/ 930 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 931 932 #if defined(CONFIG_CMD_KGDB) 933 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 934 #endif 935 936 /* 937 * Environment Configuration 938 */ 939 #define CONFIG_HOSTNAME unknown 940 #define CONFIG_ROOTPATH "/opt/nfsroot" 941 #define CONFIG_BOOTFILE "uImage" 942 #define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */ 943 944 /* default location for tftp and bootm */ 945 #define CONFIG_LOADADDR 1000000 946 947 #define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */ 948 #define CONFIG_BOOTARGS /* the boot command will set bootargs */ 949 950 #define CONFIG_BAUDRATE 115200 951 952 #ifdef __SW_BOOT_NOR 953 #define __NOR_RST_CMD \ 954 norboot=i2c dev 1; i2c mw 18 1 __SW_BOOT_NOR 1; \ 955 i2c mw 18 3 __SW_BOOT_MASK 1; reset 956 #endif 957 #ifdef __SW_BOOT_SPI 958 #define __SPI_RST_CMD \ 959 spiboot=i2c dev 1; i2c mw 18 1 __SW_BOOT_SPI 1; \ 960 i2c mw 18 3 __SW_BOOT_MASK 1; reset 961 #endif 962 #ifdef __SW_BOOT_SD 963 #define __SD_RST_CMD \ 964 sdboot=i2c dev 1; i2c mw 18 1 __SW_BOOT_SD 1; \ 965 i2c mw 18 3 __SW_BOOT_MASK 1; reset 966 #endif 967 #ifdef __SW_BOOT_NAND 968 #define __NAND_RST_CMD \ 969 nandboot=i2c dev 1; i2c mw 18 1 __SW_BOOT_NAND 1; \ 970 i2c mw 18 3 __SW_BOOT_MASK 1; reset 971 #endif 972 #ifdef __SW_BOOT_PCIE 973 #define __PCIE_RST_CMD \ 974 pciboot=i2c dev 1; i2c mw 18 1 __SW_BOOT_PCIE 1; \ 975 i2c mw 18 3 __SW_BOOT_MASK 1; reset 976 #endif 977 978 #define CONFIG_EXTRA_ENV_SETTINGS \ 979 "netdev=eth0\0" \ 980 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ 981 "loadaddr=1000000\0" \ 982 "bootfile=uImage\0" \ 983 "tftpflash=tftpboot $loadaddr $uboot; " \ 984 "protect off " __stringify(CONFIG_SYS_TEXT_BASE) " +$filesize; " \ 985 "erase " __stringify(CONFIG_SYS_TEXT_BASE) " +$filesize; " \ 986 "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) " $filesize; " \ 987 "protect on " __stringify(CONFIG_SYS_TEXT_BASE) " +$filesize; " \ 988 "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) " $filesize\0" \ 989 "hwconfig=usb1:dr_mode=host,phy_type=ulpi\0" \ 990 "consoledev=ttyS0\0" \ 991 "ramdiskaddr=2000000\0" \ 992 "ramdiskfile=rootfs.ext2.gz.uboot\0" \ 993 "fdtaddr=c00000\0" \ 994 "bdev=sda1\0" \ 995 "jffs2nor=mtdblock3\0" \ 996 "norbootaddr=ef080000\0" \ 997 "norfdtaddr=ef040000\0" \ 998 "jffs2nand=mtdblock9\0" \ 999 "nandbootaddr=100000\0" \ 1000 "nandfdtaddr=80000\0" \ 1001 "ramdisk_size=120000\0" \ 1002 "map_lowernorbank=i2c dev 1; i2c mw 18 1 02 1; i2c mw 18 3 fd 1\0" \ 1003 "map_uppernorbank=i2c dev 1; i2c mw 18 1 00 1; i2c mw 18 3 fd 1\0" \ 1004 __stringify(__NOR_RST_CMD)"\0" \ 1005 __stringify(__SPI_RST_CMD)"\0" \ 1006 __stringify(__SD_RST_CMD)"\0" \ 1007 __stringify(__NAND_RST_CMD)"\0" \ 1008 __stringify(__PCIE_RST_CMD)"\0" 1009 1010 #define CONFIG_NFSBOOTCOMMAND \ 1011 "setenv bootargs root=/dev/nfs rw " \ 1012 "nfsroot=$serverip:$rootpath " \ 1013 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 1014 "console=$consoledev,$baudrate $othbootargs;" \ 1015 "tftp $loadaddr $bootfile;" \ 1016 "tftp $fdtaddr $fdtfile;" \ 1017 "bootm $loadaddr - $fdtaddr" 1018 1019 #define CONFIG_HDBOOT \ 1020 "setenv bootargs root=/dev/$bdev rw rootdelay=30 " \ 1021 "console=$consoledev,$baudrate $othbootargs;" \ 1022 "usb start;" \ 1023 "ext2load usb 0:1 $loadaddr /boot/$bootfile;" \ 1024 "ext2load usb 0:1 $fdtaddr /boot/$fdtfile;" \ 1025 "bootm $loadaddr - $fdtaddr" 1026 1027 #define CONFIG_USB_FAT_BOOT \ 1028 "setenv bootargs root=/dev/ram rw " \ 1029 "console=$consoledev,$baudrate $othbootargs " \ 1030 "ramdisk_size=$ramdisk_size;" \ 1031 "usb start;" \ 1032 "fatload usb 0:2 $loadaddr $bootfile;" \ 1033 "fatload usb 0:2 $fdtaddr $fdtfile;" \ 1034 "fatload usb 0:2 $ramdiskaddr $ramdiskfile;" \ 1035 "bootm $loadaddr $ramdiskaddr $fdtaddr" 1036 1037 #define CONFIG_USB_EXT2_BOOT \ 1038 "setenv bootargs root=/dev/ram rw " \ 1039 "console=$consoledev,$baudrate $othbootargs " \ 1040 "ramdisk_size=$ramdisk_size;" \ 1041 "usb start;" \ 1042 "ext2load usb 0:4 $loadaddr $bootfile;" \ 1043 "ext2load usb 0:4 $fdtaddr $fdtfile;" \ 1044 "ext2load usb 0:4 $ramdiskaddr $ramdiskfile;" \ 1045 "bootm $loadaddr $ramdiskaddr $fdtaddr" 1046 1047 #define CONFIG_NORBOOT \ 1048 "setenv bootargs root=/dev/$jffs2nor rw " \ 1049 "console=$consoledev,$baudrate rootfstype=jffs2 $othbootargs;" \ 1050 "bootm $norbootaddr - $norfdtaddr" 1051 1052 #define CONFIG_RAMBOOTCOMMAND \ 1053 "setenv bootargs root=/dev/ram rw " \ 1054 "console=$consoledev,$baudrate $othbootargs " \ 1055 "ramdisk_size=$ramdisk_size;" \ 1056 "tftp $ramdiskaddr $ramdiskfile;" \ 1057 "tftp $loadaddr $bootfile;" \ 1058 "tftp $fdtaddr $fdtfile;" \ 1059 "bootm $loadaddr $ramdiskaddr $fdtaddr" 1060 1061 #define CONFIG_BOOTCOMMAND CONFIG_HDBOOT 1062 1063 #endif /* __CONFIG_H */ 1064