1 /* 2 * Copyright 2010-2011 Freescale Semiconductor, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 /* 8 * QorIQ RDB boards configuration file 9 */ 10 #ifndef __CONFIG_H 11 #define __CONFIG_H 12 13 #define CONFIG_DISPLAY_BOARDINFO 14 15 #if defined(CONFIG_P1020MBG) 16 #define CONFIG_BOARDNAME "P1020MBG-PC" 17 #define CONFIG_P1020 18 #define CONFIG_VSC7385_ENET 19 #define CONFIG_SLIC 20 #define __SW_BOOT_MASK 0x03 21 #define __SW_BOOT_NOR 0xe4 22 #define __SW_BOOT_SD 0x54 23 #define CONFIG_SYS_L2_SIZE (256 << 10) 24 #endif 25 26 #if defined(CONFIG_P1020UTM) 27 #define CONFIG_BOARDNAME "P1020UTM-PC" 28 #define CONFIG_P1020 29 #define __SW_BOOT_MASK 0x03 30 #define __SW_BOOT_NOR 0xe0 31 #define __SW_BOOT_SD 0x50 32 #define CONFIG_SYS_L2_SIZE (256 << 10) 33 #endif 34 35 #if defined(CONFIG_P1020RDB_PC) 36 #define CONFIG_BOARDNAME "P1020RDB-PC" 37 #define CONFIG_NAND_FSL_ELBC 38 #define CONFIG_P1020 39 #define CONFIG_VSC7385_ENET 40 #define CONFIG_SLIC 41 #define __SW_BOOT_MASK 0x03 42 #define __SW_BOOT_NOR 0x5c 43 #define __SW_BOOT_SPI 0x1c 44 #define __SW_BOOT_SD 0x9c 45 #define __SW_BOOT_NAND 0xec 46 #define __SW_BOOT_PCIE 0x6c 47 #define CONFIG_SYS_L2_SIZE (256 << 10) 48 #endif 49 50 /* 51 * P1020RDB-PD board has user selectable switches for evaluating different 52 * frequency and boot options for the P1020 device. The table that 53 * follow describe the available options. The front six binary number was in 54 * accordance with SW3[1:6]. 55 * 111101 533 533 267 667 NOR Core0 boot; Core1 hold-off 56 * 101101 667 667 333 667 NOR Core0 boot; Core1 hold-off 57 * 011001 800 800 400 667 NOR Core0 boot; Core1 hold-off 58 * 001001 800 800 400 667 SD/MMC Core0 boot; Core1 hold-off 59 * 001101 800 800 400 667 SPI Core0 boot; Core1 hold-off 60 * 010001 800 800 400 667 NAND Core0 boot; Core1 hold-off 61 * 011101 800 800 400 667 PCIe-2 Core0 boot; Core1 hold-off 62 */ 63 #if defined(CONFIG_P1020RDB_PD) 64 #define CONFIG_BOARDNAME "P1020RDB-PD" 65 #define CONFIG_NAND_FSL_ELBC 66 #define CONFIG_P1020 67 #define CONFIG_VSC7385_ENET 68 #define CONFIG_SLIC 69 #define __SW_BOOT_MASK 0x03 70 #define __SW_BOOT_NOR 0x64 71 #define __SW_BOOT_SPI 0x34 72 #define __SW_BOOT_SD 0x24 73 #define __SW_BOOT_NAND 0x44 74 #define __SW_BOOT_PCIE 0x74 75 #define CONFIG_SYS_L2_SIZE (256 << 10) 76 /* 77 * Dynamic MTD Partition support with mtdparts 78 */ 79 #define CONFIG_MTD_DEVICE 80 #define CONFIG_MTD_PARTITIONS 81 #define CONFIG_CMD_MTDPARTS 82 #define CONFIG_FLASH_CFI_MTD 83 #define MTDIDS_DEFAULT "nor0=ec000000.nor" 84 #define MTDPARTS_DEFAULT "mtdparts=ec000000.nor:128k(dtb),6016k(kernel)," \ 85 "57088k(fs),1m(vsc7385-firmware),1280k(u-boot)" 86 #endif 87 88 #if defined(CONFIG_P1021RDB) 89 #define CONFIG_BOARDNAME "P1021RDB-PC" 90 #define CONFIG_NAND_FSL_ELBC 91 #define CONFIG_P1021 92 #define CONFIG_QE 93 #define CONFIG_VSC7385_ENET 94 #define CONFIG_SYS_LBC_LBCR 0x00080000 /* Implement conversion of 95 addresses in the LBC */ 96 #define __SW_BOOT_MASK 0x03 97 #define __SW_BOOT_NOR 0x5c 98 #define __SW_BOOT_SPI 0x1c 99 #define __SW_BOOT_SD 0x9c 100 #define __SW_BOOT_NAND 0xec 101 #define __SW_BOOT_PCIE 0x6c 102 #define CONFIG_SYS_L2_SIZE (256 << 10) 103 /* 104 * Dynamic MTD Partition support with mtdparts 105 */ 106 #define CONFIG_MTD_DEVICE 107 #define CONFIG_MTD_PARTITIONS 108 #define CONFIG_CMD_MTDPARTS 109 #define CONFIG_FLASH_CFI_MTD 110 #ifdef CONFIG_PHYS_64BIT 111 #define MTDIDS_DEFAULT "nor0=fef000000.nor" 112 #define MTDPARTS_DEFAULT "mtdparts=fef000000.nor:256k(vsc7385-firmware)," \ 113 "256k(dtb),4608k(kernel),9728k(fs)," \ 114 "256k(qe-ucode-firmware),1280k(u-boot)" 115 #else 116 #define MTDIDS_DEFAULT "nor0=ef000000.nor" 117 #define MTDPARTS_DEFAULT "mtdparts=ef000000.nor:256k(vsc7385-firmware)," \ 118 "256k(dtb),4608k(kernel),9728k(fs)," \ 119 "256k(qe-ucode-firmware),1280k(u-boot)" 120 #endif 121 #endif 122 123 #if defined(CONFIG_P1024RDB) 124 #define CONFIG_BOARDNAME "P1024RDB" 125 #define CONFIG_NAND_FSL_ELBC 126 #define CONFIG_P1024 127 #define CONFIG_SLIC 128 #define __SW_BOOT_MASK 0xf3 129 #define __SW_BOOT_NOR 0x00 130 #define __SW_BOOT_SPI 0x08 131 #define __SW_BOOT_SD 0x04 132 #define __SW_BOOT_NAND 0x0c 133 #define CONFIG_SYS_L2_SIZE (256 << 10) 134 #endif 135 136 #if defined(CONFIG_P1025RDB) 137 #define CONFIG_BOARDNAME "P1025RDB" 138 #define CONFIG_NAND_FSL_ELBC 139 #define CONFIG_P1025 140 #define CONFIG_QE 141 #define CONFIG_SLIC 142 143 #define CONFIG_SYS_LBC_LBCR 0x00080000 /* Implement conversion of 144 addresses in the LBC */ 145 #define __SW_BOOT_MASK 0xf3 146 #define __SW_BOOT_NOR 0x00 147 #define __SW_BOOT_SPI 0x08 148 #define __SW_BOOT_SD 0x04 149 #define __SW_BOOT_NAND 0x0c 150 #define CONFIG_SYS_L2_SIZE (256 << 10) 151 #endif 152 153 #if defined(CONFIG_P2020RDB) 154 #define CONFIG_BOARDNAME "P2020RDB-PCA" 155 #define CONFIG_NAND_FSL_ELBC 156 #define CONFIG_P2020 157 #define CONFIG_VSC7385_ENET 158 #define __SW_BOOT_MASK 0x03 159 #define __SW_BOOT_NOR 0xc8 160 #define __SW_BOOT_SPI 0x28 161 #define __SW_BOOT_SD 0x68 /* or 0x18 */ 162 #define __SW_BOOT_NAND 0xe8 163 #define __SW_BOOT_PCIE 0xa8 164 #define CONFIG_SYS_L2_SIZE (512 << 10) 165 /* 166 * Dynamic MTD Partition support with mtdparts 167 */ 168 #define CONFIG_MTD_DEVICE 169 #define CONFIG_MTD_PARTITIONS 170 #define CONFIG_CMD_MTDPARTS 171 #define CONFIG_FLASH_CFI_MTD 172 #ifdef CONFIG_PHYS_64BIT 173 #define MTDIDS_DEFAULT "nor0=fef000000.nor" 174 #define MTDPARTS_DEFAULT "mtdparts=fef000000.nor:256k(vsc7385-firmware)," \ 175 "256k(dtb),4608k(kernel),9984k(fs),1280k(u-boot)" 176 #else 177 #define MTDIDS_DEFAULT "nor0=ef000000.nor" 178 #define MTDPARTS_DEFAULT "mtdparts=ef000000.nor:256k(vsc7385-firmware)," \ 179 "256k(dtb),4608k(kernel),9984k(fs),1280k(u-boot)" 180 #endif 181 #endif 182 183 #ifdef CONFIG_SDCARD 184 #define CONFIG_SPL_MMC_MINIMAL 185 #define CONFIG_SPL_FLUSH_IMAGE 186 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 187 #define CONFIG_FSL_LAW /* Use common FSL init code */ 188 #define CONFIG_SYS_TEXT_BASE 0x11001000 189 #define CONFIG_SPL_TEXT_BASE 0xf8f81000 190 #define CONFIG_SPL_PAD_TO 0x20000 191 #define CONFIG_SPL_MAX_SIZE (128 * 1024) 192 #define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10) 193 #define CONFIG_SYS_MMC_U_BOOT_DST (0x11000000) 194 #define CONFIG_SYS_MMC_U_BOOT_START (0x11000000) 195 #define CONFIG_SYS_MMC_U_BOOT_OFFS (128 << 10) 196 #define CONFIG_SYS_MPC85XX_NO_RESETVEC 197 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds" 198 #define CONFIG_SPL_MMC_BOOT 199 #ifdef CONFIG_SPL_BUILD 200 #define CONFIG_SPL_COMMON_INIT_DDR 201 #endif 202 #endif 203 204 #ifdef CONFIG_SPIFLASH 205 #define CONFIG_SPL_SPI_FLASH_MINIMAL 206 #define CONFIG_SPL_FLUSH_IMAGE 207 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 208 #define CONFIG_FSL_LAW /* Use common FSL init code */ 209 #define CONFIG_SYS_TEXT_BASE 0x11001000 210 #define CONFIG_SPL_TEXT_BASE 0xf8f81000 211 #define CONFIG_SPL_PAD_TO 0x20000 212 #define CONFIG_SPL_MAX_SIZE (128 * 1024) 213 #define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (768 << 10) 214 #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x11000000) 215 #define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x11000000) 216 #define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (128 << 10) 217 #define CONFIG_SYS_MPC85XX_NO_RESETVEC 218 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds" 219 #define CONFIG_SPL_SPI_BOOT 220 #ifdef CONFIG_SPL_BUILD 221 #define CONFIG_SPL_COMMON_INIT_DDR 222 #endif 223 #endif 224 225 #ifdef CONFIG_NAND 226 #ifdef CONFIG_TPL_BUILD 227 #define CONFIG_SPL_NAND_BOOT 228 #define CONFIG_SPL_FLUSH_IMAGE 229 #define CONFIG_SPL_NAND_INIT 230 #define CONFIG_SPL_COMMON_INIT_DDR 231 #define CONFIG_SPL_MAX_SIZE (128 << 10) 232 #define CONFIG_SPL_TEXT_BASE 0xf8f81000 233 #define CONFIG_SYS_MPC85XX_NO_RESETVEC 234 #define CONFIG_SYS_NAND_U_BOOT_SIZE (832 << 10) 235 #define CONFIG_SYS_NAND_U_BOOT_DST (0x11000000) 236 #define CONFIG_SYS_NAND_U_BOOT_START (0x11000000) 237 #define CONFIG_SYS_NAND_U_BOOT_OFFS ((128 + 128) << 10) 238 #elif defined(CONFIG_SPL_BUILD) 239 #define CONFIG_SPL_INIT_MINIMAL 240 #define CONFIG_SPL_FLUSH_IMAGE 241 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 242 #define CONFIG_SPL_TEXT_BASE 0xff800000 243 #define CONFIG_SPL_MAX_SIZE 4096 244 #define CONFIG_SYS_NAND_U_BOOT_SIZE (128 << 10) 245 #define CONFIG_SYS_NAND_U_BOOT_DST 0xf8f80000 246 #define CONFIG_SYS_NAND_U_BOOT_START 0xf8f80000 247 #define CONFIG_SYS_NAND_U_BOOT_OFFS (128 << 10) 248 #endif /* not CONFIG_TPL_BUILD */ 249 250 #define CONFIG_SPL_PAD_TO 0x20000 251 #define CONFIG_TPL_PAD_TO 0x20000 252 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 253 #define CONFIG_SYS_TEXT_BASE 0x11001000 254 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds" 255 #endif 256 257 #ifndef CONFIG_SYS_TEXT_BASE 258 #define CONFIG_SYS_TEXT_BASE 0xeff40000 259 #endif 260 261 #ifndef CONFIG_RESET_VECTOR_ADDRESS 262 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc 263 #endif 264 265 #ifndef CONFIG_SYS_MONITOR_BASE 266 #ifdef CONFIG_SPL_BUILD 267 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE 268 #else 269 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 270 #endif 271 #endif 272 273 /* High Level Configuration Options */ 274 #define CONFIG_BOOKE 275 #define CONFIG_E500 276 277 #define CONFIG_MP 278 279 #define CONFIG_FSL_ELBC 280 #define CONFIG_PCI 281 #define CONFIG_PCIE1 /* PCIE controller 1 (slot 1) */ 282 #define CONFIG_PCIE2 /* PCIE controller 2 (slot 2) */ 283 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ 284 #define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */ 285 #define CONFIG_FSL_PCIE_RESET /* need PCIe reset errata */ 286 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ 287 288 #define CONFIG_FSL_LAW 289 #define CONFIG_TSEC_ENET /* tsec ethernet support */ 290 #define CONFIG_ENV_OVERWRITE 291 292 #define CONFIG_CMD_SATA 293 #define CONFIG_SATA_SIL 294 #define CONFIG_SYS_SATA_MAX_DEVICE 2 295 #define CONFIG_LIBATA 296 #define CONFIG_LBA48 297 298 #if defined(CONFIG_P2020RDB) 299 #define CONFIG_SYS_CLK_FREQ 100000000 300 #else 301 #define CONFIG_SYS_CLK_FREQ 66666666 302 #endif 303 #define CONFIG_DDR_CLK_FREQ 66666666 304 305 #define CONFIG_HWCONFIG 306 /* 307 * These can be toggled for performance analysis, otherwise use default. 308 */ 309 #define CONFIG_L2_CACHE 310 #define CONFIG_BTB 311 312 #define CONFIG_BOARD_EARLY_INIT_F /* Call board_pre_init */ 313 314 #define CONFIG_ENABLE_36BIT_PHYS 315 316 #ifdef CONFIG_PHYS_64BIT 317 #define CONFIG_ADDR_MAP 1 318 #define CONFIG_SYS_NUM_ADDR_MAP 16 /* number of TLB1 entries */ 319 #endif 320 321 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ 322 #define CONFIG_SYS_MEMTEST_END 0x1fffffff 323 #define CONFIG_PANIC_HANG /* do not reset board on panic */ 324 325 #define CONFIG_SYS_CCSRBAR 0xffe00000 326 #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR 327 328 /* IN case of NAND bootloader relocate CCSRBAR in RAMboot code not in the 4k 329 SPL code*/ 330 #ifdef CONFIG_SPL_BUILD 331 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE 332 #endif 333 334 /* DDR Setup */ 335 #define CONFIG_SYS_FSL_DDR3 336 #define CONFIG_SYS_DDR_RAW_TIMING 337 #define CONFIG_DDR_SPD 338 #define CONFIG_SYS_SPD_BUS_NUM 1 339 #define SPD_EEPROM_ADDRESS 0x52 340 #undef CONFIG_FSL_DDR_INTERACTIVE 341 342 #if (defined(CONFIG_P1020MBG) || defined(CONFIG_P1020RDB_PD)) 343 #define CONFIG_SYS_SDRAM_SIZE_LAW LAW_SIZE_2G 344 #define CONFIG_CHIP_SELECTS_PER_CTRL 2 345 #else 346 #define CONFIG_SYS_SDRAM_SIZE_LAW LAW_SIZE_1G 347 #define CONFIG_CHIP_SELECTS_PER_CTRL 1 348 #endif 349 #define CONFIG_SYS_SDRAM_SIZE (1u << (CONFIG_SYS_SDRAM_SIZE_LAW - 19)) 350 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 351 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 352 353 #define CONFIG_NUM_DDR_CONTROLLERS 1 354 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 355 356 /* Default settings for DDR3 */ 357 #ifndef CONFIG_P2020RDB 358 #define CONFIG_SYS_DDR_CS0_BNDS 0x0000003f 359 #define CONFIG_SYS_DDR_CS0_CONFIG 0x80014302 360 #define CONFIG_SYS_DDR_CS0_CONFIG_2 0x00000000 361 #define CONFIG_SYS_DDR_CS1_BNDS 0x0040007f 362 #define CONFIG_SYS_DDR_CS1_CONFIG 0x80014302 363 #define CONFIG_SYS_DDR_CS1_CONFIG_2 0x00000000 364 365 #define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef 366 #define CONFIG_SYS_DDR_INIT_ADDR 0x00000000 367 #define CONFIG_SYS_DDR_INIT_EXT_ADDR 0x00000000 368 #define CONFIG_SYS_DDR_MODE_CONTROL 0x00000000 369 370 #define CONFIG_SYS_DDR_ZQ_CONTROL 0x89080600 371 #define CONFIG_SYS_DDR_WRLVL_CONTROL 0x8655A608 372 #define CONFIG_SYS_DDR_SR_CNTR 0x00000000 373 #define CONFIG_SYS_DDR_RCW_1 0x00000000 374 #define CONFIG_SYS_DDR_RCW_2 0x00000000 375 #define CONFIG_SYS_DDR_CONTROL 0xC70C0000 /* Type = DDR3 */ 376 #define CONFIG_SYS_DDR_CONTROL_2 0x04401050 377 #define CONFIG_SYS_DDR_TIMING_4 0x00220001 378 #define CONFIG_SYS_DDR_TIMING_5 0x03402400 379 380 #define CONFIG_SYS_DDR_TIMING_3 0x00020000 381 #define CONFIG_SYS_DDR_TIMING_0 0x00330004 382 #define CONFIG_SYS_DDR_TIMING_1 0x6f6B4846 383 #define CONFIG_SYS_DDR_TIMING_2 0x0FA8C8CF 384 #define CONFIG_SYS_DDR_CLK_CTRL 0x03000000 385 #define CONFIG_SYS_DDR_MODE_1 0x40461520 386 #define CONFIG_SYS_DDR_MODE_2 0x8000c000 387 #define CONFIG_SYS_DDR_INTERVAL 0x0C300000 388 #endif 389 390 #undef CONFIG_CLOCKS_IN_MHZ 391 392 /* 393 * Memory map 394 * 395 * 0x0000_0000 0x7fff_ffff DDR Up to 2GB cacheable 396 * 0x8000_0000 0xdfff_ffff PCI Express Mem 1.5G non-cacheable(PCIe * 3) 397 * 0xec00_0000 0xefff_ffff NOR flash Up to 64M non-cacheable CS0/1 398 * 0xf8f8_0000 0xf8ff_ffff L2 SRAM Up to 512K cacheable 399 * (early boot only) 400 * 0xff80_0000 0xff80_7fff NAND flash 32K non-cacheable CS1/0 401 * 0xff98_0000 0xff98_ffff PMC 64K non-cacheable CS2 402 * 0xffa0_0000 0xffaf_ffff CPLD 1M non-cacheable CS3 403 * 0xffb0_0000 0xffbf_ffff VSC7385 switch 1M non-cacheable CS2 404 * 0xffc0_0000 0xffc3_ffff PCI IO range 256k non-cacheable 405 * 0xffd0_0000 0xffd0_3fff L1 for stack 16K cacheable 406 * 0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable 407 */ 408 409 /* 410 * Local Bus Definitions 411 */ 412 #if (defined(CONFIG_P1020MBG) || defined(CONFIG_P1020RDB_PD)) 413 #define CONFIG_SYS_MAX_FLASH_SECT 512 /* 64M */ 414 #define CONFIG_SYS_FLASH_BASE 0xec000000 415 #elif defined(CONFIG_P1020UTM) 416 #define CONFIG_SYS_MAX_FLASH_SECT 256 /* 32M */ 417 #define CONFIG_SYS_FLASH_BASE 0xee000000 418 #else 419 #define CONFIG_SYS_MAX_FLASH_SECT 128 /* 16M */ 420 #define CONFIG_SYS_FLASH_BASE 0xef000000 421 #endif 422 423 #ifdef CONFIG_PHYS_64BIT 424 #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE) 425 #else 426 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE 427 #endif 428 429 #define CONFIG_FLASH_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) \ 430 | BR_PS_16 | BR_V) 431 432 #define CONFIG_FLASH_OR_PRELIM 0xfc000ff7 433 434 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS} 435 #define CONFIG_SYS_FLASH_QUIET_TEST 436 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 437 438 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ 439 440 #undef CONFIG_SYS_FLASH_CHECKSUM 441 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 442 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 443 444 #define CONFIG_FLASH_CFI_DRIVER 445 #define CONFIG_SYS_FLASH_CFI 446 #define CONFIG_SYS_FLASH_EMPTY_INFO 447 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 448 449 /* Nand Flash */ 450 #ifdef CONFIG_NAND_FSL_ELBC 451 #define CONFIG_SYS_NAND_BASE 0xff800000 452 #ifdef CONFIG_PHYS_64BIT 453 #define CONFIG_SYS_NAND_BASE_PHYS 0xfff800000ull 454 #else 455 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE 456 #endif 457 458 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } 459 #define CONFIG_SYS_MAX_NAND_DEVICE 1 460 #define CONFIG_CMD_NAND 461 #if defined(CONFIG_P1020RDB_PD) 462 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) 463 #else 464 #define CONFIG_SYS_NAND_BLOCK_SIZE (16 * 1024) 465 #endif 466 467 #define CONFIG_SYS_NAND_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 468 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ 469 | BR_PS_8 /* Port Size = 8 bit */ \ 470 | BR_MS_FCM /* MSEL = FCM */ \ 471 | BR_V) /* valid */ 472 #if defined(CONFIG_P1020RDB_PD) 473 #define CONFIG_SYS_NAND_OR_PRELIM (OR_AM_32KB \ 474 | OR_FCM_PGS /* Large Page*/ \ 475 | OR_FCM_CSCT \ 476 | OR_FCM_CST \ 477 | OR_FCM_CHT \ 478 | OR_FCM_SCY_1 \ 479 | OR_FCM_TRLX \ 480 | OR_FCM_EHTR) 481 #else 482 #define CONFIG_SYS_NAND_OR_PRELIM (OR_AM_32KB /* small page */ \ 483 | OR_FCM_CSCT \ 484 | OR_FCM_CST \ 485 | OR_FCM_CHT \ 486 | OR_FCM_SCY_1 \ 487 | OR_FCM_TRLX \ 488 | OR_FCM_EHTR) 489 #endif 490 #endif /* CONFIG_NAND_FSL_ELBC */ 491 492 #define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */ 493 494 #define CONFIG_SYS_INIT_RAM_LOCK 495 #define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* stack in RAM */ 496 #ifdef CONFIG_PHYS_64BIT 497 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf 498 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR 499 /* The assembler doesn't like typecast */ 500 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \ 501 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \ 502 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) 503 #else 504 /* Initial L1 address */ 505 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS CONFIG_SYS_INIT_RAM_ADDR 506 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0 507 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS 508 #endif 509 /* Size of used area in RAM */ 510 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 511 512 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ 513 GENERATED_GBL_DATA_SIZE) 514 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 515 516 #define CONFIG_SYS_MONITOR_LEN (768 * 1024) 517 #define CONFIG_SYS_MALLOC_LEN (1024 * 1024)/* Reserved for malloc */ 518 519 #define CONFIG_SYS_CPLD_BASE 0xffa00000 520 #ifdef CONFIG_PHYS_64BIT 521 #define CONFIG_SYS_CPLD_BASE_PHYS 0xfffa00000ull 522 #else 523 #define CONFIG_SYS_CPLD_BASE_PHYS CONFIG_SYS_CPLD_BASE 524 #endif 525 /* CPLD config size: 1Mb */ 526 #define CONFIG_CPLD_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE_PHYS) | \ 527 BR_PS_8 | BR_V) 528 #define CONFIG_CPLD_OR_PRELIM (0xfff009f7) 529 530 #define CONFIG_SYS_PMC_BASE 0xff980000 531 #define CONFIG_SYS_PMC_BASE_PHYS CONFIG_SYS_PMC_BASE 532 #define CONFIG_PMC_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_PMC_BASE_PHYS) | \ 533 BR_PS_8 | BR_V) 534 #define CONFIG_PMC_OR_PRELIM (OR_AM_64KB | OR_GPCM_CSNT | OR_GPCM_XACS | \ 535 OR_GPCM_SCY | OR_GPCM_TRLX | OR_GPCM_EHTR | \ 536 OR_GPCM_EAD) 537 538 #ifdef CONFIG_NAND 539 #define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Addr */ 540 #define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */ 541 #define CONFIG_SYS_BR1_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */ 542 #define CONFIG_SYS_OR1_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */ 543 #else 544 #define CONFIG_SYS_BR0_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */ 545 #define CONFIG_SYS_OR0_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */ 546 #ifdef CONFIG_NAND_FSL_ELBC 547 #define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Addr */ 548 #define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */ 549 #endif 550 #endif 551 #define CONFIG_SYS_BR3_PRELIM CONFIG_CPLD_BR_PRELIM /* CPLD Base Address */ 552 #define CONFIG_SYS_OR3_PRELIM CONFIG_CPLD_OR_PRELIM /* CPLD Options */ 553 554 /* Vsc7385 switch */ 555 #ifdef CONFIG_VSC7385_ENET 556 #define CONFIG_SYS_VSC7385_BASE 0xffb00000 557 558 #ifdef CONFIG_PHYS_64BIT 559 #define CONFIG_SYS_VSC7385_BASE_PHYS 0xfffb00000ull 560 #else 561 #define CONFIG_SYS_VSC7385_BASE_PHYS CONFIG_SYS_VSC7385_BASE 562 #endif 563 564 #define CONFIG_SYS_VSC7385_BR_PRELIM \ 565 (BR_PHYS_ADDR(CONFIG_SYS_VSC7385_BASE_PHYS) | BR_PS_8 | BR_V) 566 #define CONFIG_SYS_VSC7385_OR_PRELIM (OR_AM_128KB | OR_GPCM_CSNT | \ 567 OR_GPCM_XACS | OR_GPCM_SCY_15 | OR_GPCM_SETA | \ 568 OR_GPCM_TRLX | OR_GPCM_EHTR | OR_GPCM_EAD) 569 570 #define CONFIG_SYS_BR2_PRELIM CONFIG_SYS_VSC7385_BR_PRELIM 571 #define CONFIG_SYS_OR2_PRELIM CONFIG_SYS_VSC7385_OR_PRELIM 572 573 /* The size of the VSC7385 firmware image */ 574 #define CONFIG_VSC7385_IMAGE_SIZE 8192 575 #endif 576 577 /* 578 * Config the L2 Cache as L2 SRAM 579 */ 580 #if defined(CONFIG_SPL_BUILD) 581 #if defined(CONFIG_SDCARD) || defined(CONFIG_SPIFLASH) 582 #define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000 583 #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR 584 #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) 585 #define CONFIG_SPL_RELOC_TEXT_BASE 0xf8f81000 586 #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L2_ADDR + 112 * 1024) 587 #define CONFIG_SPL_RELOC_STACK (CONFIG_SYS_INIT_L2_ADDR + 116 * 1024) 588 #define CONFIG_SPL_RELOC_STACK_SIZE (32 << 10) 589 #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SYS_INIT_L2_ADDR + 148 * 1024) 590 #if defined(CONFIG_P2020RDB) 591 #define CONFIG_SPL_RELOC_MALLOC_SIZE (364 << 10) 592 #else 593 #define CONFIG_SPL_RELOC_MALLOC_SIZE (108 << 10) 594 #endif 595 #elif defined(CONFIG_NAND) 596 #ifdef CONFIG_TPL_BUILD 597 #define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000 598 #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR 599 #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) 600 #define CONFIG_SPL_RELOC_TEXT_BASE 0xf8f81000 601 #define CONFIG_SPL_RELOC_STACK (CONFIG_SYS_INIT_L2_ADDR + 192 * 1024) 602 #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SYS_INIT_L2_ADDR + 208 * 1024) 603 #define CONFIG_SPL_RELOC_MALLOC_SIZE (48 << 10) 604 #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L2_ADDR + 176 * 1024) 605 #else 606 #define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000 607 #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR 608 #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) 609 #define CONFIG_SPL_RELOC_TEXT_BASE (CONFIG_SYS_INIT_L2_END - 0x2000) 610 #define CONFIG_SPL_RELOC_STACK ((CONFIG_SYS_INIT_L2_END - 1) & ~0xF) 611 #endif /* CONFIG_TPL_BUILD */ 612 #endif 613 #endif 614 615 /* Serial Port - controlled on board with jumper J8 616 * open - index 2 617 * shorted - index 1 618 */ 619 #define CONFIG_CONS_INDEX 1 620 #undef CONFIG_SERIAL_SOFTWARE_FIFO 621 #define CONFIG_SYS_NS16550_SERIAL 622 #define CONFIG_SYS_NS16550_REG_SIZE 1 623 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) 624 #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_INIT_MINIMAL) 625 #define CONFIG_NS16550_MIN_FUNCTIONS 626 #endif 627 628 #define CONFIG_SYS_BAUDRATE_TABLE \ 629 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} 630 631 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) 632 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) 633 634 /* I2C */ 635 #define CONFIG_SYS_I2C 636 #define CONFIG_SYS_I2C_FSL 637 #define CONFIG_SYS_FSL_I2C_SPEED 400000 638 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 639 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 640 #define CONFIG_SYS_FSL_I2C2_SPEED 400000 641 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F 642 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100 643 #define CONFIG_SYS_I2C_NOPROBES { {0, 0x29} } 644 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x52 645 #define CONFIG_SYS_SPD_BUS_NUM 1 /* For rom_loc and flash bank */ 646 647 /* 648 * I2C2 EEPROM 649 */ 650 #undef CONFIG_ID_EEPROM 651 652 #define CONFIG_RTC_PT7C4338 653 #define CONFIG_SYS_I2C_RTC_ADDR 0x68 654 #define CONFIG_SYS_I2C_PCA9557_ADDR 0x18 655 656 /* enable read and write access to EEPROM */ 657 #define CONFIG_CMD_EEPROM 658 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 659 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 660 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 661 662 /* 663 * eSPI - Enhanced SPI 664 */ 665 #define CONFIG_HARD_SPI 666 667 #if defined(CONFIG_SPI_FLASH) 668 #define CONFIG_SF_DEFAULT_SPEED 10000000 669 #define CONFIG_SF_DEFAULT_MODE 0 670 #endif 671 672 #if defined(CONFIG_PCI) 673 /* 674 * General PCI 675 * Memory space is mapped 1-1, but I/O space must start from 0. 676 */ 677 678 /* controller 2, direct to uli, tgtid 2, Base address 9000 */ 679 #define CONFIG_SYS_PCIE2_NAME "PCIe SLOT" 680 #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000 681 #ifdef CONFIG_PHYS_64BIT 682 #define CONFIG_SYS_PCIE2_MEM_BUS 0xc0000000 683 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull 684 #else 685 #define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000 686 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000 687 #endif 688 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */ 689 #define CONFIG_SYS_PCIE2_IO_VIRT 0xffc10000 690 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 691 #ifdef CONFIG_PHYS_64BIT 692 #define CONFIG_SYS_PCIE2_IO_PHYS 0xfffc10000ull 693 #else 694 #define CONFIG_SYS_PCIE2_IO_PHYS 0xffc10000 695 #endif 696 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ 697 698 /* controller 1, Slot 2, tgtid 1, Base address a000 */ 699 #define CONFIG_SYS_PCIE1_NAME "mini PCIe SLOT" 700 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 701 #ifdef CONFIG_PHYS_64BIT 702 #define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000 703 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull 704 #else 705 #define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000 706 #define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000 707 #endif 708 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ 709 #define CONFIG_SYS_PCIE1_IO_VIRT 0xffc00000 710 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 711 #ifdef CONFIG_PHYS_64BIT 712 #define CONFIG_SYS_PCIE1_IO_PHYS 0xfffc00000ull 713 #else 714 #define CONFIG_SYS_PCIE1_IO_PHYS 0xffc00000 715 #endif 716 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ 717 718 #define CONFIG_PCI_PNP /* do pci plug-and-play */ 719 #define CONFIG_CMD_PCI 720 721 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 722 #define CONFIG_DOS_PARTITION 723 #endif /* CONFIG_PCI */ 724 725 #if defined(CONFIG_TSEC_ENET) 726 #define CONFIG_MII /* MII PHY management */ 727 #define CONFIG_TSEC1 728 #define CONFIG_TSEC1_NAME "eTSEC1" 729 #define CONFIG_TSEC2 730 #define CONFIG_TSEC2_NAME "eTSEC2" 731 #define CONFIG_TSEC3 732 #define CONFIG_TSEC3_NAME "eTSEC3" 733 734 #define TSEC1_PHY_ADDR 2 735 #define TSEC2_PHY_ADDR 0 736 #define TSEC3_PHY_ADDR 1 737 738 #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 739 #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 740 #define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 741 742 #define TSEC1_PHYIDX 0 743 #define TSEC2_PHYIDX 0 744 #define TSEC3_PHYIDX 0 745 746 #define CONFIG_ETHPRIME "eTSEC1" 747 748 #define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */ 749 750 #define CONFIG_HAS_ETH0 751 #define CONFIG_HAS_ETH1 752 #define CONFIG_HAS_ETH2 753 #endif /* CONFIG_TSEC_ENET */ 754 755 #ifdef CONFIG_QE 756 /* QE microcode/firmware address */ 757 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR 758 #define CONFIG_SYS_QE_FW_ADDR 0xefec0000 759 #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 760 #endif /* CONFIG_QE */ 761 762 #ifdef CONFIG_P1025RDB 763 /* 764 * QE UEC ethernet configuration 765 */ 766 #define CONFIG_MIIM_ADDRESS (CONFIG_SYS_CCSRBAR + 0x82120) 767 768 #undef CONFIG_UEC_ETH 769 #define CONFIG_PHY_MODE_NEED_CHANGE 770 771 #define CONFIG_UEC_ETH1 /* ETH1 */ 772 #define CONFIG_HAS_ETH0 773 774 #ifdef CONFIG_UEC_ETH1 775 #define CONFIG_SYS_UEC1_UCC_NUM 0 /* UCC1 */ 776 #define CONFIG_SYS_UEC1_RX_CLK QE_CLK12 /* CLK12 for MII */ 777 #define CONFIG_SYS_UEC1_TX_CLK QE_CLK9 /* CLK9 for MII */ 778 #define CONFIG_SYS_UEC1_ETH_TYPE FAST_ETH 779 #define CONFIG_SYS_UEC1_PHY_ADDR 0x0 /* 0x0 for MII */ 780 #define CONFIG_SYS_UEC1_INTERFACE_TYPE PHY_INTERFACE_MODE_RMII 781 #define CONFIG_SYS_UEC1_INTERFACE_SPEED 100 782 #endif /* CONFIG_UEC_ETH1 */ 783 784 #define CONFIG_UEC_ETH5 /* ETH5 */ 785 #define CONFIG_HAS_ETH1 786 787 #ifdef CONFIG_UEC_ETH5 788 #define CONFIG_SYS_UEC5_UCC_NUM 4 /* UCC5 */ 789 #define CONFIG_SYS_UEC5_RX_CLK QE_CLK_NONE 790 #define CONFIG_SYS_UEC5_TX_CLK QE_CLK13 /* CLK 13 for RMII */ 791 #define CONFIG_SYS_UEC5_ETH_TYPE FAST_ETH 792 #define CONFIG_SYS_UEC5_PHY_ADDR 0x3 /* 0x3 for RMII */ 793 #define CONFIG_SYS_UEC5_INTERFACE_TYPE PHY_INTERFACE_MODE_RMII 794 #define CONFIG_SYS_UEC5_INTERFACE_SPEED 100 795 #endif /* CONFIG_UEC_ETH5 */ 796 #endif /* CONFIG_P1025RDB */ 797 798 /* 799 * Environment 800 */ 801 #ifdef CONFIG_SPIFLASH 802 #define CONFIG_ENV_IS_IN_SPI_FLASH 803 #define CONFIG_ENV_SPI_BUS 0 804 #define CONFIG_ENV_SPI_CS 0 805 #define CONFIG_ENV_SPI_MAX_HZ 10000000 806 #define CONFIG_ENV_SPI_MODE 0 807 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */ 808 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ 809 #define CONFIG_ENV_SECT_SIZE 0x10000 810 #elif defined(CONFIG_SDCARD) 811 #define CONFIG_ENV_IS_IN_MMC 812 #define CONFIG_FSL_FIXED_MMC_LOCATION 813 #define CONFIG_ENV_SIZE 0x2000 814 #define CONFIG_SYS_MMC_ENV_DEV 0 815 #elif defined(CONFIG_NAND) 816 #ifdef CONFIG_TPL_BUILD 817 #define CONFIG_ENV_SIZE 0x2000 818 #define CONFIG_ENV_ADDR (CONFIG_SYS_INIT_L2_ADDR + (160 << 10)) 819 #else 820 #define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE 821 #endif 822 #define CONFIG_ENV_IS_IN_NAND 823 #define CONFIG_ENV_OFFSET (1024 * 1024) 824 #define CONFIG_ENV_RANGE (3 * CONFIG_ENV_SIZE) 825 #elif defined(CONFIG_SYS_RAMBOOT) 826 #define CONFIG_ENV_IS_NOWHERE /* Store ENV in memory only */ 827 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) 828 #define CONFIG_ENV_SIZE 0x2000 829 #else 830 #define CONFIG_ENV_IS_IN_FLASH 831 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) 832 #define CONFIG_ENV_SIZE 0x2000 833 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ 834 #endif 835 836 #define CONFIG_LOADS_ECHO /* echo on for serial download */ 837 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ 838 839 /* 840 * Command line configuration. 841 */ 842 #define CONFIG_CMD_IRQ 843 #define CONFIG_CMD_DATE 844 #define CONFIG_CMD_REGINFO 845 846 /* 847 * USB 848 */ 849 #define CONFIG_HAS_FSL_DR_USB 850 851 #if defined(CONFIG_HAS_FSL_DR_USB) 852 #define CONFIG_USB_EHCI 853 854 #ifdef CONFIG_USB_EHCI 855 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 856 #define CONFIG_USB_EHCI_FSL 857 #endif 858 #endif 859 860 #if defined(CONFIG_P1020RDB_PD) 861 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1 862 #endif 863 864 #define CONFIG_MMC 865 866 #ifdef CONFIG_MMC 867 #define CONFIG_FSL_ESDHC 868 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR 869 #define CONFIG_GENERIC_MMC 870 #endif 871 872 #if defined(CONFIG_MMC) || defined(CONFIG_USB_EHCI) \ 873 || defined(CONFIG_FSL_SATA) 874 #define CONFIG_DOS_PARTITION 875 #endif 876 877 #undef CONFIG_WATCHDOG /* watchdog disabled */ 878 879 /* 880 * Miscellaneous configurable options 881 */ 882 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 883 #define CONFIG_CMDLINE_EDITING /* Command-line editing */ 884 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 885 #if defined(CONFIG_CMD_KGDB) 886 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 887 #else 888 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 889 #endif 890 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) 891 /* Print Buffer Size */ 892 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 893 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */ 894 895 /* 896 * For booting Linux, the board info and command line data 897 * have to be in the first 64 MB of memory, since this is 898 * the maximum mapped by the Linux kernel during initialization. 899 */ 900 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory for Linux*/ 901 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 902 903 #if defined(CONFIG_CMD_KGDB) 904 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 905 #endif 906 907 /* 908 * Environment Configuration 909 */ 910 #define CONFIG_HOSTNAME unknown 911 #define CONFIG_ROOTPATH "/opt/nfsroot" 912 #define CONFIG_BOOTFILE "uImage" 913 #define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */ 914 915 /* default location for tftp and bootm */ 916 #define CONFIG_LOADADDR 1000000 917 918 #define CONFIG_BOOTARGS /* the boot command will set bootargs */ 919 920 #define CONFIG_BAUDRATE 115200 921 922 #ifdef __SW_BOOT_NOR 923 #define __NOR_RST_CMD \ 924 norboot=i2c dev 1; i2c mw 18 1 __SW_BOOT_NOR 1; \ 925 i2c mw 18 3 __SW_BOOT_MASK 1; reset 926 #endif 927 #ifdef __SW_BOOT_SPI 928 #define __SPI_RST_CMD \ 929 spiboot=i2c dev 1; i2c mw 18 1 __SW_BOOT_SPI 1; \ 930 i2c mw 18 3 __SW_BOOT_MASK 1; reset 931 #endif 932 #ifdef __SW_BOOT_SD 933 #define __SD_RST_CMD \ 934 sdboot=i2c dev 1; i2c mw 18 1 __SW_BOOT_SD 1; \ 935 i2c mw 18 3 __SW_BOOT_MASK 1; reset 936 #endif 937 #ifdef __SW_BOOT_NAND 938 #define __NAND_RST_CMD \ 939 nandboot=i2c dev 1; i2c mw 18 1 __SW_BOOT_NAND 1; \ 940 i2c mw 18 3 __SW_BOOT_MASK 1; reset 941 #endif 942 #ifdef __SW_BOOT_PCIE 943 #define __PCIE_RST_CMD \ 944 pciboot=i2c dev 1; i2c mw 18 1 __SW_BOOT_PCIE 1; \ 945 i2c mw 18 3 __SW_BOOT_MASK 1; reset 946 #endif 947 948 #define CONFIG_EXTRA_ENV_SETTINGS \ 949 "netdev=eth0\0" \ 950 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ 951 "loadaddr=1000000\0" \ 952 "bootfile=uImage\0" \ 953 "tftpflash=tftpboot $loadaddr $uboot; " \ 954 "protect off " __stringify(CONFIG_SYS_TEXT_BASE) " +$filesize; " \ 955 "erase " __stringify(CONFIG_SYS_TEXT_BASE) " +$filesize; " \ 956 "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) " $filesize; " \ 957 "protect on " __stringify(CONFIG_SYS_TEXT_BASE) " +$filesize; " \ 958 "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) " $filesize\0" \ 959 "hwconfig=usb1:dr_mode=host,phy_type=ulpi\0" \ 960 "consoledev=ttyS0\0" \ 961 "ramdiskaddr=2000000\0" \ 962 "ramdiskfile=rootfs.ext2.gz.uboot\0" \ 963 "fdtaddr=1e00000\0" \ 964 "bdev=sda1\0" \ 965 "jffs2nor=mtdblock3\0" \ 966 "norbootaddr=ef080000\0" \ 967 "norfdtaddr=ef040000\0" \ 968 "jffs2nand=mtdblock9\0" \ 969 "nandbootaddr=100000\0" \ 970 "nandfdtaddr=80000\0" \ 971 "ramdisk_size=120000\0" \ 972 "map_lowernorbank=i2c dev 1; i2c mw 18 1 02 1; i2c mw 18 3 fd 1\0" \ 973 "map_uppernorbank=i2c dev 1; i2c mw 18 1 00 1; i2c mw 18 3 fd 1\0" \ 974 __stringify(__NOR_RST_CMD)"\0" \ 975 __stringify(__SPI_RST_CMD)"\0" \ 976 __stringify(__SD_RST_CMD)"\0" \ 977 __stringify(__NAND_RST_CMD)"\0" \ 978 __stringify(__PCIE_RST_CMD)"\0" 979 980 #define CONFIG_NFSBOOTCOMMAND \ 981 "setenv bootargs root=/dev/nfs rw " \ 982 "nfsroot=$serverip:$rootpath " \ 983 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 984 "console=$consoledev,$baudrate $othbootargs;" \ 985 "tftp $loadaddr $bootfile;" \ 986 "tftp $fdtaddr $fdtfile;" \ 987 "bootm $loadaddr - $fdtaddr" 988 989 #define CONFIG_HDBOOT \ 990 "setenv bootargs root=/dev/$bdev rw rootdelay=30 " \ 991 "console=$consoledev,$baudrate $othbootargs;" \ 992 "usb start;" \ 993 "ext2load usb 0:1 $loadaddr /boot/$bootfile;" \ 994 "ext2load usb 0:1 $fdtaddr /boot/$fdtfile;" \ 995 "bootm $loadaddr - $fdtaddr" 996 997 #define CONFIG_USB_FAT_BOOT \ 998 "setenv bootargs root=/dev/ram rw " \ 999 "console=$consoledev,$baudrate $othbootargs " \ 1000 "ramdisk_size=$ramdisk_size;" \ 1001 "usb start;" \ 1002 "fatload usb 0:2 $loadaddr $bootfile;" \ 1003 "fatload usb 0:2 $fdtaddr $fdtfile;" \ 1004 "fatload usb 0:2 $ramdiskaddr $ramdiskfile;" \ 1005 "bootm $loadaddr $ramdiskaddr $fdtaddr" 1006 1007 #define CONFIG_USB_EXT2_BOOT \ 1008 "setenv bootargs root=/dev/ram rw " \ 1009 "console=$consoledev,$baudrate $othbootargs " \ 1010 "ramdisk_size=$ramdisk_size;" \ 1011 "usb start;" \ 1012 "ext2load usb 0:4 $loadaddr $bootfile;" \ 1013 "ext2load usb 0:4 $fdtaddr $fdtfile;" \ 1014 "ext2load usb 0:4 $ramdiskaddr $ramdiskfile;" \ 1015 "bootm $loadaddr $ramdiskaddr $fdtaddr" 1016 1017 #define CONFIG_NORBOOT \ 1018 "setenv bootargs root=/dev/$jffs2nor rw " \ 1019 "console=$consoledev,$baudrate rootfstype=jffs2 $othbootargs;" \ 1020 "bootm $norbootaddr - $norfdtaddr" 1021 1022 #define CONFIG_RAMBOOTCOMMAND \ 1023 "setenv bootargs root=/dev/ram rw " \ 1024 "console=$consoledev,$baudrate $othbootargs " \ 1025 "ramdisk_size=$ramdisk_size;" \ 1026 "tftp $ramdiskaddr $ramdiskfile;" \ 1027 "tftp $loadaddr $bootfile;" \ 1028 "tftp $fdtaddr $fdtfile;" \ 1029 "bootm $loadaddr $ramdiskaddr $fdtaddr" 1030 1031 #define CONFIG_BOOTCOMMAND CONFIG_HDBOOT 1032 1033 #endif /* __CONFIG_H */ 1034