1 /* 2 * Copyright 2010-2011 Freescale Semiconductor, Inc. 3 * 4 * See file CREDITS for list of people who contributed to this 5 * project. 6 * 7 * This program is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU General Public License as 9 * published by the Free Software Foundation; either version 2 of 10 * the License, or (at your option) any later version. 11 * 12 * This program is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 * 17 * You should have received a copy of the GNU General Public License 18 * along with this program; if not, write to the Free Software 19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 20 * MA 02111-1307 USA 21 */ 22 23 /* 24 * QorIQ RDB boards configuration file 25 */ 26 #ifndef __CONFIG_H 27 #define __CONFIG_H 28 29 #ifdef CONFIG_36BIT 30 #define CONFIG_PHYS_64BIT 31 #endif 32 33 #if defined(CONFIG_P1020MBG) 34 #define CONFIG_BOARDNAME "P1020MBG-PC" 35 #define CONFIG_P1020 36 #define CONFIG_VSC7385_ENET 37 #define CONFIG_SLIC 38 #define __SW_BOOT_MASK 0x03 39 #define __SW_BOOT_NOR 0xe4 40 #define __SW_BOOT_SD 0x54 41 #endif 42 43 #if defined(CONFIG_P1020UTM) 44 #define CONFIG_BOARDNAME "P1020UTM-PC" 45 #define CONFIG_P1020 46 #define __SW_BOOT_MASK 0x03 47 #define __SW_BOOT_NOR 0xe0 48 #define __SW_BOOT_SD 0x50 49 #endif 50 51 #if defined(CONFIG_P1020RDB) 52 #define CONFIG_BOARDNAME "P1020RDB-PC" 53 #define CONFIG_NAND_FSL_ELBC 54 #define CONFIG_P1020 55 #define CONFIG_SPI_FLASH 56 #define CONFIG_VSC7385_ENET 57 #define CONFIG_SLIC 58 #define __SW_BOOT_MASK 0x03 59 #define __SW_BOOT_NOR 0x5c 60 #define __SW_BOOT_SPI 0x1c 61 #define __SW_BOOT_SD 0x9c 62 #define __SW_BOOT_NAND 0xec 63 #define __SW_BOOT_PCIE 0x6c 64 #endif 65 66 #if defined(CONFIG_P1021RDB) 67 #define CONFIG_BOARDNAME "P1021RDB-PC" 68 #define CONFIG_NAND_FSL_ELBC 69 #define CONFIG_P1021 70 #define CONFIG_QE 71 #define CONFIG_SPI_FLASH 72 #define CONFIG_VSC7385_ENET 73 #define CONFIG_SYS_LBC_LBCR 0x00080000 /* Implement conversion of 74 addresses in the LBC */ 75 #define __SW_BOOT_MASK 0x03 76 #define __SW_BOOT_NOR 0x5c 77 #define __SW_BOOT_SPI 0x1c 78 #define __SW_BOOT_SD 0x9c 79 #define __SW_BOOT_NAND 0xec 80 #define __SW_BOOT_PCIE 0x6c 81 #endif 82 83 #if defined(CONFIG_P1024RDB) 84 #define CONFIG_BOARDNAME "P1024RDB" 85 #define CONFIG_NAND_FSL_ELBC 86 #define CONFIG_P1024 87 #define CONFIG_SLIC 88 #define CONFIG_SPI_FLASH 89 #define __SW_BOOT_MASK 0xf3 90 #define __SW_BOOT_NOR 0x00 91 #define __SW_BOOT_SPI 0x08 92 #define __SW_BOOT_SD 0x04 93 #define __SW_BOOT_NAND 0x0c 94 #endif 95 96 #if defined(CONFIG_P1025RDB) 97 #define CONFIG_BOARDNAME "P1025RDB" 98 #define CONFIG_NAND_FSL_ELBC 99 #define CONFIG_P1025 100 #define CONFIG_QE 101 #define CONFIG_SLIC 102 #define CONFIG_SPI_FLASH 103 104 #define CONFIG_SYS_LBC_LBCR 0x00080000 /* Implement conversion of 105 addresses in the LBC */ 106 #define __SW_BOOT_MASK 0xf3 107 #define __SW_BOOT_NOR 0x00 108 #define __SW_BOOT_SPI 0x08 109 #define __SW_BOOT_SD 0x04 110 #define __SW_BOOT_NAND 0x0c 111 #endif 112 113 #if defined(CONFIG_P2020RDB) 114 #define CONFIG_BOARDNAME "P2020RDB-PCA" 115 #define CONFIG_NAND_FSL_ELBC 116 #define CONFIG_P2020 117 #define CONFIG_SPI_FLASH 118 #define CONFIG_VSC7385_ENET 119 #define __SW_BOOT_MASK 0x03 120 #define __SW_BOOT_NOR 0xc8 121 #define __SW_BOOT_SPI 0x28 122 #define __SW_BOOT_SD 0x68 /* or 0x18 */ 123 #define __SW_BOOT_NAND 0xe8 124 #define __SW_BOOT_PCIE 0xa8 125 #endif 126 127 #ifdef CONFIG_SDCARD 128 #define CONFIG_RAMBOOT_SDCARD 129 #define CONFIG_SYS_RAMBOOT 130 #define CONFIG_SYS_EXTRA_ENV_RELOC 131 #define CONFIG_SYS_TEXT_BASE 0x11000000 132 #define CONFIG_RESET_VECTOR_ADDRESS 0x1107fffc 133 #endif 134 135 #ifdef CONFIG_SPIFLASH 136 #define CONFIG_RAMBOOT_SPIFLASH 137 #define CONFIG_SYS_RAMBOOT 138 #define CONFIG_SYS_EXTRA_ENV_RELOC 139 #define CONFIG_SYS_TEXT_BASE 0x11000000 140 #define CONFIG_RESET_VECTOR_ADDRESS 0x1107fffc 141 #endif 142 143 #ifdef CONFIG_NAND 144 #define CONFIG_SPL 145 #define CONFIG_SPL_INIT_MINIMAL 146 #define CONFIG_SPL_SERIAL_SUPPORT 147 #define CONFIG_SPL_NAND_SUPPORT 148 #define CONFIG_SPL_NAND_MINIMAL 149 #define CONFIG_SPL_FLUSH_IMAGE 150 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 151 152 #define CONFIG_SYS_TEXT_BASE 0x00201000 153 #define CONFIG_SPL_TEXT_BASE 0xfffff000 154 #define CONFIG_SPL_MAX_SIZE (4 * 1024) 155 #define CONFIG_SPL_RELOC_TEXT_BASE 0x00100000 156 #define CONFIG_SPL_RELOC_STACK 0x00100000 157 #define CONFIG_SYS_NAND_U_BOOT_SIZE ((512 << 10) + CONFIG_SPL_MAX_SIZE) 158 #define CONFIG_SYS_NAND_U_BOOT_DST (0x00200000 - CONFIG_SPL_MAX_SIZE) 159 #define CONFIG_SYS_NAND_U_BOOT_START 0x00200000 160 #define CONFIG_SYS_NAND_U_BOOT_OFFS 0 161 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds" 162 #endif 163 164 #ifndef CONFIG_SYS_TEXT_BASE 165 #define CONFIG_SYS_TEXT_BASE 0xeff80000 166 #endif 167 168 #ifndef CONFIG_RESET_VECTOR_ADDRESS 169 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc 170 #endif 171 172 #ifndef CONFIG_SYS_MONITOR_BASE 173 #ifdef CONFIG_SPL_BUILD 174 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE 175 #else 176 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 177 #endif 178 #endif 179 180 /* High Level Configuration Options */ 181 #define CONFIG_BOOKE 182 #define CONFIG_E500 183 #define CONFIG_MPC85xx 184 185 #define CONFIG_MP 186 187 #define CONFIG_FSL_ELBC 188 #define CONFIG_PCI 189 #define CONFIG_PCIE1 /* PCIE controler 1 (slot 1) */ 190 #define CONFIG_PCIE2 /* PCIE controler 2 (slot 2) */ 191 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ 192 #define CONFIG_FSL_PCIE_RESET /* need PCIe reset errata */ 193 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ 194 195 #define CONFIG_FSL_LAW 196 #define CONFIG_TSEC_ENET /* tsec ethernet support */ 197 #define CONFIG_ENV_OVERWRITE 198 199 #define CONFIG_CMD_SATA 200 #define CONFIG_SATA_SIL 201 #define CONFIG_SYS_SATA_MAX_DEVICE 2 202 #define CONFIG_LIBATA 203 #define CONFIG_LBA48 204 205 #if defined(CONFIG_P2020RDB) 206 #define CONFIG_SYS_CLK_FREQ 100000000 207 #else 208 #define CONFIG_SYS_CLK_FREQ 66666666 209 #endif 210 #define CONFIG_DDR_CLK_FREQ 66666666 211 212 #define CONFIG_HWCONFIG 213 /* 214 * These can be toggled for performance analysis, otherwise use default. 215 */ 216 #define CONFIG_L2_CACHE 217 #define CONFIG_BTB 218 219 #define CONFIG_BOARD_EARLY_INIT_F /* Call board_pre_init */ 220 221 #define CONFIG_ENABLE_36BIT_PHYS 222 223 #ifdef CONFIG_PHYS_64BIT 224 #define CONFIG_ADDR_MAP 1 225 #define CONFIG_SYS_NUM_ADDR_MAP 16 /* number of TLB1 entries */ 226 #endif 227 228 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ 229 #define CONFIG_SYS_MEMTEST_END 0x1fffffff 230 #define CONFIG_PANIC_HANG /* do not reset board on panic */ 231 232 #define CONFIG_SYS_CCSRBAR 0xffe00000 233 #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR 234 235 /* IN case of NAND bootloader relocate CCSRBAR in RAMboot code not in the 4k 236 SPL code*/ 237 #ifdef CONFIG_SPL_BUILD 238 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE 239 #endif 240 241 /* DDR Setup */ 242 #define CONFIG_FSL_DDR3 243 #define CONFIG_SYS_DDR_RAW_TIMING 244 #define CONFIG_DDR_SPD 245 #define CONFIG_SYS_SPD_BUS_NUM 1 246 #define SPD_EEPROM_ADDRESS 0x52 247 #undef CONFIG_FSL_DDR_INTERACTIVE 248 249 #ifdef CONFIG_P1020MBG 250 #define CONFIG_SYS_SDRAM_SIZE_LAW LAW_SIZE_2G 251 #define CONFIG_CHIP_SELECTS_PER_CTRL 2 252 #else 253 #define CONFIG_SYS_SDRAM_SIZE_LAW LAW_SIZE_1G 254 #define CONFIG_CHIP_SELECTS_PER_CTRL 1 255 #endif 256 #define CONFIG_SYS_SDRAM_SIZE (1u << (CONFIG_SYS_SDRAM_SIZE_LAW - 19)) 257 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 258 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 259 260 #define CONFIG_NUM_DDR_CONTROLLERS 1 261 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 262 263 /* Default settings for DDR3 */ 264 #ifdef CONFIG_P2020RDB 265 #define CONFIG_SYS_DDR_CS0_BNDS 0x0000003f 266 #define CONFIG_SYS_DDR_CS0_CONFIG 0x80014202 267 #define CONFIG_SYS_DDR_CS0_CONFIG_2 0x00000000 268 #define CONFIG_SYS_DDR_CS1_BNDS 0x00000000 269 #define CONFIG_SYS_DDR_CS1_CONFIG 0x00000000 270 #define CONFIG_SYS_DDR_CS1_CONFIG_2 0x00000000 271 272 #define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef 273 #define CONFIG_SYS_DDR_INIT_ADDR 0x00000000 274 #define CONFIG_SYS_DDR_INIT_EXT_ADDR 0x00000000 275 #define CONFIG_SYS_DDR_MODE_CONTROL 0x00000000 276 277 #define CONFIG_SYS_DDR_ZQ_CONTROL 0x89080600 278 #define CONFIG_SYS_DDR_WRLVL_CONTROL 0x8645F607 279 #define CONFIG_SYS_DDR_SR_CNTR 0x00000000 280 #define CONFIG_SYS_DDR_RCW_1 0x00000000 281 #define CONFIG_SYS_DDR_RCW_2 0x00000000 282 #define CONFIG_SYS_DDR_CONTROL 0xC7000000 /* Type = DDR3 */ 283 #define CONFIG_SYS_DDR_CONTROL_2 0x24401000 284 #define CONFIG_SYS_DDR_TIMING_4 0x00220001 285 #define CONFIG_SYS_DDR_TIMING_5 0x02401400 286 287 #define CONFIG_SYS_DDR_TIMING_3 0x00020000 288 #define CONFIG_SYS_DDR_TIMING_0 0x00330104 289 #define CONFIG_SYS_DDR_TIMING_1 0x6f6B4644 290 #define CONFIG_SYS_DDR_TIMING_2 0x0FA88CCF 291 #define CONFIG_SYS_DDR_CLK_CTRL 0x02000000 292 #define CONFIG_SYS_DDR_MODE_1 0x00421422 293 #define CONFIG_SYS_DDR_MODE_2 0x04000000 294 #define CONFIG_SYS_DDR_INTERVAL 0x0C300100 295 296 #else 297 #define CONFIG_SYS_DDR_CS0_BNDS 0x0000003f 298 #define CONFIG_SYS_DDR_CS0_CONFIG 0x80014302 299 #define CONFIG_SYS_DDR_CS0_CONFIG_2 0x00000000 300 #define CONFIG_SYS_DDR_CS1_BNDS 0x0040007f 301 #define CONFIG_SYS_DDR_CS1_CONFIG 0x80014302 302 #define CONFIG_SYS_DDR_CS1_CONFIG_2 0x00000000 303 304 #define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef 305 #define CONFIG_SYS_DDR_INIT_ADDR 0x00000000 306 #define CONFIG_SYS_DDR_INIT_EXT_ADDR 0x00000000 307 #define CONFIG_SYS_DDR_MODE_CONTROL 0x00000000 308 309 #define CONFIG_SYS_DDR_ZQ_CONTROL 0x89080600 310 #define CONFIG_SYS_DDR_WRLVL_CONTROL 0x8655A608 311 #define CONFIG_SYS_DDR_SR_CNTR 0x00000000 312 #define CONFIG_SYS_DDR_RCW_1 0x00000000 313 #define CONFIG_SYS_DDR_RCW_2 0x00000000 314 #define CONFIG_SYS_DDR_CONTROL 0xC70C0000 /* Type = DDR3 */ 315 #define CONFIG_SYS_DDR_CONTROL_2 0x04401050 316 #define CONFIG_SYS_DDR_TIMING_4 0x00220001 317 #define CONFIG_SYS_DDR_TIMING_5 0x03402400 318 319 #define CONFIG_SYS_DDR_TIMING_3 0x00020000 320 #define CONFIG_SYS_DDR_TIMING_0 0x00330004 321 #define CONFIG_SYS_DDR_TIMING_1 0x6f6B4846 322 #define CONFIG_SYS_DDR_TIMING_2 0x0FA8C8CF 323 #define CONFIG_SYS_DDR_CLK_CTRL 0x03000000 324 #define CONFIG_SYS_DDR_MODE_1 0x40461520 325 #define CONFIG_SYS_DDR_MODE_2 0x8000c000 326 #define CONFIG_SYS_DDR_INTERVAL 0x0C300000 327 #endif 328 329 #undef CONFIG_CLOCKS_IN_MHZ 330 331 /* 332 * Memory map 333 * 334 * 0x0000_0000 0x7fff_ffff DDR Up to 2GB cacheable 335 * 0x8000_0000 0xdfff_ffff PCI Express Mem 1.5G non-cacheable(PCIe * 3) 336 * 0xffc0_0000 0xffc3_ffff PCI IO range 256k non-cacheable 337 * 338 * Localbus cacheable (TBD) 339 * 0xXXXX_XXXX 0xXXXX_XXXX SRAM YZ M Cacheable 340 * 341 * Localbus non-cacheable 342 * 0xec00_0000 0xefff_ffff FLASH Up to 64M non-cacheable 343 * 0xff80_0000 0xff8f_ffff NAND flash 1M non-cacheable 344 * 0xff90_0000 0xff97_ffff L2 SDRAM(REV.) 512K cacheable(optional) 345 * 0xffa0_0000 0xffaf_ffff CPLD 1M non-cacheable 346 * 0xffb0_0000 0xffbf_ffff VSC7385 switch 1M non-cacheable 347 * 0xffd0_0000 0xffd0_3fff L1 for stack 16K Cacheable TLB0 348 * 0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable 349 */ 350 351 352 /* 353 * Local Bus Definitions 354 */ 355 #if defined(CONFIG_P1020MBG) 356 #define CONFIG_SYS_MAX_FLASH_SECT 512 /* 64M */ 357 #define CONFIG_SYS_FLASH_BASE 0xec000000 358 #elif defined(CONFIG_P1020UTM) 359 #define CONFIG_SYS_MAX_FLASH_SECT 256 /* 32M */ 360 #define CONFIG_SYS_FLASH_BASE 0xee000000 361 #else 362 #define CONFIG_SYS_MAX_FLASH_SECT 128 /* 16M */ 363 #define CONFIG_SYS_FLASH_BASE 0xef000000 364 #endif 365 366 367 #ifdef CONFIG_PHYS_64BIT 368 #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE) 369 #else 370 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE 371 #endif 372 373 #define CONFIG_FLASH_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) \ 374 | BR_PS_16 | BR_V) 375 376 #define CONFIG_FLASH_OR_PRELIM 0xfc000ff7 377 378 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS} 379 #define CONFIG_SYS_FLASH_QUIET_TEST 380 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 381 382 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ 383 384 #undef CONFIG_SYS_FLASH_CHECKSUM 385 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 386 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 387 388 #define CONFIG_FLASH_CFI_DRIVER 389 #define CONFIG_SYS_FLASH_CFI 390 #define CONFIG_SYS_FLASH_EMPTY_INFO 391 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 392 393 /* Nand Flash */ 394 #ifdef CONFIG_NAND_FSL_ELBC 395 #define CONFIG_SYS_NAND_BASE 0xff800000 396 #ifdef CONFIG_PHYS_64BIT 397 #define CONFIG_SYS_NAND_BASE_PHYS 0xfff800000ull 398 #else 399 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE 400 #endif 401 402 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } 403 #define CONFIG_SYS_MAX_NAND_DEVICE 1 404 #define CONFIG_MTD_NAND_VERIFY_WRITE 405 #define CONFIG_CMD_NAND 406 #define CONFIG_SYS_NAND_BLOCK_SIZE (16 * 1024) 407 408 #define CONFIG_SYS_NAND_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 409 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ 410 | BR_PS_8 /* Port Size = 8 bit */ \ 411 | BR_MS_FCM /* MSEL = FCM */ \ 412 | BR_V) /* valid */ 413 #define CONFIG_SYS_NAND_OR_PRELIM (OR_AM_32KB /* small page */ \ 414 | OR_FCM_CSCT \ 415 | OR_FCM_CST \ 416 | OR_FCM_CHT \ 417 | OR_FCM_SCY_1 \ 418 | OR_FCM_TRLX \ 419 | OR_FCM_EHTR) 420 #endif /* CONFIG_NAND_FSL_ELBC */ 421 422 #define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */ 423 424 #define CONFIG_SYS_INIT_RAM_LOCK 425 #define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* stack in RAM */ 426 #ifdef CONFIG_PHYS_64BIT 427 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf 428 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR 429 /* The assembler doesn't like typecast */ 430 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \ 431 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \ 432 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) 433 #else 434 /* Initial L1 address */ 435 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS CONFIG_SYS_INIT_RAM_ADDR 436 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0 437 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS 438 #endif 439 /* Size of used area in RAM */ 440 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 441 442 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ 443 GENERATED_GBL_DATA_SIZE) 444 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 445 446 #define CONFIG_SYS_MONITOR_LEN (256 * 1024)/* Reserve 256 kB for Mon */ 447 #define CONFIG_SYS_MALLOC_LEN (1024 * 1024)/* Reserved for malloc */ 448 449 #define CONFIG_SYS_CPLD_BASE 0xffa00000 450 #ifdef CONFIG_PHYS_64BIT 451 #define CONFIG_SYS_CPLD_BASE_PHYS 0xfffa00000ull 452 #else 453 #define CONFIG_SYS_CPLD_BASE_PHYS CONFIG_SYS_CPLD_BASE 454 #endif 455 /* CPLD config size: 1Mb */ 456 #define CONFIG_CPLD_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE_PHYS) | \ 457 BR_PS_8 | BR_V) 458 #define CONFIG_CPLD_OR_PRELIM (0xfff009f7) 459 460 #define CONFIG_SYS_PMC_BASE 0xff980000 461 #define CONFIG_SYS_PMC_BASE_PHYS CONFIG_SYS_PMC_BASE 462 #define CONFIG_PMC_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_PMC_BASE_PHYS) | \ 463 BR_PS_8 | BR_V) 464 #define CONFIG_PMC_OR_PRELIM (OR_AM_64KB | OR_GPCM_CSNT | OR_GPCM_XACS | \ 465 OR_GPCM_SCY | OR_GPCM_TRLX | OR_GPCM_EHTR | \ 466 OR_GPCM_EAD) 467 468 #ifdef CONFIG_NAND 469 #define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Addr */ 470 #define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */ 471 #define CONFIG_SYS_BR1_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */ 472 #define CONFIG_SYS_OR1_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */ 473 #else 474 #define CONFIG_SYS_BR0_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */ 475 #define CONFIG_SYS_OR0_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */ 476 #ifdef CONFIG_NAND_FSL_ELBC 477 #define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Addr */ 478 #define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */ 479 #endif 480 #endif 481 #define CONFIG_SYS_BR3_PRELIM CONFIG_CPLD_BR_PRELIM /* CPLD Base Address */ 482 #define CONFIG_SYS_OR3_PRELIM CONFIG_CPLD_OR_PRELIM /* CPLD Options */ 483 484 485 /* Vsc7385 switch */ 486 #ifdef CONFIG_VSC7385_ENET 487 #define CONFIG_SYS_VSC7385_BASE 0xffb00000 488 489 #ifdef CONFIG_PHYS_64BIT 490 #define CONFIG_SYS_VSC7385_BASE_PHYS 0xfffb00000ull 491 #else 492 #define CONFIG_SYS_VSC7385_BASE_PHYS CONFIG_SYS_VSC7385_BASE 493 #endif 494 495 #define CONFIG_SYS_VSC7385_BR_PRELIM \ 496 (BR_PHYS_ADDR(CONFIG_SYS_VSC7385_BASE_PHYS) | BR_PS_8 | BR_V) 497 #define CONFIG_SYS_VSC7385_OR_PRELIM (OR_AM_128KB | OR_GPCM_CSNT | \ 498 OR_GPCM_XACS | OR_GPCM_SCY_15 | OR_GPCM_SETA | \ 499 OR_GPCM_TRLX | OR_GPCM_EHTR | OR_GPCM_EAD) 500 501 #define CONFIG_SYS_BR2_PRELIM CONFIG_SYS_VSC7385_BR_PRELIM 502 #define CONFIG_SYS_OR2_PRELIM CONFIG_SYS_VSC7385_OR_PRELIM 503 504 /* The size of the VSC7385 firmware image */ 505 #define CONFIG_VSC7385_IMAGE_SIZE 8192 506 #endif 507 508 /* Serial Port - controlled on board with jumper J8 509 * open - index 2 510 * shorted - index 1 511 */ 512 #define CONFIG_CONS_INDEX 1 513 #undef CONFIG_SERIAL_SOFTWARE_FIFO 514 #define CONFIG_SYS_NS16550 515 #define CONFIG_SYS_NS16550_SERIAL 516 #define CONFIG_SYS_NS16550_REG_SIZE 1 517 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) 518 #ifdef CONFIG_SPL_BUILD 519 #define CONFIG_NS16550_MIN_FUNCTIONS 520 #endif 521 522 #define CONFIG_SYS_BAUDRATE_TABLE \ 523 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} 524 525 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) 526 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) 527 528 /* Use the HUSH parser */ 529 #define CONFIG_SYS_HUSH_PARSER 530 531 /* 532 * Pass open firmware flat tree 533 */ 534 #define CONFIG_OF_LIBFDT 535 #define CONFIG_OF_BOARD_SETUP 536 #define CONFIG_OF_STDOUT_VIA_ALIAS 537 538 /* new uImage format support */ 539 #define CONFIG_FIT 540 #define CONFIG_FIT_VERBOSE /* enable fit_format_{error,warning}() */ 541 542 /* I2C */ 543 #define CONFIG_FSL_I2C /* Use FSL common I2C driver */ 544 #define CONFIG_HARD_I2C /* I2C with hardware support */ 545 #undef CONFIG_SOFT_I2C /* I2C bit-banged */ 546 #define CONFIG_I2C_MULTI_BUS 547 #define CONFIG_I2C_CMD_TREE 548 #define CONFIG_SYS_I2C_SPEED 400000 /* I2C spd and slave address */ 549 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x52 550 #define CONFIG_SYS_I2C_SLAVE 0x7F 551 #define CONFIG_SYS_I2C_NOPROBES {{0, 0x29}} /* Don't probe this addr */ 552 #define CONFIG_SYS_I2C_OFFSET 0x3000 553 #define CONFIG_SYS_I2C2_OFFSET 0x3100 554 #define CONFIG_SYS_SPD_BUS_NUM 1 /* For rom_loc and flash bank */ 555 556 /* 557 * I2C2 EEPROM 558 */ 559 #undef CONFIG_ID_EEPROM 560 561 #define CONFIG_RTC_PT7C4338 562 #define CONFIG_SYS_I2C_RTC_ADDR 0x68 563 #define CONFIG_SYS_I2C_PCA9557_ADDR 0x18 564 565 /* enable read and write access to EEPROM */ 566 #define CONFIG_CMD_EEPROM 567 #define CONFIG_SYS_I2C_MULTI_EEPROMS 568 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 569 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 570 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 571 572 /* 573 * eSPI - Enhanced SPI 574 */ 575 #define CONFIG_HARD_SPI 576 #define CONFIG_FSL_ESPI 577 578 #if defined(CONFIG_SPI_FLASH) 579 #define CONFIG_SPI_FLASH_SPANSION 580 #define CONFIG_CMD_SF 581 #define CONFIG_SF_DEFAULT_SPEED 10000000 582 #define CONFIG_SF_DEFAULT_MODE 0 583 #endif 584 585 #if defined(CONFIG_PCI) 586 /* 587 * General PCI 588 * Memory space is mapped 1-1, but I/O space must start from 0. 589 */ 590 591 /* controller 2, direct to uli, tgtid 2, Base address 9000 */ 592 #define CONFIG_SYS_PCIE2_NAME "PCIe SLOT" 593 #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000 594 #ifdef CONFIG_PHYS_64BIT 595 #define CONFIG_SYS_PCIE2_MEM_BUS 0xc0000000 596 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull 597 #else 598 #define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000 599 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000 600 #endif 601 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */ 602 #define CONFIG_SYS_PCIE2_IO_VIRT 0xffc10000 603 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 604 #ifdef CONFIG_PHYS_64BIT 605 #define CONFIG_SYS_PCIE2_IO_PHYS 0xfffc10000ull 606 #else 607 #define CONFIG_SYS_PCIE2_IO_PHYS 0xffc10000 608 #endif 609 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ 610 611 /* controller 1, Slot 2, tgtid 1, Base address a000 */ 612 #define CONFIG_SYS_PCIE1_NAME "mini PCIe SLOT" 613 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 614 #ifdef CONFIG_PHYS_64BIT 615 #define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000 616 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull 617 #else 618 #define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000 619 #define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000 620 #endif 621 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ 622 #define CONFIG_SYS_PCIE1_IO_VIRT 0xffc00000 623 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 624 #ifdef CONFIG_PHYS_64BIT 625 #define CONFIG_SYS_PCIE1_IO_PHYS 0xfffc00000ull 626 #else 627 #define CONFIG_SYS_PCIE1_IO_PHYS 0xffc00000 628 #endif 629 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ 630 631 #define CONFIG_PCI_PNP /* do pci plug-and-play */ 632 #define CONFIG_E1000 /* Defind e1000 pci Ethernet card*/ 633 #define CONFIG_CMD_PCI 634 #define CONFIG_CMD_NET 635 636 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 637 #define CONFIG_DOS_PARTITION 638 #endif /* CONFIG_PCI */ 639 640 #if defined(CONFIG_TSEC_ENET) 641 #define CONFIG_MII /* MII PHY management */ 642 #define CONFIG_TSEC1 643 #define CONFIG_TSEC1_NAME "eTSEC1" 644 #define CONFIG_TSEC2 645 #define CONFIG_TSEC2_NAME "eTSEC2" 646 #define CONFIG_TSEC3 647 #define CONFIG_TSEC3_NAME "eTSEC3" 648 649 #define TSEC1_PHY_ADDR 2 650 #define TSEC2_PHY_ADDR 0 651 #define TSEC3_PHY_ADDR 1 652 653 #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 654 #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 655 #define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 656 657 #define TSEC1_PHYIDX 0 658 #define TSEC2_PHYIDX 0 659 #define TSEC3_PHYIDX 0 660 661 #define CONFIG_ETHPRIME "eTSEC1" 662 663 #define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */ 664 665 #define CONFIG_HAS_ETH0 666 #define CONFIG_HAS_ETH1 667 #define CONFIG_HAS_ETH2 668 #endif /* CONFIG_TSEC_ENET */ 669 670 #ifdef CONFIG_QE 671 /* QE microcode/firmware address */ 672 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR 673 #define CONFIG_SYS_QE_FMAN_FW_ADDR 0xefec0000 674 #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 675 #endif /* CONFIG_QE */ 676 677 #ifdef CONFIG_P1025RDB 678 /* 679 * QE UEC ethernet configuration 680 */ 681 #define CONFIG_MIIM_ADDRESS (CONFIG_SYS_CCSRBAR + 0x82120) 682 683 #undef CONFIG_UEC_ETH 684 #define CONFIG_PHY_MODE_NEED_CHANGE 685 686 #define CONFIG_UEC_ETH1 /* ETH1 */ 687 #define CONFIG_HAS_ETH0 688 689 #ifdef CONFIG_UEC_ETH1 690 #define CONFIG_SYS_UEC1_UCC_NUM 0 /* UCC1 */ 691 #define CONFIG_SYS_UEC1_RX_CLK QE_CLK12 /* CLK12 for MII */ 692 #define CONFIG_SYS_UEC1_TX_CLK QE_CLK9 /* CLK9 for MII */ 693 #define CONFIG_SYS_UEC1_ETH_TYPE FAST_ETH 694 #define CONFIG_SYS_UEC1_PHY_ADDR 0x0 /* 0x0 for MII */ 695 #define CONFIG_SYS_UEC1_INTERFACE_TYPE PHY_INTERFACE_MODE_RMII 696 #define CONFIG_SYS_UEC1_INTERFACE_SPEED 100 697 #endif /* CONFIG_UEC_ETH1 */ 698 699 #define CONFIG_UEC_ETH5 /* ETH5 */ 700 #define CONFIG_HAS_ETH1 701 702 #ifdef CONFIG_UEC_ETH5 703 #define CONFIG_SYS_UEC5_UCC_NUM 4 /* UCC5 */ 704 #define CONFIG_SYS_UEC5_RX_CLK QE_CLK_NONE 705 #define CONFIG_SYS_UEC5_TX_CLK QE_CLK13 /* CLK 13 for RMII */ 706 #define CONFIG_SYS_UEC5_ETH_TYPE FAST_ETH 707 #define CONFIG_SYS_UEC5_PHY_ADDR 0x3 /* 0x3 for RMII */ 708 #define CONFIG_SYS_UEC5_INTERFACE_TYPE PHY_INTERFACE_MODE_RMII 709 #define CONFIG_SYS_UEC5_INTERFACE_SPEED 100 710 #endif /* CONFIG_UEC_ETH5 */ 711 #endif /* CONFIG_P1025RDB */ 712 713 /* 714 * Environment 715 */ 716 #ifdef CONFIG_RAMBOOT_SPIFLASH 717 #define CONFIG_ENV_IS_IN_SPI_FLASH 718 #define CONFIG_ENV_SPI_BUS 0 719 #define CONFIG_ENV_SPI_CS 0 720 #define CONFIG_ENV_SPI_MAX_HZ 10000000 721 #define CONFIG_ENV_SPI_MODE 0 722 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */ 723 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ 724 #define CONFIG_ENV_SECT_SIZE 0x10000 725 #elif defined(CONFIG_RAMBOOT_SDCARD) 726 #define CONFIG_ENV_IS_IN_MMC 727 #define CONFIG_FSL_FIXED_MMC_LOCATION 728 #define CONFIG_ENV_SIZE 0x2000 729 #define CONFIG_SYS_MMC_ENV_DEV 0 730 #elif defined(CONFIG_NAND) 731 #define CONFIG_ENV_IS_IN_NAND 732 #define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE 733 #define CONFIG_ENV_OFFSET ((512 * 1024) + CONFIG_SYS_NAND_BLOCK_SIZE) 734 #define CONFIG_ENV_RANGE (3 * CONFIG_ENV_SIZE) 735 #elif defined(CONFIG_SYS_RAMBOOT) 736 #define CONFIG_ENV_IS_NOWHERE /* Store ENV in memory only */ 737 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) 738 #define CONFIG_ENV_SIZE 0x2000 739 #else 740 #define CONFIG_ENV_IS_IN_FLASH 741 #if CONFIG_SYS_MONITOR_BASE > 0xfff80000 742 #define CONFIG_ENV_ADDR 0xfff80000 743 #else 744 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) 745 #endif 746 #define CONFIG_ENV_SIZE 0x2000 747 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ 748 #endif 749 750 #define CONFIG_LOADS_ECHO /* echo on for serial download */ 751 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ 752 753 /* 754 * Command line configuration. 755 */ 756 #include <config_cmd_default.h> 757 758 #define CONFIG_CMD_IRQ 759 #define CONFIG_CMD_PING 760 #define CONFIG_CMD_I2C 761 #define CONFIG_CMD_MII 762 #define CONFIG_CMD_DATE 763 #define CONFIG_CMD_ELF 764 #define CONFIG_CMD_SETEXPR 765 #define CONFIG_CMD_REGINFO 766 767 /* 768 * USB 769 */ 770 #define CONFIG_HAS_FSL_DR_USB 771 772 #if defined(CONFIG_HAS_FSL_DR_USB) 773 #define CONFIG_USB_EHCI 774 775 #ifdef CONFIG_USB_EHCI 776 #define CONFIG_CMD_USB 777 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 778 #define CONFIG_USB_EHCI_FSL 779 #define CONFIG_USB_STORAGE 780 #endif 781 #endif 782 783 #define CONFIG_MMC 784 785 #ifdef CONFIG_MMC 786 #define CONFIG_FSL_ESDHC 787 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR 788 #define CONFIG_CMD_MMC 789 #define CONFIG_GENERIC_MMC 790 #endif 791 792 #if defined(CONFIG_MMC) || defined(CONFIG_USB_EHCI) \ 793 || defined(CONFIG_FSL_SATA) 794 #define CONFIG_CMD_EXT2 795 #define CONFIG_CMD_FAT 796 #define CONFIG_DOS_PARTITION 797 #endif 798 799 #undef CONFIG_WATCHDOG /* watchdog disabled */ 800 801 /* 802 * Miscellaneous configurable options 803 */ 804 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 805 #define CONFIG_CMDLINE_EDITING /* Command-line editing */ 806 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 807 #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ 808 #if defined(CONFIG_CMD_KGDB) 809 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 810 #else 811 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 812 #endif 813 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) 814 /* Print Buffer Size */ 815 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 816 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */ 817 #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms tick */ 818 819 /* 820 * For booting Linux, the board info and command line data 821 * have to be in the first 64 MB of memory, since this is 822 * the maximum mapped by the Linux kernel during initialization. 823 */ 824 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory for Linux*/ 825 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 826 827 #if defined(CONFIG_CMD_KGDB) 828 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 829 #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ 830 #endif 831 832 /* 833 * Environment Configuration 834 */ 835 #define CONFIG_HOSTNAME unknown 836 #define CONFIG_ROOTPATH "/opt/nfsroot" 837 #define CONFIG_BOOTFILE "uImage" 838 #define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */ 839 840 /* default location for tftp and bootm */ 841 #define CONFIG_LOADADDR 1000000 842 843 #define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */ 844 #define CONFIG_BOOTARGS /* the boot command will set bootargs */ 845 846 #define CONFIG_BAUDRATE 115200 847 848 #ifdef __SW_BOOT_NOR 849 #define __NOR_RST_CMD \ 850 norboot=i2c dev 1; i2c mw 18 1 __SW_BOOT_NOR 1; \ 851 i2c mw 18 3 __SW_BOOT_MASK 1; reset 852 #endif 853 #ifdef __SW_BOOT_SPI 854 #define __SPI_RST_CMD \ 855 spiboot=i2c dev 1; i2c mw 18 1 __SW_BOOT_SPI 1; \ 856 i2c mw 18 3 __SW_BOOT_MASK 1; reset 857 #endif 858 #ifdef __SW_BOOT_SD 859 #define __SD_RST_CMD \ 860 sdboot=i2c dev 1; i2c mw 18 1 __SW_BOOT_SD 1; \ 861 i2c mw 18 3 __SW_BOOT_MASK 1; reset 862 #endif 863 #ifdef __SW_BOOT_NAND 864 #define __NAND_RST_CMD \ 865 nandboot=i2c dev 1; i2c mw 18 1 __SW_BOOT_NAND 1; \ 866 i2c mw 18 3 __SW_BOOT_MASK 1; reset 867 #endif 868 #ifdef __SW_BOOT_PCIE 869 #define __PCIE_RST_CMD \ 870 pciboot=i2c dev 1; i2c mw 18 1 __SW_BOOT_PCIE 1; \ 871 i2c mw 18 3 __SW_BOOT_MASK 1; reset 872 #endif 873 874 #define CONFIG_EXTRA_ENV_SETTINGS \ 875 "netdev=eth0\0" \ 876 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ 877 "loadaddr=1000000\0" \ 878 "bootfile=uImage\0" \ 879 "tftpflash=tftpboot $loadaddr $uboot; " \ 880 "protect off " __stringify(CONFIG_SYS_TEXT_BASE) " +$filesize; " \ 881 "erase " __stringify(CONFIG_SYS_TEXT_BASE) " +$filesize; " \ 882 "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) " $filesize; " \ 883 "protect on " __stringify(CONFIG_SYS_TEXT_BASE) " +$filesize; " \ 884 "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) " $filesize\0" \ 885 "hwconfig=usb1:dr_mode=host,phy_type=ulpi\0" \ 886 "consoledev=ttyS0\0" \ 887 "ramdiskaddr=2000000\0" \ 888 "ramdiskfile=rootfs.ext2.gz.uboot\0" \ 889 "fdtaddr=c00000\0" \ 890 "bdev=sda1\0" \ 891 "jffs2nor=mtdblock3\0" \ 892 "norbootaddr=ef080000\0" \ 893 "norfdtaddr=ef040000\0" \ 894 "jffs2nand=mtdblock9\0" \ 895 "nandbootaddr=100000\0" \ 896 "nandfdtaddr=80000\0" \ 897 "ramdisk_size=120000\0" \ 898 "map_lowernorbank=i2c dev 1; i2c mw 18 1 02 1; i2c mw 18 3 fd 1\0" \ 899 "map_uppernorbank=i2c dev 1; i2c mw 18 1 00 1; i2c mw 18 3 fd 1\0" \ 900 __stringify(__NOR_RST_CMD)"\0" \ 901 __stringify(__SPI_RST_CMD)"\0" \ 902 __stringify(__SD_RST_CMD)"\0" \ 903 __stringify(__NAND_RST_CMD)"\0" \ 904 __stringify(__PCIE_RST_CMD)"\0" 905 906 #define CONFIG_NFSBOOTCOMMAND \ 907 "setenv bootargs root=/dev/nfs rw " \ 908 "nfsroot=$serverip:$rootpath " \ 909 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 910 "console=$consoledev,$baudrate $othbootargs;" \ 911 "tftp $loadaddr $bootfile;" \ 912 "tftp $fdtaddr $fdtfile;" \ 913 "bootm $loadaddr - $fdtaddr" 914 915 #define CONFIG_HDBOOT \ 916 "setenv bootargs root=/dev/$bdev rw rootdelay=30 " \ 917 "console=$consoledev,$baudrate $othbootargs;" \ 918 "usb start;" \ 919 "ext2load usb 0:1 $loadaddr /boot/$bootfile;" \ 920 "ext2load usb 0:1 $fdtaddr /boot/$fdtfile;" \ 921 "bootm $loadaddr - $fdtaddr" 922 923 #define CONFIG_USB_FAT_BOOT \ 924 "setenv bootargs root=/dev/ram rw " \ 925 "console=$consoledev,$baudrate $othbootargs " \ 926 "ramdisk_size=$ramdisk_size;" \ 927 "usb start;" \ 928 "fatload usb 0:2 $loadaddr $bootfile;" \ 929 "fatload usb 0:2 $fdtaddr $fdtfile;" \ 930 "fatload usb 0:2 $ramdiskaddr $ramdiskfile;" \ 931 "bootm $loadaddr $ramdiskaddr $fdtaddr" 932 933 #define CONFIG_USB_EXT2_BOOT \ 934 "setenv bootargs root=/dev/ram rw " \ 935 "console=$consoledev,$baudrate $othbootargs " \ 936 "ramdisk_size=$ramdisk_size;" \ 937 "usb start;" \ 938 "ext2load usb 0:4 $loadaddr $bootfile;" \ 939 "ext2load usb 0:4 $fdtaddr $fdtfile;" \ 940 "ext2load usb 0:4 $ramdiskaddr $ramdiskfile;" \ 941 "bootm $loadaddr $ramdiskaddr $fdtaddr" 942 943 #define CONFIG_NORBOOT \ 944 "setenv bootargs root=/dev/$jffs2nor rw " \ 945 "console=$consoledev,$baudrate rootfstype=jffs2 $othbootargs;" \ 946 "bootm $norbootaddr - $norfdtaddr" 947 948 #define CONFIG_RAMBOOTCOMMAND \ 949 "setenv bootargs root=/dev/ram rw " \ 950 "console=$consoledev,$baudrate $othbootargs " \ 951 "ramdisk_size=$ramdisk_size;" \ 952 "tftp $ramdiskaddr $ramdiskfile;" \ 953 "tftp $loadaddr $bootfile;" \ 954 "tftp $fdtaddr $fdtfile;" \ 955 "bootm $loadaddr $ramdiskaddr $fdtaddr" 956 957 #define CONFIG_BOOTCOMMAND CONFIG_HDBOOT 958 959 #endif /* __CONFIG_H */ 960