1 /* 2 * Copyright 2010-2011 Freescale Semiconductor, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 /* 8 * QorIQ RDB boards configuration file 9 */ 10 #ifndef __CONFIG_H 11 #define __CONFIG_H 12 13 #if defined(CONFIG_TARGET_P1020MBG) 14 #define CONFIG_BOARDNAME "P1020MBG-PC" 15 #define CONFIG_VSC7385_ENET 16 #define CONFIG_SLIC 17 #define __SW_BOOT_MASK 0x03 18 #define __SW_BOOT_NOR 0xe4 19 #define __SW_BOOT_SD 0x54 20 #define CONFIG_SYS_L2_SIZE (256 << 10) 21 #endif 22 23 #if defined(CONFIG_TARGET_P1020UTM) 24 #define CONFIG_BOARDNAME "P1020UTM-PC" 25 #define __SW_BOOT_MASK 0x03 26 #define __SW_BOOT_NOR 0xe0 27 #define __SW_BOOT_SD 0x50 28 #define CONFIG_SYS_L2_SIZE (256 << 10) 29 #endif 30 31 #if defined(CONFIG_TARGET_P1020RDB_PC) 32 #define CONFIG_BOARDNAME "P1020RDB-PC" 33 #define CONFIG_NAND_FSL_ELBC 34 #define CONFIG_VSC7385_ENET 35 #define CONFIG_SLIC 36 #define __SW_BOOT_MASK 0x03 37 #define __SW_BOOT_NOR 0x5c 38 #define __SW_BOOT_SPI 0x1c 39 #define __SW_BOOT_SD 0x9c 40 #define __SW_BOOT_NAND 0xec 41 #define __SW_BOOT_PCIE 0x6c 42 #define CONFIG_SYS_L2_SIZE (256 << 10) 43 #endif 44 45 /* 46 * P1020RDB-PD board has user selectable switches for evaluating different 47 * frequency and boot options for the P1020 device. The table that 48 * follow describe the available options. The front six binary number was in 49 * accordance with SW3[1:6]. 50 * 111101 533 533 267 667 NOR Core0 boot; Core1 hold-off 51 * 101101 667 667 333 667 NOR Core0 boot; Core1 hold-off 52 * 011001 800 800 400 667 NOR Core0 boot; Core1 hold-off 53 * 001001 800 800 400 667 SD/MMC Core0 boot; Core1 hold-off 54 * 001101 800 800 400 667 SPI Core0 boot; Core1 hold-off 55 * 010001 800 800 400 667 NAND Core0 boot; Core1 hold-off 56 * 011101 800 800 400 667 PCIe-2 Core0 boot; Core1 hold-off 57 */ 58 #if defined(CONFIG_TARGET_P1020RDB_PD) 59 #define CONFIG_BOARDNAME "P1020RDB-PD" 60 #define CONFIG_NAND_FSL_ELBC 61 #define CONFIG_VSC7385_ENET 62 #define CONFIG_SLIC 63 #define __SW_BOOT_MASK 0x03 64 #define __SW_BOOT_NOR 0x64 65 #define __SW_BOOT_SPI 0x34 66 #define __SW_BOOT_SD 0x24 67 #define __SW_BOOT_NAND 0x44 68 #define __SW_BOOT_PCIE 0x74 69 #define CONFIG_SYS_L2_SIZE (256 << 10) 70 /* 71 * Dynamic MTD Partition support with mtdparts 72 */ 73 #define CONFIG_MTD_DEVICE 74 #define CONFIG_MTD_PARTITIONS 75 #define CONFIG_FLASH_CFI_MTD 76 #endif 77 78 #if defined(CONFIG_TARGET_P1021RDB) 79 #define CONFIG_BOARDNAME "P1021RDB-PC" 80 #define CONFIG_NAND_FSL_ELBC 81 #define CONFIG_QE 82 #define CONFIG_VSC7385_ENET 83 #define CONFIG_SYS_LBC_LBCR 0x00080000 /* Implement conversion of 84 addresses in the LBC */ 85 #define __SW_BOOT_MASK 0x03 86 #define __SW_BOOT_NOR 0x5c 87 #define __SW_BOOT_SPI 0x1c 88 #define __SW_BOOT_SD 0x9c 89 #define __SW_BOOT_NAND 0xec 90 #define __SW_BOOT_PCIE 0x6c 91 #define CONFIG_SYS_L2_SIZE (256 << 10) 92 /* 93 * Dynamic MTD Partition support with mtdparts 94 */ 95 #define CONFIG_MTD_DEVICE 96 #define CONFIG_MTD_PARTITIONS 97 #define CONFIG_FLASH_CFI_MTD 98 #endif 99 100 #if defined(CONFIG_TARGET_P1024RDB) 101 #define CONFIG_BOARDNAME "P1024RDB" 102 #define CONFIG_NAND_FSL_ELBC 103 #define CONFIG_SLIC 104 #define __SW_BOOT_MASK 0xf3 105 #define __SW_BOOT_NOR 0x00 106 #define __SW_BOOT_SPI 0x08 107 #define __SW_BOOT_SD 0x04 108 #define __SW_BOOT_NAND 0x0c 109 #define CONFIG_SYS_L2_SIZE (256 << 10) 110 #endif 111 112 #if defined(CONFIG_TARGET_P1025RDB) 113 #define CONFIG_BOARDNAME "P1025RDB" 114 #define CONFIG_NAND_FSL_ELBC 115 #define CONFIG_QE 116 #define CONFIG_SLIC 117 118 #define CONFIG_SYS_LBC_LBCR 0x00080000 /* Implement conversion of 119 addresses in the LBC */ 120 #define __SW_BOOT_MASK 0xf3 121 #define __SW_BOOT_NOR 0x00 122 #define __SW_BOOT_SPI 0x08 123 #define __SW_BOOT_SD 0x04 124 #define __SW_BOOT_NAND 0x0c 125 #define CONFIG_SYS_L2_SIZE (256 << 10) 126 #endif 127 128 #if defined(CONFIG_TARGET_P2020RDB) 129 #define CONFIG_BOARDNAME "P2020RDB-PC" 130 #define CONFIG_NAND_FSL_ELBC 131 #define CONFIG_VSC7385_ENET 132 #define __SW_BOOT_MASK 0x03 133 #define __SW_BOOT_NOR 0xc8 134 #define __SW_BOOT_SPI 0x28 135 #define __SW_BOOT_SD 0x68 /* or 0x18 */ 136 #define __SW_BOOT_NAND 0xe8 137 #define __SW_BOOT_PCIE 0xa8 138 #define CONFIG_SYS_L2_SIZE (512 << 10) 139 /* 140 * Dynamic MTD Partition support with mtdparts 141 */ 142 #define CONFIG_MTD_DEVICE 143 #define CONFIG_MTD_PARTITIONS 144 #define CONFIG_FLASH_CFI_MTD 145 #endif 146 147 #ifdef CONFIG_SDCARD 148 #define CONFIG_SPL_FLUSH_IMAGE 149 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 150 #define CONFIG_SPL_TEXT_BASE 0xf8f81000 151 #define CONFIG_SPL_PAD_TO 0x20000 152 #define CONFIG_SPL_MAX_SIZE (128 * 1024) 153 #define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10) 154 #define CONFIG_SYS_MMC_U_BOOT_DST (0x11000000) 155 #define CONFIG_SYS_MMC_U_BOOT_START (0x11000000) 156 #define CONFIG_SYS_MMC_U_BOOT_OFFS (128 << 10) 157 #define CONFIG_SYS_MPC85XX_NO_RESETVEC 158 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds" 159 #define CONFIG_SPL_MMC_BOOT 160 #ifdef CONFIG_SPL_BUILD 161 #define CONFIG_SPL_COMMON_INIT_DDR 162 #endif 163 #endif 164 165 #ifdef CONFIG_SPIFLASH 166 #define CONFIG_SPL_SPI_FLASH_MINIMAL 167 #define CONFIG_SPL_FLUSH_IMAGE 168 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 169 #define CONFIG_SPL_TEXT_BASE 0xf8f81000 170 #define CONFIG_SPL_PAD_TO 0x20000 171 #define CONFIG_SPL_MAX_SIZE (128 * 1024) 172 #define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (768 << 10) 173 #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x11000000) 174 #define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x11000000) 175 #define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (128 << 10) 176 #define CONFIG_SYS_MPC85XX_NO_RESETVEC 177 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds" 178 #define CONFIG_SPL_SPI_BOOT 179 #ifdef CONFIG_SPL_BUILD 180 #define CONFIG_SPL_COMMON_INIT_DDR 181 #endif 182 #endif 183 184 #ifdef CONFIG_NAND 185 #ifdef CONFIG_TPL_BUILD 186 #define CONFIG_SPL_NAND_BOOT 187 #define CONFIG_SPL_FLUSH_IMAGE 188 #define CONFIG_SPL_NAND_INIT 189 #define CONFIG_SPL_COMMON_INIT_DDR 190 #define CONFIG_SPL_MAX_SIZE (128 << 10) 191 #define CONFIG_SPL_TEXT_BASE 0xf8f81000 192 #define CONFIG_SYS_MPC85XX_NO_RESETVEC 193 #define CONFIG_SYS_NAND_U_BOOT_SIZE (832 << 10) 194 #define CONFIG_SYS_NAND_U_BOOT_DST (0x11000000) 195 #define CONFIG_SYS_NAND_U_BOOT_START (0x11000000) 196 #define CONFIG_SYS_NAND_U_BOOT_OFFS ((128 + 128) << 10) 197 #elif defined(CONFIG_SPL_BUILD) 198 #define CONFIG_SPL_INIT_MINIMAL 199 #define CONFIG_SPL_FLUSH_IMAGE 200 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 201 #define CONFIG_SPL_TEXT_BASE 0xff800000 202 #define CONFIG_SPL_MAX_SIZE 4096 203 #define CONFIG_SYS_NAND_U_BOOT_SIZE (128 << 10) 204 #define CONFIG_SYS_NAND_U_BOOT_DST 0xf8f80000 205 #define CONFIG_SYS_NAND_U_BOOT_START 0xf8f80000 206 #define CONFIG_SYS_NAND_U_BOOT_OFFS (128 << 10) 207 #endif /* not CONFIG_TPL_BUILD */ 208 209 #define CONFIG_SPL_PAD_TO 0x20000 210 #define CONFIG_TPL_PAD_TO 0x20000 211 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 212 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds" 213 #endif 214 215 #ifndef CONFIG_RESET_VECTOR_ADDRESS 216 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc 217 #endif 218 219 #ifndef CONFIG_SYS_MONITOR_BASE 220 #ifdef CONFIG_SPL_BUILD 221 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE 222 #else 223 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 224 #endif 225 #endif 226 227 #define CONFIG_MP 228 229 #define CONFIG_PCIE1 /* PCIE controller 1 (slot 1) */ 230 #define CONFIG_PCIE2 /* PCIE controller 2 (slot 2) */ 231 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ 232 #define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */ 233 #define CONFIG_FSL_PCIE_RESET /* need PCIe reset errata */ 234 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ 235 236 #define CONFIG_TSEC_ENET /* tsec ethernet support */ 237 #define CONFIG_ENV_OVERWRITE 238 239 #define CONFIG_SYS_SATA_MAX_DEVICE 2 240 #define CONFIG_LBA48 241 242 #if defined(CONFIG_TARGET_P2020RDB) 243 #define CONFIG_SYS_CLK_FREQ 100000000 244 #else 245 #define CONFIG_SYS_CLK_FREQ 66666666 246 #endif 247 #define CONFIG_DDR_CLK_FREQ 66666666 248 249 #define CONFIG_HWCONFIG 250 /* 251 * These can be toggled for performance analysis, otherwise use default. 252 */ 253 #define CONFIG_L2_CACHE 254 #define CONFIG_BTB 255 256 #define CONFIG_ENABLE_36BIT_PHYS 257 258 #ifdef CONFIG_PHYS_64BIT 259 #define CONFIG_ADDR_MAP 1 260 #define CONFIG_SYS_NUM_ADDR_MAP 16 /* number of TLB1 entries */ 261 #endif 262 263 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ 264 #define CONFIG_SYS_MEMTEST_END 0x1fffffff 265 266 #define CONFIG_SYS_CCSRBAR 0xffe00000 267 #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR 268 269 /* IN case of NAND bootloader relocate CCSRBAR in RAMboot code not in the 4k 270 SPL code*/ 271 #ifdef CONFIG_SPL_BUILD 272 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE 273 #endif 274 275 /* DDR Setup */ 276 #define CONFIG_SYS_DDR_RAW_TIMING 277 #define CONFIG_DDR_SPD 278 #define CONFIG_SYS_SPD_BUS_NUM 1 279 #define SPD_EEPROM_ADDRESS 0x52 280 #undef CONFIG_FSL_DDR_INTERACTIVE 281 282 #if (defined(CONFIG_TARGET_P1020MBG) || defined(CONFIG_TARGET_P1020RDB_PD)) 283 #define CONFIG_SYS_SDRAM_SIZE_LAW LAW_SIZE_2G 284 #define CONFIG_CHIP_SELECTS_PER_CTRL 2 285 #else 286 #define CONFIG_SYS_SDRAM_SIZE_LAW LAW_SIZE_1G 287 #define CONFIG_CHIP_SELECTS_PER_CTRL 1 288 #endif 289 #define CONFIG_SYS_SDRAM_SIZE (1u << (CONFIG_SYS_SDRAM_SIZE_LAW - 19)) 290 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 291 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 292 293 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 294 295 /* Default settings for DDR3 */ 296 #ifndef CONFIG_TARGET_P2020RDB 297 #define CONFIG_SYS_DDR_CS0_BNDS 0x0000003f 298 #define CONFIG_SYS_DDR_CS0_CONFIG 0x80014302 299 #define CONFIG_SYS_DDR_CS0_CONFIG_2 0x00000000 300 #define CONFIG_SYS_DDR_CS1_BNDS 0x0040007f 301 #define CONFIG_SYS_DDR_CS1_CONFIG 0x80014302 302 #define CONFIG_SYS_DDR_CS1_CONFIG_2 0x00000000 303 304 #define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef 305 #define CONFIG_SYS_DDR_INIT_ADDR 0x00000000 306 #define CONFIG_SYS_DDR_INIT_EXT_ADDR 0x00000000 307 #define CONFIG_SYS_DDR_MODE_CONTROL 0x00000000 308 309 #define CONFIG_SYS_DDR_ZQ_CONTROL 0x89080600 310 #define CONFIG_SYS_DDR_WRLVL_CONTROL 0x8655A608 311 #define CONFIG_SYS_DDR_SR_CNTR 0x00000000 312 #define CONFIG_SYS_DDR_RCW_1 0x00000000 313 #define CONFIG_SYS_DDR_RCW_2 0x00000000 314 #define CONFIG_SYS_DDR_CONTROL 0xC70C0000 /* Type = DDR3 */ 315 #define CONFIG_SYS_DDR_CONTROL_2 0x04401050 316 #define CONFIG_SYS_DDR_TIMING_4 0x00220001 317 #define CONFIG_SYS_DDR_TIMING_5 0x03402400 318 319 #define CONFIG_SYS_DDR_TIMING_3 0x00020000 320 #define CONFIG_SYS_DDR_TIMING_0 0x00330004 321 #define CONFIG_SYS_DDR_TIMING_1 0x6f6B4846 322 #define CONFIG_SYS_DDR_TIMING_2 0x0FA8C8CF 323 #define CONFIG_SYS_DDR_CLK_CTRL 0x03000000 324 #define CONFIG_SYS_DDR_MODE_1 0x40461520 325 #define CONFIG_SYS_DDR_MODE_2 0x8000c000 326 #define CONFIG_SYS_DDR_INTERVAL 0x0C300000 327 #endif 328 329 #undef CONFIG_CLOCKS_IN_MHZ 330 331 /* 332 * Memory map 333 * 334 * 0x0000_0000 0x7fff_ffff DDR Up to 2GB cacheable 335 * 0x8000_0000 0xdfff_ffff PCI Express Mem 1.5G non-cacheable(PCIe * 3) 336 * 0xec00_0000 0xefff_ffff NOR flash Up to 64M non-cacheable CS0/1 337 * 0xf8f8_0000 0xf8ff_ffff L2 SRAM Up to 512K cacheable 338 * (early boot only) 339 * 0xff80_0000 0xff80_7fff NAND flash 32K non-cacheable CS1/0 340 * 0xff98_0000 0xff98_ffff PMC 64K non-cacheable CS2 341 * 0xffa0_0000 0xffaf_ffff CPLD 1M non-cacheable CS3 342 * 0xffb0_0000 0xffbf_ffff VSC7385 switch 1M non-cacheable CS2 343 * 0xffc0_0000 0xffc3_ffff PCI IO range 256k non-cacheable 344 * 0xffd0_0000 0xffd0_3fff L1 for stack 16K cacheable 345 * 0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable 346 */ 347 348 /* 349 * Local Bus Definitions 350 */ 351 #if (defined(CONFIG_TARGET_P1020MBG) || defined(CONFIG_TARGET_P1020RDB_PD)) 352 #define CONFIG_SYS_MAX_FLASH_SECT 512 /* 64M */ 353 #define CONFIG_SYS_FLASH_BASE 0xec000000 354 #elif defined(CONFIG_TARGET_P1020UTM) 355 #define CONFIG_SYS_MAX_FLASH_SECT 256 /* 32M */ 356 #define CONFIG_SYS_FLASH_BASE 0xee000000 357 #else 358 #define CONFIG_SYS_MAX_FLASH_SECT 128 /* 16M */ 359 #define CONFIG_SYS_FLASH_BASE 0xef000000 360 #endif 361 362 #ifdef CONFIG_PHYS_64BIT 363 #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE) 364 #else 365 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE 366 #endif 367 368 #define CONFIG_FLASH_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) \ 369 | BR_PS_16 | BR_V) 370 371 #define CONFIG_FLASH_OR_PRELIM 0xfc000ff7 372 373 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS} 374 #define CONFIG_SYS_FLASH_QUIET_TEST 375 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 376 377 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ 378 379 #undef CONFIG_SYS_FLASH_CHECKSUM 380 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 381 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 382 383 #define CONFIG_FLASH_CFI_DRIVER 384 #define CONFIG_SYS_FLASH_CFI 385 #define CONFIG_SYS_FLASH_EMPTY_INFO 386 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 387 388 /* Nand Flash */ 389 #ifdef CONFIG_NAND_FSL_ELBC 390 #define CONFIG_SYS_NAND_BASE 0xff800000 391 #ifdef CONFIG_PHYS_64BIT 392 #define CONFIG_SYS_NAND_BASE_PHYS 0xfff800000ull 393 #else 394 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE 395 #endif 396 397 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } 398 #define CONFIG_SYS_MAX_NAND_DEVICE 1 399 #if defined(CONFIG_TARGET_P1020RDB_PD) 400 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) 401 #else 402 #define CONFIG_SYS_NAND_BLOCK_SIZE (16 * 1024) 403 #endif 404 405 #define CONFIG_SYS_NAND_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 406 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ 407 | BR_PS_8 /* Port Size = 8 bit */ \ 408 | BR_MS_FCM /* MSEL = FCM */ \ 409 | BR_V) /* valid */ 410 #if defined(CONFIG_TARGET_P1020RDB_PD) 411 #define CONFIG_SYS_NAND_OR_PRELIM (OR_AM_32KB \ 412 | OR_FCM_PGS /* Large Page*/ \ 413 | OR_FCM_CSCT \ 414 | OR_FCM_CST \ 415 | OR_FCM_CHT \ 416 | OR_FCM_SCY_1 \ 417 | OR_FCM_TRLX \ 418 | OR_FCM_EHTR) 419 #else 420 #define CONFIG_SYS_NAND_OR_PRELIM (OR_AM_32KB /* small page */ \ 421 | OR_FCM_CSCT \ 422 | OR_FCM_CST \ 423 | OR_FCM_CHT \ 424 | OR_FCM_SCY_1 \ 425 | OR_FCM_TRLX \ 426 | OR_FCM_EHTR) 427 #endif 428 #endif /* CONFIG_NAND_FSL_ELBC */ 429 430 #define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */ 431 432 #define CONFIG_SYS_INIT_RAM_LOCK 433 #define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* stack in RAM */ 434 #ifdef CONFIG_PHYS_64BIT 435 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf 436 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR 437 /* The assembler doesn't like typecast */ 438 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \ 439 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \ 440 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) 441 #else 442 /* Initial L1 address */ 443 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS CONFIG_SYS_INIT_RAM_ADDR 444 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0 445 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS 446 #endif 447 /* Size of used area in RAM */ 448 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 449 450 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ 451 GENERATED_GBL_DATA_SIZE) 452 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 453 454 #define CONFIG_SYS_MONITOR_LEN (768 * 1024) 455 #define CONFIG_SYS_MALLOC_LEN (1024 * 1024)/* Reserved for malloc */ 456 457 #define CONFIG_SYS_CPLD_BASE 0xffa00000 458 #ifdef CONFIG_PHYS_64BIT 459 #define CONFIG_SYS_CPLD_BASE_PHYS 0xfffa00000ull 460 #else 461 #define CONFIG_SYS_CPLD_BASE_PHYS CONFIG_SYS_CPLD_BASE 462 #endif 463 /* CPLD config size: 1Mb */ 464 #define CONFIG_CPLD_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE_PHYS) | \ 465 BR_PS_8 | BR_V) 466 #define CONFIG_CPLD_OR_PRELIM (0xfff009f7) 467 468 #define CONFIG_SYS_PMC_BASE 0xff980000 469 #define CONFIG_SYS_PMC_BASE_PHYS CONFIG_SYS_PMC_BASE 470 #define CONFIG_PMC_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_PMC_BASE_PHYS) | \ 471 BR_PS_8 | BR_V) 472 #define CONFIG_PMC_OR_PRELIM (OR_AM_64KB | OR_GPCM_CSNT | OR_GPCM_XACS | \ 473 OR_GPCM_SCY | OR_GPCM_TRLX | OR_GPCM_EHTR | \ 474 OR_GPCM_EAD) 475 476 #ifdef CONFIG_NAND 477 #define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Addr */ 478 #define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */ 479 #define CONFIG_SYS_BR1_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */ 480 #define CONFIG_SYS_OR1_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */ 481 #else 482 #define CONFIG_SYS_BR0_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */ 483 #define CONFIG_SYS_OR0_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */ 484 #ifdef CONFIG_NAND_FSL_ELBC 485 #define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Addr */ 486 #define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */ 487 #endif 488 #endif 489 #define CONFIG_SYS_BR3_PRELIM CONFIG_CPLD_BR_PRELIM /* CPLD Base Address */ 490 #define CONFIG_SYS_OR3_PRELIM CONFIG_CPLD_OR_PRELIM /* CPLD Options */ 491 492 /* Vsc7385 switch */ 493 #ifdef CONFIG_VSC7385_ENET 494 #define CONFIG_SYS_VSC7385_BASE 0xffb00000 495 496 #ifdef CONFIG_PHYS_64BIT 497 #define CONFIG_SYS_VSC7385_BASE_PHYS 0xfffb00000ull 498 #else 499 #define CONFIG_SYS_VSC7385_BASE_PHYS CONFIG_SYS_VSC7385_BASE 500 #endif 501 502 #define CONFIG_SYS_VSC7385_BR_PRELIM \ 503 (BR_PHYS_ADDR(CONFIG_SYS_VSC7385_BASE_PHYS) | BR_PS_8 | BR_V) 504 #define CONFIG_SYS_VSC7385_OR_PRELIM (OR_AM_128KB | OR_GPCM_CSNT | \ 505 OR_GPCM_XACS | OR_GPCM_SCY_15 | OR_GPCM_SETA | \ 506 OR_GPCM_TRLX | OR_GPCM_EHTR | OR_GPCM_EAD) 507 508 #define CONFIG_SYS_BR2_PRELIM CONFIG_SYS_VSC7385_BR_PRELIM 509 #define CONFIG_SYS_OR2_PRELIM CONFIG_SYS_VSC7385_OR_PRELIM 510 511 /* The size of the VSC7385 firmware image */ 512 #define CONFIG_VSC7385_IMAGE_SIZE 8192 513 #endif 514 515 /* 516 * Config the L2 Cache as L2 SRAM 517 */ 518 #if defined(CONFIG_SPL_BUILD) 519 #if defined(CONFIG_SDCARD) || defined(CONFIG_SPIFLASH) 520 #define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000 521 #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR 522 #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) 523 #define CONFIG_SPL_RELOC_TEXT_BASE 0xf8f81000 524 #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L2_ADDR + 112 * 1024) 525 #define CONFIG_SPL_RELOC_STACK (CONFIG_SYS_INIT_L2_ADDR + 116 * 1024) 526 #define CONFIG_SPL_RELOC_STACK_SIZE (32 << 10) 527 #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SYS_INIT_L2_ADDR + 148 * 1024) 528 #if defined(CONFIG_TARGET_P2020RDB) 529 #define CONFIG_SPL_RELOC_MALLOC_SIZE (364 << 10) 530 #else 531 #define CONFIG_SPL_RELOC_MALLOC_SIZE (108 << 10) 532 #endif 533 #elif defined(CONFIG_NAND) 534 #ifdef CONFIG_TPL_BUILD 535 #define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000 536 #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR 537 #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) 538 #define CONFIG_SPL_RELOC_TEXT_BASE 0xf8f81000 539 #define CONFIG_SPL_RELOC_STACK (CONFIG_SYS_INIT_L2_ADDR + 192 * 1024) 540 #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SYS_INIT_L2_ADDR + 208 * 1024) 541 #define CONFIG_SPL_RELOC_MALLOC_SIZE (48 << 10) 542 #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L2_ADDR + 176 * 1024) 543 #else 544 #define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000 545 #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR 546 #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) 547 #define CONFIG_SPL_RELOC_TEXT_BASE (CONFIG_SYS_INIT_L2_END - 0x2000) 548 #define CONFIG_SPL_RELOC_STACK ((CONFIG_SYS_INIT_L2_END - 1) & ~0xF) 549 #endif /* CONFIG_TPL_BUILD */ 550 #endif 551 #endif 552 553 /* Serial Port - controlled on board with jumper J8 554 * open - index 2 555 * shorted - index 1 556 */ 557 #undef CONFIG_SERIAL_SOFTWARE_FIFO 558 #define CONFIG_SYS_NS16550_SERIAL 559 #define CONFIG_SYS_NS16550_REG_SIZE 1 560 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) 561 #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_INIT_MINIMAL) 562 #define CONFIG_NS16550_MIN_FUNCTIONS 563 #endif 564 565 #define CONFIG_SYS_BAUDRATE_TABLE \ 566 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} 567 568 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) 569 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) 570 571 /* I2C */ 572 #define CONFIG_SYS_I2C 573 #define CONFIG_SYS_I2C_FSL 574 #define CONFIG_SYS_FSL_I2C_SPEED 400000 575 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 576 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 577 #define CONFIG_SYS_FSL_I2C2_SPEED 400000 578 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F 579 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100 580 #define CONFIG_SYS_I2C_NOPROBES { {0, 0x29} } 581 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x52 582 #define CONFIG_SYS_SPD_BUS_NUM 1 /* For rom_loc and flash bank */ 583 584 /* 585 * I2C2 EEPROM 586 */ 587 #undef CONFIG_ID_EEPROM 588 589 #define CONFIG_RTC_PT7C4338 590 #define CONFIG_SYS_I2C_RTC_ADDR 0x68 591 #define CONFIG_SYS_I2C_PCA9557_ADDR 0x18 592 593 /* enable read and write access to EEPROM */ 594 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 595 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 596 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 597 598 /* 599 * eSPI - Enhanced SPI 600 */ 601 #define CONFIG_HARD_SPI 602 603 #if defined(CONFIG_SPI_FLASH) 604 #define CONFIG_SF_DEFAULT_SPEED 10000000 605 #define CONFIG_SF_DEFAULT_MODE 0 606 #endif 607 608 #if defined(CONFIG_PCI) 609 /* 610 * General PCI 611 * Memory space is mapped 1-1, but I/O space must start from 0. 612 */ 613 614 /* controller 2, direct to uli, tgtid 2, Base address 9000 */ 615 #define CONFIG_SYS_PCIE2_NAME "PCIe SLOT" 616 #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000 617 #ifdef CONFIG_PHYS_64BIT 618 #define CONFIG_SYS_PCIE2_MEM_BUS 0xc0000000 619 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull 620 #else 621 #define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000 622 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000 623 #endif 624 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */ 625 #define CONFIG_SYS_PCIE2_IO_VIRT 0xffc10000 626 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 627 #ifdef CONFIG_PHYS_64BIT 628 #define CONFIG_SYS_PCIE2_IO_PHYS 0xfffc10000ull 629 #else 630 #define CONFIG_SYS_PCIE2_IO_PHYS 0xffc10000 631 #endif 632 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ 633 634 /* controller 1, Slot 2, tgtid 1, Base address a000 */ 635 #define CONFIG_SYS_PCIE1_NAME "mini PCIe SLOT" 636 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 637 #ifdef CONFIG_PHYS_64BIT 638 #define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000 639 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull 640 #else 641 #define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000 642 #define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000 643 #endif 644 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ 645 #define CONFIG_SYS_PCIE1_IO_VIRT 0xffc00000 646 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 647 #ifdef CONFIG_PHYS_64BIT 648 #define CONFIG_SYS_PCIE1_IO_PHYS 0xfffc00000ull 649 #else 650 #define CONFIG_SYS_PCIE1_IO_PHYS 0xffc00000 651 #endif 652 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ 653 654 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 655 #endif /* CONFIG_PCI */ 656 657 #if defined(CONFIG_TSEC_ENET) 658 #define CONFIG_MII /* MII PHY management */ 659 #define CONFIG_TSEC1 660 #define CONFIG_TSEC1_NAME "eTSEC1" 661 #define CONFIG_TSEC2 662 #define CONFIG_TSEC2_NAME "eTSEC2" 663 #define CONFIG_TSEC3 664 #define CONFIG_TSEC3_NAME "eTSEC3" 665 666 #define TSEC1_PHY_ADDR 2 667 #define TSEC2_PHY_ADDR 0 668 #define TSEC3_PHY_ADDR 1 669 670 #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 671 #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 672 #define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 673 674 #define TSEC1_PHYIDX 0 675 #define TSEC2_PHYIDX 0 676 #define TSEC3_PHYIDX 0 677 678 #define CONFIG_ETHPRIME "eTSEC1" 679 680 #define CONFIG_HAS_ETH0 681 #define CONFIG_HAS_ETH1 682 #define CONFIG_HAS_ETH2 683 #endif /* CONFIG_TSEC_ENET */ 684 685 #ifdef CONFIG_QE 686 /* QE microcode/firmware address */ 687 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR 688 #define CONFIG_SYS_QE_FW_ADDR 0xefec0000 689 #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 690 #endif /* CONFIG_QE */ 691 692 #ifdef CONFIG_TARGET_P1025RDB 693 /* 694 * QE UEC ethernet configuration 695 */ 696 #define CONFIG_MIIM_ADDRESS (CONFIG_SYS_CCSRBAR + 0x82120) 697 698 #undef CONFIG_UEC_ETH 699 #define CONFIG_PHY_MODE_NEED_CHANGE 700 701 #define CONFIG_UEC_ETH1 /* ETH1 */ 702 #define CONFIG_HAS_ETH0 703 704 #ifdef CONFIG_UEC_ETH1 705 #define CONFIG_SYS_UEC1_UCC_NUM 0 /* UCC1 */ 706 #define CONFIG_SYS_UEC1_RX_CLK QE_CLK12 /* CLK12 for MII */ 707 #define CONFIG_SYS_UEC1_TX_CLK QE_CLK9 /* CLK9 for MII */ 708 #define CONFIG_SYS_UEC1_ETH_TYPE FAST_ETH 709 #define CONFIG_SYS_UEC1_PHY_ADDR 0x0 /* 0x0 for MII */ 710 #define CONFIG_SYS_UEC1_INTERFACE_TYPE PHY_INTERFACE_MODE_RMII 711 #define CONFIG_SYS_UEC1_INTERFACE_SPEED 100 712 #endif /* CONFIG_UEC_ETH1 */ 713 714 #define CONFIG_UEC_ETH5 /* ETH5 */ 715 #define CONFIG_HAS_ETH1 716 717 #ifdef CONFIG_UEC_ETH5 718 #define CONFIG_SYS_UEC5_UCC_NUM 4 /* UCC5 */ 719 #define CONFIG_SYS_UEC5_RX_CLK QE_CLK_NONE 720 #define CONFIG_SYS_UEC5_TX_CLK QE_CLK13 /* CLK 13 for RMII */ 721 #define CONFIG_SYS_UEC5_ETH_TYPE FAST_ETH 722 #define CONFIG_SYS_UEC5_PHY_ADDR 0x3 /* 0x3 for RMII */ 723 #define CONFIG_SYS_UEC5_INTERFACE_TYPE PHY_INTERFACE_MODE_RMII 724 #define CONFIG_SYS_UEC5_INTERFACE_SPEED 100 725 #endif /* CONFIG_UEC_ETH5 */ 726 #endif /* CONFIG_TARGET_P1025RDB */ 727 728 /* 729 * Environment 730 */ 731 #ifdef CONFIG_SPIFLASH 732 #define CONFIG_ENV_SPI_BUS 0 733 #define CONFIG_ENV_SPI_CS 0 734 #define CONFIG_ENV_SPI_MAX_HZ 10000000 735 #define CONFIG_ENV_SPI_MODE 0 736 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */ 737 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ 738 #define CONFIG_ENV_SECT_SIZE 0x10000 739 #elif defined(CONFIG_SDCARD) 740 #define CONFIG_FSL_FIXED_MMC_LOCATION 741 #define CONFIG_ENV_SIZE 0x2000 742 #define CONFIG_SYS_MMC_ENV_DEV 0 743 #elif defined(CONFIG_NAND) 744 #ifdef CONFIG_TPL_BUILD 745 #define CONFIG_ENV_SIZE 0x2000 746 #define CONFIG_ENV_ADDR (CONFIG_SYS_INIT_L2_ADDR + (160 << 10)) 747 #else 748 #define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE 749 #endif 750 #define CONFIG_ENV_OFFSET (1024 * 1024) 751 #define CONFIG_ENV_RANGE (3 * CONFIG_ENV_SIZE) 752 #elif defined(CONFIG_SYS_RAMBOOT) 753 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) 754 #define CONFIG_ENV_SIZE 0x2000 755 #else 756 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) 757 #define CONFIG_ENV_SIZE 0x2000 758 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ 759 #endif 760 761 #define CONFIG_LOADS_ECHO /* echo on for serial download */ 762 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ 763 764 /* 765 * USB 766 */ 767 #define CONFIG_HAS_FSL_DR_USB 768 769 #if defined(CONFIG_HAS_FSL_DR_USB) 770 #ifdef CONFIG_USB_EHCI_HCD 771 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 772 #define CONFIG_USB_EHCI_FSL 773 #define CONFIG_EHCI_DESC_BIG_ENDIAN 774 #endif 775 #endif 776 777 #if defined(CONFIG_TARGET_P1020RDB_PD) 778 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1 779 #endif 780 781 #ifdef CONFIG_MMC 782 #define CONFIG_FSL_ESDHC 783 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR 784 #endif 785 786 #undef CONFIG_WATCHDOG /* watchdog disabled */ 787 788 /* 789 * Miscellaneous configurable options 790 */ 791 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 792 793 /* 794 * For booting Linux, the board info and command line data 795 * have to be in the first 64 MB of memory, since this is 796 * the maximum mapped by the Linux kernel during initialization. 797 */ 798 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory for Linux*/ 799 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 800 801 #if defined(CONFIG_CMD_KGDB) 802 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 803 #endif 804 805 /* 806 * Environment Configuration 807 */ 808 #define CONFIG_HOSTNAME unknown 809 #define CONFIG_ROOTPATH "/opt/nfsroot" 810 #define CONFIG_BOOTFILE "uImage" 811 #define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */ 812 813 /* default location for tftp and bootm */ 814 #define CONFIG_LOADADDR 1000000 815 816 #ifdef __SW_BOOT_NOR 817 #define __NOR_RST_CMD \ 818 norboot=i2c dev 1; i2c mw 18 1 __SW_BOOT_NOR 1; \ 819 i2c mw 18 3 __SW_BOOT_MASK 1; reset 820 #endif 821 #ifdef __SW_BOOT_SPI 822 #define __SPI_RST_CMD \ 823 spiboot=i2c dev 1; i2c mw 18 1 __SW_BOOT_SPI 1; \ 824 i2c mw 18 3 __SW_BOOT_MASK 1; reset 825 #endif 826 #ifdef __SW_BOOT_SD 827 #define __SD_RST_CMD \ 828 sdboot=i2c dev 1; i2c mw 18 1 __SW_BOOT_SD 1; \ 829 i2c mw 18 3 __SW_BOOT_MASK 1; reset 830 #endif 831 #ifdef __SW_BOOT_NAND 832 #define __NAND_RST_CMD \ 833 nandboot=i2c dev 1; i2c mw 18 1 __SW_BOOT_NAND 1; \ 834 i2c mw 18 3 __SW_BOOT_MASK 1; reset 835 #endif 836 #ifdef __SW_BOOT_PCIE 837 #define __PCIE_RST_CMD \ 838 pciboot=i2c dev 1; i2c mw 18 1 __SW_BOOT_PCIE 1; \ 839 i2c mw 18 3 __SW_BOOT_MASK 1; reset 840 #endif 841 842 #define CONFIG_EXTRA_ENV_SETTINGS \ 843 "netdev=eth0\0" \ 844 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ 845 "loadaddr=1000000\0" \ 846 "bootfile=uImage\0" \ 847 "tftpflash=tftpboot $loadaddr $uboot; " \ 848 "protect off " __stringify(CONFIG_SYS_TEXT_BASE) " +$filesize; " \ 849 "erase " __stringify(CONFIG_SYS_TEXT_BASE) " +$filesize; " \ 850 "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) " $filesize; " \ 851 "protect on " __stringify(CONFIG_SYS_TEXT_BASE) " +$filesize; " \ 852 "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) " $filesize\0" \ 853 "hwconfig=usb1:dr_mode=host,phy_type=ulpi\0" \ 854 "consoledev=ttyS0\0" \ 855 "ramdiskaddr=2000000\0" \ 856 "ramdiskfile=rootfs.ext2.gz.uboot\0" \ 857 "fdtaddr=1e00000\0" \ 858 "bdev=sda1\0" \ 859 "jffs2nor=mtdblock3\0" \ 860 "norbootaddr=ef080000\0" \ 861 "norfdtaddr=ef040000\0" \ 862 "jffs2nand=mtdblock9\0" \ 863 "nandbootaddr=100000\0" \ 864 "nandfdtaddr=80000\0" \ 865 "ramdisk_size=120000\0" \ 866 "map_lowernorbank=i2c dev 1; i2c mw 18 1 02 1; i2c mw 18 3 fd 1\0" \ 867 "map_uppernorbank=i2c dev 1; i2c mw 18 1 00 1; i2c mw 18 3 fd 1\0" \ 868 __stringify(__NOR_RST_CMD)"\0" \ 869 __stringify(__SPI_RST_CMD)"\0" \ 870 __stringify(__SD_RST_CMD)"\0" \ 871 __stringify(__NAND_RST_CMD)"\0" \ 872 __stringify(__PCIE_RST_CMD)"\0" 873 874 #define CONFIG_NFSBOOTCOMMAND \ 875 "setenv bootargs root=/dev/nfs rw " \ 876 "nfsroot=$serverip:$rootpath " \ 877 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 878 "console=$consoledev,$baudrate $othbootargs;" \ 879 "tftp $loadaddr $bootfile;" \ 880 "tftp $fdtaddr $fdtfile;" \ 881 "bootm $loadaddr - $fdtaddr" 882 883 #define CONFIG_HDBOOT \ 884 "setenv bootargs root=/dev/$bdev rw rootdelay=30 " \ 885 "console=$consoledev,$baudrate $othbootargs;" \ 886 "usb start;" \ 887 "ext2load usb 0:1 $loadaddr /boot/$bootfile;" \ 888 "ext2load usb 0:1 $fdtaddr /boot/$fdtfile;" \ 889 "bootm $loadaddr - $fdtaddr" 890 891 #define CONFIG_USB_FAT_BOOT \ 892 "setenv bootargs root=/dev/ram rw " \ 893 "console=$consoledev,$baudrate $othbootargs " \ 894 "ramdisk_size=$ramdisk_size;" \ 895 "usb start;" \ 896 "fatload usb 0:2 $loadaddr $bootfile;" \ 897 "fatload usb 0:2 $fdtaddr $fdtfile;" \ 898 "fatload usb 0:2 $ramdiskaddr $ramdiskfile;" \ 899 "bootm $loadaddr $ramdiskaddr $fdtaddr" 900 901 #define CONFIG_USB_EXT2_BOOT \ 902 "setenv bootargs root=/dev/ram rw " \ 903 "console=$consoledev,$baudrate $othbootargs " \ 904 "ramdisk_size=$ramdisk_size;" \ 905 "usb start;" \ 906 "ext2load usb 0:4 $loadaddr $bootfile;" \ 907 "ext2load usb 0:4 $fdtaddr $fdtfile;" \ 908 "ext2load usb 0:4 $ramdiskaddr $ramdiskfile;" \ 909 "bootm $loadaddr $ramdiskaddr $fdtaddr" 910 911 #define CONFIG_NORBOOT \ 912 "setenv bootargs root=/dev/$jffs2nor rw " \ 913 "console=$consoledev,$baudrate rootfstype=jffs2 $othbootargs;" \ 914 "bootm $norbootaddr - $norfdtaddr" 915 916 #define CONFIG_RAMBOOTCOMMAND \ 917 "setenv bootargs root=/dev/ram rw " \ 918 "console=$consoledev,$baudrate $othbootargs " \ 919 "ramdisk_size=$ramdisk_size;" \ 920 "tftp $ramdiskaddr $ramdiskfile;" \ 921 "tftp $loadaddr $bootfile;" \ 922 "tftp $fdtaddr $fdtfile;" \ 923 "bootm $loadaddr $ramdiskaddr $fdtaddr" 924 925 #define CONFIG_BOOTCOMMAND CONFIG_HDBOOT 926 927 #endif /* __CONFIG_H */ 928