1 /*
2  * Copyright 2010-2011 Freescale Semiconductor, Inc.
3  *
4  * SPDX-License-Identifier:	GPL-2.0+
5  */
6 
7 /*
8  * QorIQ RDB boards configuration file
9  */
10 #ifndef __CONFIG_H
11 #define __CONFIG_H
12 
13 #define CONFIG_SYS_GENERIC_BOARD
14 #define CONFIG_DISPLAY_BOARDINFO
15 
16 #ifdef CONFIG_36BIT
17 #define CONFIG_PHYS_64BIT
18 #endif
19 
20 #if defined(CONFIG_P1020MBG)
21 #define CONFIG_BOARDNAME "P1020MBG-PC"
22 #define CONFIG_P1020
23 #define CONFIG_VSC7385_ENET
24 #define CONFIG_SLIC
25 #define __SW_BOOT_MASK		0x03
26 #define __SW_BOOT_NOR		0xe4
27 #define __SW_BOOT_SD		0x54
28 #define CONFIG_SYS_L2_SIZE	(256 << 10)
29 #endif
30 
31 #if defined(CONFIG_P1020UTM)
32 #define CONFIG_BOARDNAME "P1020UTM-PC"
33 #define CONFIG_P1020
34 #define __SW_BOOT_MASK		0x03
35 #define __SW_BOOT_NOR		0xe0
36 #define __SW_BOOT_SD		0x50
37 #define CONFIG_SYS_L2_SIZE	(256 << 10)
38 #endif
39 
40 #if defined(CONFIG_P1020RDB_PC)
41 #define CONFIG_BOARDNAME "P1020RDB-PC"
42 #define CONFIG_NAND_FSL_ELBC
43 #define CONFIG_P1020
44 #define CONFIG_VSC7385_ENET
45 #define CONFIG_SLIC
46 #define __SW_BOOT_MASK		0x03
47 #define __SW_BOOT_NOR		0x5c
48 #define __SW_BOOT_SPI		0x1c
49 #define __SW_BOOT_SD		0x9c
50 #define __SW_BOOT_NAND		0xec
51 #define __SW_BOOT_PCIE		0x6c
52 #define CONFIG_SYS_L2_SIZE	(256 << 10)
53 #endif
54 
55 /*
56  * P1020RDB-PD board has user selectable switches for evaluating different
57  * frequency and boot options for the P1020 device. The table that
58  * follow describe the available options. The front six binary number was in
59  * accordance with SW3[1:6].
60  * 111101 533 533 267 667 NOR Core0 boot; Core1 hold-off
61  * 101101 667 667 333 667 NOR Core0 boot; Core1 hold-off
62  * 011001 800 800 400 667 NOR Core0 boot; Core1 hold-off
63  * 001001 800 800 400 667 SD/MMC Core0 boot; Core1 hold-off
64  * 001101 800 800 400 667 SPI Core0 boot; Core1 hold-off
65  * 010001 800 800 400 667 NAND Core0 boot; Core1 hold-off
66  * 011101 800 800 400 667 PCIe-2 Core0 boot; Core1 hold-off
67  */
68 #if defined(CONFIG_P1020RDB_PD)
69 #define CONFIG_BOARDNAME "P1020RDB-PD"
70 #define CONFIG_NAND_FSL_ELBC
71 #define CONFIG_P1020
72 #define CONFIG_VSC7385_ENET
73 #define CONFIG_SLIC
74 #define __SW_BOOT_MASK		0x03
75 #define __SW_BOOT_NOR		0x64
76 #define __SW_BOOT_SPI		0x34
77 #define __SW_BOOT_SD		0x24
78 #define __SW_BOOT_NAND		0x44
79 #define __SW_BOOT_PCIE		0x74
80 #define CONFIG_SYS_L2_SIZE	(256 << 10)
81 /*
82  * Dynamic MTD Partition support with mtdparts
83  */
84 #define CONFIG_MTD_DEVICE
85 #define CONFIG_MTD_PARTITIONS
86 #define CONFIG_CMD_MTDPARTS
87 #define CONFIG_FLASH_CFI_MTD
88 #define MTDIDS_DEFAULT "nor0=ec000000.nor"
89 #define MTDPARTS_DEFAULT "mtdparts=ec000000.nor:128k(dtb),6016k(kernel)," \
90 			"57088k(fs),1m(vsc7385-firmware),1280k(u-boot)"
91 #endif
92 
93 #if defined(CONFIG_P1021RDB)
94 #define CONFIG_BOARDNAME "P1021RDB-PC"
95 #define CONFIG_NAND_FSL_ELBC
96 #define CONFIG_P1021
97 #define CONFIG_QE
98 #define CONFIG_VSC7385_ENET
99 #define CONFIG_SYS_LBC_LBCR	0x00080000	/* Implement conversion of
100 						addresses in the LBC */
101 #define __SW_BOOT_MASK		0x03
102 #define __SW_BOOT_NOR		0x5c
103 #define __SW_BOOT_SPI		0x1c
104 #define __SW_BOOT_SD		0x9c
105 #define __SW_BOOT_NAND		0xec
106 #define __SW_BOOT_PCIE		0x6c
107 #define CONFIG_SYS_L2_SIZE	(256 << 10)
108 /*
109  * Dynamic MTD Partition support with mtdparts
110  */
111 #define CONFIG_MTD_DEVICE
112 #define CONFIG_MTD_PARTITIONS
113 #define CONFIG_CMD_MTDPARTS
114 #define CONFIG_FLASH_CFI_MTD
115 #ifdef CONFIG_PHYS_64BIT
116 #define MTDIDS_DEFAULT "nor0=fef000000.nor"
117 #define MTDPARTS_DEFAULT "mtdparts=fef000000.nor:256k(vsc7385-firmware)," \
118 			"256k(dtb),4608k(kernel),9728k(fs)," \
119 			"256k(qe-ucode-firmware),1280k(u-boot)"
120 #else
121 #define MTDIDS_DEFAULT "nor0=ef000000.nor"
122 #define MTDPARTS_DEFAULT "mtdparts=ef000000.nor:256k(vsc7385-firmware)," \
123 			"256k(dtb),4608k(kernel),9728k(fs)," \
124 			"256k(qe-ucode-firmware),1280k(u-boot)"
125 #endif
126 #endif
127 
128 #if defined(CONFIG_P1024RDB)
129 #define CONFIG_BOARDNAME "P1024RDB"
130 #define CONFIG_NAND_FSL_ELBC
131 #define CONFIG_P1024
132 #define CONFIG_SLIC
133 #define __SW_BOOT_MASK		0xf3
134 #define __SW_BOOT_NOR		0x00
135 #define __SW_BOOT_SPI		0x08
136 #define __SW_BOOT_SD		0x04
137 #define __SW_BOOT_NAND		0x0c
138 #define CONFIG_SYS_L2_SIZE	(256 << 10)
139 #endif
140 
141 #if defined(CONFIG_P1025RDB)
142 #define CONFIG_BOARDNAME "P1025RDB"
143 #define CONFIG_NAND_FSL_ELBC
144 #define CONFIG_P1025
145 #define CONFIG_QE
146 #define CONFIG_SLIC
147 
148 #define CONFIG_SYS_LBC_LBCR	0x00080000	/* Implement conversion of
149 						addresses in the LBC */
150 #define __SW_BOOT_MASK		0xf3
151 #define __SW_BOOT_NOR		0x00
152 #define __SW_BOOT_SPI		0x08
153 #define __SW_BOOT_SD		0x04
154 #define __SW_BOOT_NAND		0x0c
155 #define CONFIG_SYS_L2_SIZE	(256 << 10)
156 #endif
157 
158 #if defined(CONFIG_P2020RDB)
159 #define CONFIG_BOARDNAME "P2020RDB-PCA"
160 #define CONFIG_NAND_FSL_ELBC
161 #define CONFIG_P2020
162 #define CONFIG_VSC7385_ENET
163 #define __SW_BOOT_MASK		0x03
164 #define __SW_BOOT_NOR		0xc8
165 #define __SW_BOOT_SPI		0x28
166 #define __SW_BOOT_SD		0x68 /* or 0x18 */
167 #define __SW_BOOT_NAND		0xe8
168 #define __SW_BOOT_PCIE		0xa8
169 #define CONFIG_SYS_L2_SIZE	(512 << 10)
170 /*
171  * Dynamic MTD Partition support with mtdparts
172  */
173 #define CONFIG_MTD_DEVICE
174 #define CONFIG_MTD_PARTITIONS
175 #define CONFIG_CMD_MTDPARTS
176 #define CONFIG_FLASH_CFI_MTD
177 #ifdef CONFIG_PHYS_64BIT
178 #define MTDIDS_DEFAULT "nor0=fef000000.nor"
179 #define MTDPARTS_DEFAULT "mtdparts=fef000000.nor:256k(vsc7385-firmware)," \
180 			"256k(dtb),4608k(kernel),9984k(fs),1280k(u-boot)"
181 #else
182 #define MTDIDS_DEFAULT "nor0=ef000000.nor"
183 #define MTDPARTS_DEFAULT "mtdparts=ef000000.nor:256k(vsc7385-firmware)," \
184 			"256k(dtb),4608k(kernel),9984k(fs),1280k(u-boot)"
185 #endif
186 #endif
187 
188 #ifdef CONFIG_SDCARD
189 #define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT
190 #define CONFIG_SPL_ENV_SUPPORT
191 #define CONFIG_SPL_SERIAL_SUPPORT
192 #define CONFIG_SPL_MMC_SUPPORT
193 #define CONFIG_SPL_MMC_MINIMAL
194 #define CONFIG_SPL_FLUSH_IMAGE
195 #define CONFIG_SPL_TARGET		"u-boot-with-spl.bin"
196 #define CONFIG_SPL_LIBGENERIC_SUPPORT
197 #define CONFIG_SPL_LIBCOMMON_SUPPORT
198 #define CONFIG_SPL_I2C_SUPPORT
199 #define CONFIG_FSL_LAW                 /* Use common FSL init code */
200 #define CONFIG_SYS_TEXT_BASE		0x11001000
201 #define CONFIG_SPL_TEXT_BASE		0xf8f81000
202 #define CONFIG_SPL_PAD_TO		0x20000
203 #define CONFIG_SPL_MAX_SIZE		(128 * 1024)
204 #define CONFIG_SYS_MMC_U_BOOT_SIZE	(768 << 10)
205 #define CONFIG_SYS_MMC_U_BOOT_DST	(0x11000000)
206 #define CONFIG_SYS_MMC_U_BOOT_START	(0x11000000)
207 #define CONFIG_SYS_MMC_U_BOOT_OFFS	(128 << 10)
208 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
209 #define CONFIG_SYS_LDSCRIPT	"arch/powerpc/cpu/mpc85xx/u-boot.lds"
210 #define CONFIG_SPL_MMC_BOOT
211 #ifdef CONFIG_SPL_BUILD
212 #define CONFIG_SPL_COMMON_INIT_DDR
213 #endif
214 #endif
215 
216 #ifdef CONFIG_SPIFLASH
217 #define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT
218 #define CONFIG_SPL_ENV_SUPPORT
219 #define CONFIG_SPL_SERIAL_SUPPORT
220 #define CONFIG_SPL_SPI_SUPPORT
221 #define CONFIG_SPL_SPI_FLASH_SUPPORT
222 #define CONFIG_SPL_SPI_FLASH_MINIMAL
223 #define CONFIG_SPL_FLUSH_IMAGE
224 #define CONFIG_SPL_TARGET		"u-boot-with-spl.bin"
225 #define CONFIG_SPL_LIBGENERIC_SUPPORT
226 #define CONFIG_SPL_LIBCOMMON_SUPPORT
227 #define CONFIG_SPL_I2C_SUPPORT
228 #define CONFIG_FSL_LAW         /* Use common FSL init code */
229 #define CONFIG_SYS_TEXT_BASE		0x11001000
230 #define CONFIG_SPL_TEXT_BASE		0xf8f81000
231 #define CONFIG_SPL_PAD_TO		0x20000
232 #define CONFIG_SPL_MAX_SIZE		(128 * 1024)
233 #define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE	(768 << 10)
234 #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST		(0x11000000)
235 #define CONFIG_SYS_SPI_FLASH_U_BOOT_START	(0x11000000)
236 #define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS	(128 << 10)
237 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
238 #define CONFIG_SYS_LDSCRIPT	"arch/powerpc/cpu/mpc85xx/u-boot.lds"
239 #define CONFIG_SPL_SPI_BOOT
240 #ifdef CONFIG_SPL_BUILD
241 #define CONFIG_SPL_COMMON_INIT_DDR
242 #endif
243 #endif
244 
245 #ifdef CONFIG_NAND
246 #ifdef CONFIG_TPL_BUILD
247 #define CONFIG_SPL_NAND_BOOT
248 #define CONFIG_SPL_FLUSH_IMAGE
249 #define CONFIG_SPL_ENV_SUPPORT
250 #define CONFIG_SPL_NAND_INIT
251 #define CONFIG_SPL_SERIAL_SUPPORT
252 #define CONFIG_SPL_LIBGENERIC_SUPPORT
253 #define CONFIG_SPL_LIBCOMMON_SUPPORT
254 #define CONFIG_SPL_I2C_SUPPORT
255 #define CONFIG_SPL_NAND_SUPPORT
256 #define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT
257 #define CONFIG_SPL_COMMON_INIT_DDR
258 #define CONFIG_SPL_MAX_SIZE		(128 << 10)
259 #define CONFIG_SPL_TEXT_BASE		0xf8f81000
260 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
261 #define CONFIG_SYS_NAND_U_BOOT_SIZE	(832 << 10)
262 #define CONFIG_SYS_NAND_U_BOOT_DST	(0x11000000)
263 #define CONFIG_SYS_NAND_U_BOOT_START	(0x11000000)
264 #define CONFIG_SYS_NAND_U_BOOT_OFFS	((128 + 128) << 10)
265 #elif defined(CONFIG_SPL_BUILD)
266 #define CONFIG_SPL_INIT_MINIMAL
267 #define CONFIG_SPL_SERIAL_SUPPORT
268 #define CONFIG_SPL_NAND_SUPPORT
269 #define CONFIG_SPL_FLUSH_IMAGE
270 #define CONFIG_SPL_TARGET		"u-boot-with-spl.bin"
271 #define CONFIG_SPL_TEXT_BASE		0xff800000
272 #define CONFIG_SPL_MAX_SIZE		4096
273 #define CONFIG_SYS_NAND_U_BOOT_SIZE	(128 << 10)
274 #define CONFIG_SYS_NAND_U_BOOT_DST	0xf8f80000
275 #define CONFIG_SYS_NAND_U_BOOT_START	0xf8f80000
276 #define CONFIG_SYS_NAND_U_BOOT_OFFS	(128 << 10)
277 #endif /* not CONFIG_TPL_BUILD */
278 
279 #define CONFIG_SPL_PAD_TO		0x20000
280 #define CONFIG_TPL_PAD_TO		0x20000
281 #define CONFIG_SPL_TARGET		"u-boot-with-spl.bin"
282 #define CONFIG_SYS_TEXT_BASE		0x11001000
283 #define CONFIG_SYS_LDSCRIPT	"arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
284 #endif
285 
286 #ifndef CONFIG_SYS_TEXT_BASE
287 #define CONFIG_SYS_TEXT_BASE		0xeff40000
288 #endif
289 
290 #ifndef CONFIG_RESET_VECTOR_ADDRESS
291 #define CONFIG_RESET_VECTOR_ADDRESS	0xeffffffc
292 #endif
293 
294 #ifndef CONFIG_SYS_MONITOR_BASE
295 #ifdef CONFIG_SPL_BUILD
296 #define CONFIG_SYS_MONITOR_BASE	CONFIG_SPL_TEXT_BASE
297 #else
298 #define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_TEXT_BASE	/* start of monitor */
299 #endif
300 #endif
301 
302 /* High Level Configuration Options */
303 #define CONFIG_BOOKE
304 #define CONFIG_E500
305 
306 #define CONFIG_MP
307 
308 #define CONFIG_FSL_ELBC
309 #define CONFIG_PCI
310 #define CONFIG_PCIE1	/* PCIE controler 1 (slot 1) */
311 #define CONFIG_PCIE2	/* PCIE controler 2 (slot 2) */
312 #define CONFIG_FSL_PCI_INIT	/* Use common FSL init code */
313 #define CONFIG_PCI_INDIRECT_BRIDGE	/* indirect PCI bridge support */
314 #define CONFIG_FSL_PCIE_RESET	/* need PCIe reset errata */
315 #define CONFIG_SYS_PCI_64BIT	/* enable 64-bit PCI resources */
316 
317 #define CONFIG_FSL_LAW
318 #define CONFIG_TSEC_ENET	/* tsec ethernet support */
319 #define CONFIG_ENV_OVERWRITE
320 
321 #define CONFIG_CMD_SATA
322 #define CONFIG_SATA_SIL
323 #define CONFIG_SYS_SATA_MAX_DEVICE	2
324 #define CONFIG_LIBATA
325 #define CONFIG_LBA48
326 
327 #if defined(CONFIG_P2020RDB)
328 #define CONFIG_SYS_CLK_FREQ	100000000
329 #else
330 #define CONFIG_SYS_CLK_FREQ	66666666
331 #endif
332 #define CONFIG_DDR_CLK_FREQ	66666666
333 
334 #define CONFIG_HWCONFIG
335 /*
336  * These can be toggled for performance analysis, otherwise use default.
337  */
338 #define CONFIG_L2_CACHE
339 #define CONFIG_BTB
340 
341 #define CONFIG_BOARD_EARLY_INIT_F	/* Call board_pre_init */
342 
343 #define CONFIG_ENABLE_36BIT_PHYS
344 
345 #ifdef CONFIG_PHYS_64BIT
346 #define CONFIG_ADDR_MAP			1
347 #define CONFIG_SYS_NUM_ADDR_MAP		16	/* number of TLB1 entries */
348 #endif
349 
350 #define CONFIG_SYS_MEMTEST_START	0x00200000	/* memtest works on */
351 #define CONFIG_SYS_MEMTEST_END		0x1fffffff
352 #define CONFIG_PANIC_HANG	/* do not reset board on panic */
353 
354 #define CONFIG_SYS_CCSRBAR		0xffe00000
355 #define CONFIG_SYS_CCSRBAR_PHYS_LOW	CONFIG_SYS_CCSRBAR
356 
357 /* IN case of NAND bootloader relocate CCSRBAR in RAMboot code not in the 4k
358        SPL code*/
359 #ifdef CONFIG_SPL_BUILD
360 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
361 #endif
362 
363 /* DDR Setup */
364 #define CONFIG_SYS_FSL_DDR3
365 #define CONFIG_SYS_DDR_RAW_TIMING
366 #define CONFIG_DDR_SPD
367 #define CONFIG_SYS_SPD_BUS_NUM 1
368 #define SPD_EEPROM_ADDRESS 0x52
369 #undef CONFIG_FSL_DDR_INTERACTIVE
370 
371 #if (defined(CONFIG_P1020MBG) || defined(CONFIG_P1020RDB_PD))
372 #define CONFIG_SYS_SDRAM_SIZE_LAW	LAW_SIZE_2G
373 #define CONFIG_CHIP_SELECTS_PER_CTRL	2
374 #else
375 #define CONFIG_SYS_SDRAM_SIZE_LAW	LAW_SIZE_1G
376 #define CONFIG_CHIP_SELECTS_PER_CTRL	1
377 #endif
378 #define CONFIG_SYS_SDRAM_SIZE		(1u << (CONFIG_SYS_SDRAM_SIZE_LAW - 19))
379 #define CONFIG_SYS_DDR_SDRAM_BASE	0x00000000
380 #define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_DDR_SDRAM_BASE
381 
382 #define CONFIG_NUM_DDR_CONTROLLERS	1
383 #define CONFIG_DIMM_SLOTS_PER_CTLR	1
384 
385 /* Default settings for DDR3 */
386 #ifndef CONFIG_P2020RDB
387 #define CONFIG_SYS_DDR_CS0_BNDS		0x0000003f
388 #define CONFIG_SYS_DDR_CS0_CONFIG	0x80014302
389 #define CONFIG_SYS_DDR_CS0_CONFIG_2	0x00000000
390 #define CONFIG_SYS_DDR_CS1_BNDS		0x0040007f
391 #define CONFIG_SYS_DDR_CS1_CONFIG	0x80014302
392 #define CONFIG_SYS_DDR_CS1_CONFIG_2	0x00000000
393 
394 #define CONFIG_SYS_DDR_DATA_INIT	0xdeadbeef
395 #define CONFIG_SYS_DDR_INIT_ADDR	0x00000000
396 #define CONFIG_SYS_DDR_INIT_EXT_ADDR	0x00000000
397 #define CONFIG_SYS_DDR_MODE_CONTROL	0x00000000
398 
399 #define CONFIG_SYS_DDR_ZQ_CONTROL	0x89080600
400 #define CONFIG_SYS_DDR_WRLVL_CONTROL	0x8655A608
401 #define CONFIG_SYS_DDR_SR_CNTR		0x00000000
402 #define CONFIG_SYS_DDR_RCW_1		0x00000000
403 #define CONFIG_SYS_DDR_RCW_2		0x00000000
404 #define CONFIG_SYS_DDR_CONTROL		0xC70C0000	/* Type = DDR3	*/
405 #define CONFIG_SYS_DDR_CONTROL_2	0x04401050
406 #define CONFIG_SYS_DDR_TIMING_4		0x00220001
407 #define CONFIG_SYS_DDR_TIMING_5		0x03402400
408 
409 #define CONFIG_SYS_DDR_TIMING_3		0x00020000
410 #define CONFIG_SYS_DDR_TIMING_0		0x00330004
411 #define CONFIG_SYS_DDR_TIMING_1		0x6f6B4846
412 #define CONFIG_SYS_DDR_TIMING_2		0x0FA8C8CF
413 #define CONFIG_SYS_DDR_CLK_CTRL		0x03000000
414 #define CONFIG_SYS_DDR_MODE_1		0x40461520
415 #define CONFIG_SYS_DDR_MODE_2		0x8000c000
416 #define CONFIG_SYS_DDR_INTERVAL		0x0C300000
417 #endif
418 
419 #undef CONFIG_CLOCKS_IN_MHZ
420 
421 /*
422  * Memory map
423  *
424  * 0x0000_0000 0x7fff_ffff	DDR		Up to 2GB cacheable
425  * 0x8000_0000 0xdfff_ffff	PCI Express Mem	1.5G non-cacheable(PCIe * 3)
426  * 0xec00_0000 0xefff_ffff	NOR flash	Up to 64M non-cacheable	CS0/1
427  * 0xf8f8_0000 0xf8ff_ffff	L2 SRAM		Up to 512K cacheable
428  *   (early boot only)
429  * 0xff80_0000 0xff80_7fff	NAND flash	32K non-cacheable	CS1/0
430  * 0xff98_0000 0xff98_ffff	PMC		64K non-cacheable	CS2
431  * 0xffa0_0000 0xffaf_ffff	CPLD		1M non-cacheable	CS3
432  * 0xffb0_0000 0xffbf_ffff	VSC7385 switch  1M non-cacheable	CS2
433  * 0xffc0_0000 0xffc3_ffff	PCI IO range	256k non-cacheable
434  * 0xffd0_0000 0xffd0_3fff	L1 for stack	16K cacheable
435  * 0xffe0_0000 0xffef_ffff	CCSR		1M non-cacheable
436  */
437 
438 
439 /*
440  * Local Bus Definitions
441  */
442 #if (defined(CONFIG_P1020MBG) || defined(CONFIG_P1020RDB_PD))
443 #define CONFIG_SYS_MAX_FLASH_SECT	512	/* 64M */
444 #define CONFIG_SYS_FLASH_BASE		0xec000000
445 #elif defined(CONFIG_P1020UTM)
446 #define CONFIG_SYS_MAX_FLASH_SECT	256	/* 32M */
447 #define CONFIG_SYS_FLASH_BASE		0xee000000
448 #else
449 #define CONFIG_SYS_MAX_FLASH_SECT	128	/* 16M */
450 #define CONFIG_SYS_FLASH_BASE		0xef000000
451 #endif
452 
453 
454 #ifdef CONFIG_PHYS_64BIT
455 #define CONFIG_SYS_FLASH_BASE_PHYS	(0xf00000000ull | CONFIG_SYS_FLASH_BASE)
456 #else
457 #define CONFIG_SYS_FLASH_BASE_PHYS	CONFIG_SYS_FLASH_BASE
458 #endif
459 
460 #define CONFIG_FLASH_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) \
461 	| BR_PS_16 | BR_V)
462 
463 #define CONFIG_FLASH_OR_PRELIM	0xfc000ff7
464 
465 #define CONFIG_SYS_FLASH_BANKS_LIST	{CONFIG_SYS_FLASH_BASE_PHYS}
466 #define CONFIG_SYS_FLASH_QUIET_TEST
467 #define CONFIG_FLASH_SHOW_PROGRESS	45	/* count down from 45/5: 9..1 */
468 
469 #define CONFIG_SYS_MAX_FLASH_BANKS	1	/* number of banks */
470 
471 #undef CONFIG_SYS_FLASH_CHECKSUM
472 #define CONFIG_SYS_FLASH_ERASE_TOUT	60000	/* Flash Erase Timeout (ms) */
473 #define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (ms) */
474 
475 #define CONFIG_FLASH_CFI_DRIVER
476 #define CONFIG_SYS_FLASH_CFI
477 #define CONFIG_SYS_FLASH_EMPTY_INFO
478 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
479 
480 /* Nand Flash */
481 #ifdef CONFIG_NAND_FSL_ELBC
482 #define CONFIG_SYS_NAND_BASE		0xff800000
483 #ifdef CONFIG_PHYS_64BIT
484 #define CONFIG_SYS_NAND_BASE_PHYS	0xfff800000ull
485 #else
486 #define CONFIG_SYS_NAND_BASE_PHYS	CONFIG_SYS_NAND_BASE
487 #endif
488 
489 #define CONFIG_SYS_NAND_BASE_LIST	{ CONFIG_SYS_NAND_BASE }
490 #define CONFIG_SYS_MAX_NAND_DEVICE	1
491 #define CONFIG_CMD_NAND
492 #if defined(CONFIG_P1020RDB_PD)
493 #define CONFIG_SYS_NAND_BLOCK_SIZE	(128 * 1024)
494 #else
495 #define CONFIG_SYS_NAND_BLOCK_SIZE	(16 * 1024)
496 #endif
497 
498 #define CONFIG_SYS_NAND_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
499 	| (2<<BR_DECC_SHIFT)	/* Use HW ECC */ \
500 	| BR_PS_8	/* Port Size = 8 bit */ \
501 	| BR_MS_FCM	/* MSEL = FCM */ \
502 	| BR_V)	/* valid */
503 #if defined(CONFIG_P1020RDB_PD)
504 #define CONFIG_SYS_NAND_OR_PRELIM	(OR_AM_32KB \
505 	| OR_FCM_PGS	/* Large Page*/ \
506 	| OR_FCM_CSCT \
507 	| OR_FCM_CST \
508 	| OR_FCM_CHT \
509 	| OR_FCM_SCY_1 \
510 	| OR_FCM_TRLX \
511 	| OR_FCM_EHTR)
512 #else
513 #define CONFIG_SYS_NAND_OR_PRELIM	(OR_AM_32KB	/* small page */ \
514 	| OR_FCM_CSCT \
515 	| OR_FCM_CST \
516 	| OR_FCM_CHT \
517 	| OR_FCM_SCY_1 \
518 	| OR_FCM_TRLX \
519 	| OR_FCM_EHTR)
520 #endif
521 #endif /* CONFIG_NAND_FSL_ELBC */
522 
523 #define CONFIG_BOARD_EARLY_INIT_R	/* call board_early_init_r function */
524 
525 #define CONFIG_SYS_INIT_RAM_LOCK
526 #define CONFIG_SYS_INIT_RAM_ADDR	0xffd00000 /* stack in RAM */
527 #ifdef CONFIG_PHYS_64BIT
528 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
529 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR
530 /* The assembler doesn't like typecast */
531 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
532 	((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
533 	  CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
534 #else
535 /* Initial L1 address */
536 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS	CONFIG_SYS_INIT_RAM_ADDR
537 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0
538 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS
539 #endif
540 /* Size of used area in RAM */
541 #define CONFIG_SYS_INIT_RAM_SIZE	0x00004000
542 
543 #define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - \
544 					GENERATED_GBL_DATA_SIZE)
545 #define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
546 
547 #define CONFIG_SYS_MONITOR_LEN	(768 * 1024)
548 #define CONFIG_SYS_MALLOC_LEN	(1024 * 1024)/* Reserved for malloc */
549 
550 #define CONFIG_SYS_CPLD_BASE	0xffa00000
551 #ifdef CONFIG_PHYS_64BIT
552 #define CONFIG_SYS_CPLD_BASE_PHYS	0xfffa00000ull
553 #else
554 #define CONFIG_SYS_CPLD_BASE_PHYS	CONFIG_SYS_CPLD_BASE
555 #endif
556 /* CPLD config size: 1Mb */
557 #define CONFIG_CPLD_BR_PRELIM	(BR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE_PHYS) | \
558 					BR_PS_8 | BR_V)
559 #define CONFIG_CPLD_OR_PRELIM	(0xfff009f7)
560 
561 #define CONFIG_SYS_PMC_BASE	0xff980000
562 #define CONFIG_SYS_PMC_BASE_PHYS	CONFIG_SYS_PMC_BASE
563 #define CONFIG_PMC_BR_PRELIM	(BR_PHYS_ADDR(CONFIG_SYS_PMC_BASE_PHYS) | \
564 					BR_PS_8 | BR_V)
565 #define CONFIG_PMC_OR_PRELIM	(OR_AM_64KB | OR_GPCM_CSNT | OR_GPCM_XACS | \
566 				 OR_GPCM_SCY | OR_GPCM_TRLX | OR_GPCM_EHTR | \
567 				 OR_GPCM_EAD)
568 
569 #ifdef CONFIG_NAND
570 #define CONFIG_SYS_BR0_PRELIM	CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Addr */
571 #define CONFIG_SYS_OR0_PRELIM	CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
572 #define CONFIG_SYS_BR1_PRELIM	CONFIG_FLASH_BR_PRELIM	/* NOR Base Address */
573 #define CONFIG_SYS_OR1_PRELIM	CONFIG_FLASH_OR_PRELIM	/* NOR Options */
574 #else
575 #define CONFIG_SYS_BR0_PRELIM	CONFIG_FLASH_BR_PRELIM	/* NOR Base Address */
576 #define CONFIG_SYS_OR0_PRELIM	CONFIG_FLASH_OR_PRELIM	/* NOR Options */
577 #ifdef CONFIG_NAND_FSL_ELBC
578 #define CONFIG_SYS_BR1_PRELIM	CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Addr */
579 #define CONFIG_SYS_OR1_PRELIM	CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
580 #endif
581 #endif
582 #define CONFIG_SYS_BR3_PRELIM	CONFIG_CPLD_BR_PRELIM	/* CPLD Base Address */
583 #define CONFIG_SYS_OR3_PRELIM	CONFIG_CPLD_OR_PRELIM	/* CPLD Options */
584 
585 
586 /* Vsc7385 switch */
587 #ifdef CONFIG_VSC7385_ENET
588 #define CONFIG_SYS_VSC7385_BASE		0xffb00000
589 
590 #ifdef CONFIG_PHYS_64BIT
591 #define CONFIG_SYS_VSC7385_BASE_PHYS	0xfffb00000ull
592 #else
593 #define CONFIG_SYS_VSC7385_BASE_PHYS	CONFIG_SYS_VSC7385_BASE
594 #endif
595 
596 #define CONFIG_SYS_VSC7385_BR_PRELIM	\
597 	(BR_PHYS_ADDR(CONFIG_SYS_VSC7385_BASE_PHYS) | BR_PS_8 | BR_V)
598 #define CONFIG_SYS_VSC7385_OR_PRELIM	(OR_AM_128KB | OR_GPCM_CSNT | \
599 			OR_GPCM_XACS |  OR_GPCM_SCY_15 | OR_GPCM_SETA | \
600 			OR_GPCM_TRLX |  OR_GPCM_EHTR | OR_GPCM_EAD)
601 
602 #define CONFIG_SYS_BR2_PRELIM	CONFIG_SYS_VSC7385_BR_PRELIM
603 #define CONFIG_SYS_OR2_PRELIM	CONFIG_SYS_VSC7385_OR_PRELIM
604 
605 /* The size of the VSC7385 firmware image */
606 #define CONFIG_VSC7385_IMAGE_SIZE	8192
607 #endif
608 
609 /*
610  * Config the L2 Cache as L2 SRAM
611 */
612 #if defined(CONFIG_SPL_BUILD)
613 #if defined(CONFIG_SDCARD) || defined(CONFIG_SPIFLASH)
614 #define CONFIG_SYS_INIT_L2_ADDR		0xf8f80000
615 #define CONFIG_SYS_INIT_L2_ADDR_PHYS	CONFIG_SYS_INIT_L2_ADDR
616 #define CONFIG_SYS_INIT_L2_END	(CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
617 #define CONFIG_SPL_RELOC_TEXT_BASE	0xf8f81000
618 #define CONFIG_SPL_GD_ADDR		(CONFIG_SYS_INIT_L2_ADDR + 112 * 1024)
619 #define CONFIG_SPL_RELOC_STACK		(CONFIG_SYS_INIT_L2_ADDR + 116 * 1024)
620 #define CONFIG_SPL_RELOC_STACK_SIZE	(32 << 10)
621 #define CONFIG_SPL_RELOC_MALLOC_ADDR	(CONFIG_SYS_INIT_L2_ADDR + 148 * 1024)
622 #if defined(CONFIG_P2020RDB)
623 #define CONFIG_SPL_RELOC_MALLOC_SIZE	(364 << 10)
624 #else
625 #define CONFIG_SPL_RELOC_MALLOC_SIZE	(108 << 10)
626 #endif
627 #elif defined(CONFIG_NAND)
628 #ifdef CONFIG_TPL_BUILD
629 #define CONFIG_SYS_INIT_L2_ADDR		0xf8f80000
630 #define CONFIG_SYS_INIT_L2_ADDR_PHYS	CONFIG_SYS_INIT_L2_ADDR
631 #define CONFIG_SYS_INIT_L2_END	(CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
632 #define CONFIG_SPL_RELOC_TEXT_BASE	0xf8f81000
633 #define CONFIG_SPL_RELOC_STACK		(CONFIG_SYS_INIT_L2_ADDR + 192 * 1024)
634 #define CONFIG_SPL_RELOC_MALLOC_ADDR	(CONFIG_SYS_INIT_L2_ADDR + 208 * 1024)
635 #define CONFIG_SPL_RELOC_MALLOC_SIZE	(48 << 10)
636 #define CONFIG_SPL_GD_ADDR		(CONFIG_SYS_INIT_L2_ADDR + 176 * 1024)
637 #else
638 #define CONFIG_SYS_INIT_L2_ADDR		0xf8f80000
639 #define CONFIG_SYS_INIT_L2_ADDR_PHYS	CONFIG_SYS_INIT_L2_ADDR
640 #define CONFIG_SYS_INIT_L2_END	(CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
641 #define CONFIG_SPL_RELOC_TEXT_BASE	(CONFIG_SYS_INIT_L2_END - 0x2000)
642 #define CONFIG_SPL_RELOC_STACK		((CONFIG_SYS_INIT_L2_END - 1) & ~0xF)
643 #endif /* CONFIG_TPL_BUILD */
644 #endif
645 #endif
646 
647 /* Serial Port - controlled on board with jumper J8
648  * open - index 2
649  * shorted - index 1
650  */
651 #define CONFIG_CONS_INDEX		1
652 #undef CONFIG_SERIAL_SOFTWARE_FIFO
653 #define CONFIG_SYS_NS16550
654 #define CONFIG_SYS_NS16550_SERIAL
655 #define CONFIG_SYS_NS16550_REG_SIZE	1
656 #define CONFIG_SYS_NS16550_CLK		get_bus_freq(0)
657 #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_INIT_MINIMAL)
658 #define CONFIG_NS16550_MIN_FUNCTIONS
659 #endif
660 
661 #define CONFIG_SYS_BAUDRATE_TABLE	\
662 	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
663 
664 #define CONFIG_SYS_NS16550_COM1	(CONFIG_SYS_CCSRBAR+0x4500)
665 #define CONFIG_SYS_NS16550_COM2	(CONFIG_SYS_CCSRBAR+0x4600)
666 
667 /* Use the HUSH parser */
668 #define CONFIG_SYS_HUSH_PARSER
669 
670 /*
671  * Pass open firmware flat tree
672  */
673 #define CONFIG_OF_LIBFDT
674 #define CONFIG_OF_BOARD_SETUP
675 #define CONFIG_OF_STDOUT_VIA_ALIAS
676 
677 /* new uImage format support */
678 #define CONFIG_FIT
679 #define CONFIG_FIT_VERBOSE	/* enable fit_format_{error,warning}() */
680 
681 /* I2C */
682 #define CONFIG_SYS_I2C
683 #define CONFIG_SYS_I2C_FSL
684 #define CONFIG_SYS_FSL_I2C_SPEED	400000
685 #define CONFIG_SYS_FSL_I2C_SLAVE	0x7F
686 #define CONFIG_SYS_FSL_I2C_OFFSET	0x3000
687 #define CONFIG_SYS_FSL_I2C2_SPEED	400000
688 #define CONFIG_SYS_FSL_I2C2_SLAVE	0x7F
689 #define CONFIG_SYS_FSL_I2C2_OFFSET	0x3100
690 #define CONFIG_SYS_I2C_NOPROBES		{ {0, 0x29} }
691 #define CONFIG_SYS_I2C_EEPROM_ADDR	0x52
692 #define CONFIG_SYS_SPD_BUS_NUM		1 /* For rom_loc and flash bank */
693 
694 /*
695  * I2C2 EEPROM
696  */
697 #undef CONFIG_ID_EEPROM
698 
699 #define CONFIG_RTC_PT7C4338
700 #define CONFIG_SYS_I2C_RTC_ADDR		0x68
701 #define CONFIG_SYS_I2C_PCA9557_ADDR	0x18
702 
703 /* enable read and write access to EEPROM */
704 #define CONFIG_CMD_EEPROM
705 #define CONFIG_SYS_I2C_MULTI_EEPROMS
706 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
707 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
708 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
709 
710 /*
711  * eSPI - Enhanced SPI
712  */
713 #define CONFIG_HARD_SPI
714 #define CONFIG_FSL_ESPI
715 
716 #if defined(CONFIG_SPI_FLASH)
717 #define CONFIG_SPI_FLASH_SPANSION
718 #define CONFIG_CMD_SF
719 #define CONFIG_SF_DEFAULT_SPEED	10000000
720 #define CONFIG_SF_DEFAULT_MODE	0
721 #endif
722 
723 #if defined(CONFIG_PCI)
724 /*
725  * General PCI
726  * Memory space is mapped 1-1, but I/O space must start from 0.
727  */
728 
729 /* controller 2, direct to uli, tgtid 2, Base address 9000 */
730 #define CONFIG_SYS_PCIE2_NAME		"PCIe SLOT"
731 #define CONFIG_SYS_PCIE2_MEM_VIRT	0xa0000000
732 #ifdef CONFIG_PHYS_64BIT
733 #define CONFIG_SYS_PCIE2_MEM_BUS	0xc0000000
734 #define CONFIG_SYS_PCIE2_MEM_PHYS	0xc20000000ull
735 #else
736 #define CONFIG_SYS_PCIE2_MEM_BUS	0xa0000000
737 #define CONFIG_SYS_PCIE2_MEM_PHYS	0xa0000000
738 #endif
739 #define CONFIG_SYS_PCIE2_MEM_SIZE	0x20000000	/* 512M */
740 #define CONFIG_SYS_PCIE2_IO_VIRT	0xffc10000
741 #define CONFIG_SYS_PCIE2_IO_BUS		0x00000000
742 #ifdef CONFIG_PHYS_64BIT
743 #define CONFIG_SYS_PCIE2_IO_PHYS	0xfffc10000ull
744 #else
745 #define CONFIG_SYS_PCIE2_IO_PHYS	0xffc10000
746 #endif
747 #define CONFIG_SYS_PCIE2_IO_SIZE	0x00010000	/* 64k */
748 
749 /* controller 1, Slot 2, tgtid 1, Base address a000 */
750 #define CONFIG_SYS_PCIE1_NAME		"mini PCIe SLOT"
751 #define CONFIG_SYS_PCIE1_MEM_VIRT	0x80000000
752 #ifdef CONFIG_PHYS_64BIT
753 #define CONFIG_SYS_PCIE1_MEM_BUS	0x80000000
754 #define CONFIG_SYS_PCIE1_MEM_PHYS	0xc00000000ull
755 #else
756 #define CONFIG_SYS_PCIE1_MEM_BUS	0x80000000
757 #define CONFIG_SYS_PCIE1_MEM_PHYS	0x80000000
758 #endif
759 #define CONFIG_SYS_PCIE1_MEM_SIZE	0x20000000	/* 512M */
760 #define CONFIG_SYS_PCIE1_IO_VIRT	0xffc00000
761 #define CONFIG_SYS_PCIE1_IO_BUS		0x00000000
762 #ifdef CONFIG_PHYS_64BIT
763 #define CONFIG_SYS_PCIE1_IO_PHYS	0xfffc00000ull
764 #else
765 #define CONFIG_SYS_PCIE1_IO_PHYS	0xffc00000
766 #endif
767 #define CONFIG_SYS_PCIE1_IO_SIZE	0x00010000	/* 64k */
768 
769 #define CONFIG_PCI_PNP	/* do pci plug-and-play */
770 #define CONFIG_CMD_PCI
771 
772 #define CONFIG_PCI_SCAN_SHOW	/* show pci devices on startup */
773 #define CONFIG_DOS_PARTITION
774 #endif /* CONFIG_PCI */
775 
776 #if defined(CONFIG_TSEC_ENET)
777 #define CONFIG_MII		/* MII PHY management */
778 #define CONFIG_TSEC1
779 #define CONFIG_TSEC1_NAME	"eTSEC1"
780 #define CONFIG_TSEC2
781 #define CONFIG_TSEC2_NAME	"eTSEC2"
782 #define CONFIG_TSEC3
783 #define CONFIG_TSEC3_NAME	"eTSEC3"
784 
785 #define TSEC1_PHY_ADDR	2
786 #define TSEC2_PHY_ADDR	0
787 #define TSEC3_PHY_ADDR	1
788 
789 #define TSEC1_FLAGS	(TSEC_GIGABIT | TSEC_REDUCED)
790 #define TSEC2_FLAGS	(TSEC_GIGABIT | TSEC_REDUCED)
791 #define TSEC3_FLAGS	(TSEC_GIGABIT | TSEC_REDUCED)
792 
793 #define TSEC1_PHYIDX	0
794 #define TSEC2_PHYIDX	0
795 #define TSEC3_PHYIDX	0
796 
797 #define CONFIG_ETHPRIME	"eTSEC1"
798 
799 #define CONFIG_PHY_GIGE	1	/* Include GbE speed/duplex detection */
800 
801 #define CONFIG_HAS_ETH0
802 #define CONFIG_HAS_ETH1
803 #define CONFIG_HAS_ETH2
804 #endif /* CONFIG_TSEC_ENET */
805 
806 #ifdef CONFIG_QE
807 /* QE microcode/firmware address */
808 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR
809 #define CONFIG_SYS_QE_FW_ADDR	0xefec0000
810 #define CONFIG_SYS_QE_FMAN_FW_LENGTH	0x10000
811 #endif /* CONFIG_QE */
812 
813 #ifdef CONFIG_P1025RDB
814 /*
815  * QE UEC ethernet configuration
816  */
817 #define CONFIG_MIIM_ADDRESS	(CONFIG_SYS_CCSRBAR + 0x82120)
818 
819 #undef CONFIG_UEC_ETH
820 #define CONFIG_PHY_MODE_NEED_CHANGE
821 
822 #define CONFIG_UEC_ETH1	/* ETH1 */
823 #define CONFIG_HAS_ETH0
824 
825 #ifdef CONFIG_UEC_ETH1
826 #define CONFIG_SYS_UEC1_UCC_NUM	0	/* UCC1 */
827 #define CONFIG_SYS_UEC1_RX_CLK	QE_CLK12 /* CLK12 for MII */
828 #define CONFIG_SYS_UEC1_TX_CLK	QE_CLK9 /* CLK9 for MII */
829 #define CONFIG_SYS_UEC1_ETH_TYPE	FAST_ETH
830 #define CONFIG_SYS_UEC1_PHY_ADDR	0x0	/* 0x0 for MII */
831 #define CONFIG_SYS_UEC1_INTERFACE_TYPE PHY_INTERFACE_MODE_RMII
832 #define CONFIG_SYS_UEC1_INTERFACE_SPEED	100
833 #endif /* CONFIG_UEC_ETH1 */
834 
835 #define CONFIG_UEC_ETH5	/* ETH5 */
836 #define CONFIG_HAS_ETH1
837 
838 #ifdef CONFIG_UEC_ETH5
839 #define CONFIG_SYS_UEC5_UCC_NUM	4	/* UCC5 */
840 #define CONFIG_SYS_UEC5_RX_CLK	QE_CLK_NONE
841 #define CONFIG_SYS_UEC5_TX_CLK	QE_CLK13 /* CLK 13 for RMII */
842 #define CONFIG_SYS_UEC5_ETH_TYPE	FAST_ETH
843 #define CONFIG_SYS_UEC5_PHY_ADDR	0x3	/* 0x3 for RMII */
844 #define CONFIG_SYS_UEC5_INTERFACE_TYPE PHY_INTERFACE_MODE_RMII
845 #define CONFIG_SYS_UEC5_INTERFACE_SPEED	100
846 #endif /* CONFIG_UEC_ETH5 */
847 #endif /* CONFIG_P1025RDB */
848 
849 /*
850  * Environment
851  */
852 #ifdef CONFIG_SPIFLASH
853 #define CONFIG_ENV_IS_IN_SPI_FLASH
854 #define CONFIG_ENV_SPI_BUS	0
855 #define CONFIG_ENV_SPI_CS	0
856 #define CONFIG_ENV_SPI_MAX_HZ	10000000
857 #define CONFIG_ENV_SPI_MODE	0
858 #define CONFIG_ENV_SIZE		0x2000	/* 8KB */
859 #define CONFIG_ENV_OFFSET	0x100000	/* 1MB */
860 #define CONFIG_ENV_SECT_SIZE	0x10000
861 #elif defined(CONFIG_SDCARD)
862 #define CONFIG_ENV_IS_IN_MMC
863 #define CONFIG_FSL_FIXED_MMC_LOCATION
864 #define CONFIG_ENV_SIZE		0x2000
865 #define CONFIG_SYS_MMC_ENV_DEV	0
866 #elif defined(CONFIG_NAND)
867 #ifdef CONFIG_TPL_BUILD
868 #define CONFIG_ENV_SIZE		0x2000
869 #define CONFIG_ENV_ADDR		(CONFIG_SYS_INIT_L2_ADDR + (160 << 10))
870 #else
871 #define CONFIG_ENV_SIZE		CONFIG_SYS_NAND_BLOCK_SIZE
872 #endif
873 #define CONFIG_ENV_IS_IN_NAND
874 #define CONFIG_ENV_OFFSET	(1024 * 1024)
875 #define CONFIG_ENV_RANGE	(3 * CONFIG_ENV_SIZE)
876 #elif defined(CONFIG_SYS_RAMBOOT)
877 #define CONFIG_ENV_IS_NOWHERE	/* Store ENV in memory only */
878 #define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE - 0x1000)
879 #define CONFIG_ENV_SIZE		0x2000
880 #else
881 #define CONFIG_ENV_IS_IN_FLASH
882 #define CONFIG_ENV_ADDR	(CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
883 #define CONFIG_ENV_SIZE		0x2000
884 #define CONFIG_ENV_SECT_SIZE	0x20000 /* 128K (one sector) */
885 #endif
886 
887 #define CONFIG_LOADS_ECHO		/* echo on for serial download */
888 #define CONFIG_SYS_LOADS_BAUD_CHANGE	/* allow baudrate change */
889 
890 /*
891  * Command line configuration.
892  */
893 #define CONFIG_CMD_IRQ
894 #define CONFIG_CMD_PING
895 #define CONFIG_CMD_I2C
896 #define CONFIG_CMD_MII
897 #define CONFIG_CMD_DATE
898 #define CONFIG_CMD_ELF
899 #define CONFIG_CMD_REGINFO
900 
901 /*
902  * USB
903  */
904 #define CONFIG_HAS_FSL_DR_USB
905 
906 #if defined(CONFIG_HAS_FSL_DR_USB)
907 #define CONFIG_USB_EHCI
908 
909 #ifdef CONFIG_USB_EHCI
910 #define CONFIG_CMD_USB
911 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
912 #define CONFIG_USB_EHCI_FSL
913 #define CONFIG_USB_STORAGE
914 #endif
915 #endif
916 
917 #if defined(CONFIG_P1020RDB_PD)
918 #define CONFIG_USB_MAX_CONTROLLER_COUNT	1
919 #endif
920 
921 #define CONFIG_MMC
922 
923 #ifdef CONFIG_MMC
924 #define CONFIG_FSL_ESDHC
925 #define CONFIG_SYS_FSL_ESDHC_ADDR	CONFIG_SYS_MPC85xx_ESDHC_ADDR
926 #define CONFIG_CMD_MMC
927 #define CONFIG_GENERIC_MMC
928 #endif
929 
930 #if defined(CONFIG_MMC) || defined(CONFIG_USB_EHCI) \
931 		 || defined(CONFIG_FSL_SATA)
932 #define CONFIG_CMD_EXT2
933 #define CONFIG_CMD_FAT
934 #define CONFIG_DOS_PARTITION
935 #endif
936 
937 #undef CONFIG_WATCHDOG	/* watchdog disabled */
938 
939 /*
940  * Miscellaneous configurable options
941  */
942 #define CONFIG_SYS_LONGHELP			/* undef to save memory */
943 #define CONFIG_CMDLINE_EDITING			/* Command-line editing */
944 #define CONFIG_SYS_LOAD_ADDR	0x2000000	/* default load address */
945 #if defined(CONFIG_CMD_KGDB)
946 #define CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size */
947 #else
948 #define CONFIG_SYS_CBSIZE	256		/* Console I/O Buffer Size */
949 #endif
950 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
951 	/* Print Buffer Size */
952 #define CONFIG_SYS_MAXARGS	16	/* max number of command args */
953 #define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */
954 
955 /*
956  * For booting Linux, the board info and command line data
957  * have to be in the first 64 MB of memory, since this is
958  * the maximum mapped by the Linux kernel during initialization.
959  */
960 #define CONFIG_SYS_BOOTMAPSZ	(64 << 20)	/* Initial Memory for Linux*/
961 #define CONFIG_SYS_BOOTM_LEN	(64 << 20)	/* Increase max gunzip size */
962 
963 #if defined(CONFIG_CMD_KGDB)
964 #define CONFIG_KGDB_BAUDRATE	230400	/* speed to run kgdb serial port */
965 #endif
966 
967 /*
968  * Environment Configuration
969  */
970 #define CONFIG_HOSTNAME		unknown
971 #define CONFIG_ROOTPATH		"/opt/nfsroot"
972 #define CONFIG_BOOTFILE		"uImage"
973 #define CONFIG_UBOOTPATH	u-boot.bin /* U-Boot image on TFTP server */
974 
975 /* default location for tftp and bootm */
976 #define CONFIG_LOADADDR	1000000
977 
978 #define CONFIG_BOOTDELAY 10	/* -1 disables auto-boot */
979 #define CONFIG_BOOTARGS	/* the boot command will set bootargs */
980 
981 #define CONFIG_BAUDRATE	115200
982 
983 #ifdef __SW_BOOT_NOR
984 #define __NOR_RST_CMD	\
985 norboot=i2c dev 1; i2c mw 18 1 __SW_BOOT_NOR 1; \
986 i2c mw 18 3 __SW_BOOT_MASK 1; reset
987 #endif
988 #ifdef __SW_BOOT_SPI
989 #define __SPI_RST_CMD	\
990 spiboot=i2c dev 1; i2c mw 18 1 __SW_BOOT_SPI 1; \
991 i2c mw 18 3 __SW_BOOT_MASK 1; reset
992 #endif
993 #ifdef __SW_BOOT_SD
994 #define __SD_RST_CMD	\
995 sdboot=i2c dev 1; i2c mw 18 1 __SW_BOOT_SD 1; \
996 i2c mw 18 3 __SW_BOOT_MASK 1; reset
997 #endif
998 #ifdef __SW_BOOT_NAND
999 #define __NAND_RST_CMD	\
1000 nandboot=i2c dev 1; i2c mw 18 1 __SW_BOOT_NAND 1; \
1001 i2c mw 18 3 __SW_BOOT_MASK 1; reset
1002 #endif
1003 #ifdef __SW_BOOT_PCIE
1004 #define __PCIE_RST_CMD	\
1005 pciboot=i2c dev 1; i2c mw 18 1 __SW_BOOT_PCIE 1; \
1006 i2c mw 18 3 __SW_BOOT_MASK 1; reset
1007 #endif
1008 
1009 #define	CONFIG_EXTRA_ENV_SETTINGS	\
1010 "netdev=eth0\0"	\
1011 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0"	\
1012 "loadaddr=1000000\0"	\
1013 "bootfile=uImage\0"	\
1014 "tftpflash=tftpboot $loadaddr $uboot; "	\
1015 	"protect off " __stringify(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
1016 	"erase " __stringify(CONFIG_SYS_TEXT_BASE) " +$filesize; "	\
1017 	"cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) " $filesize; " \
1018 	"protect on " __stringify(CONFIG_SYS_TEXT_BASE) " +$filesize; "	\
1019 	"cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) " $filesize\0" \
1020 "hwconfig=usb1:dr_mode=host,phy_type=ulpi\0"    \
1021 "consoledev=ttyS0\0"	\
1022 "ramdiskaddr=2000000\0"	\
1023 "ramdiskfile=rootfs.ext2.gz.uboot\0"	\
1024 "fdtaddr=c00000\0"	\
1025 "bdev=sda1\0" \
1026 "jffs2nor=mtdblock3\0"	\
1027 "norbootaddr=ef080000\0"	\
1028 "norfdtaddr=ef040000\0"	\
1029 "jffs2nand=mtdblock9\0"	\
1030 "nandbootaddr=100000\0"	\
1031 "nandfdtaddr=80000\0"		\
1032 "ramdisk_size=120000\0"	\
1033 "map_lowernorbank=i2c dev 1; i2c mw 18 1 02 1; i2c mw 18 3 fd 1\0" \
1034 "map_uppernorbank=i2c dev 1; i2c mw 18 1 00 1; i2c mw 18 3 fd 1\0" \
1035 __stringify(__NOR_RST_CMD)"\0" \
1036 __stringify(__SPI_RST_CMD)"\0" \
1037 __stringify(__SD_RST_CMD)"\0" \
1038 __stringify(__NAND_RST_CMD)"\0" \
1039 __stringify(__PCIE_RST_CMD)"\0"
1040 
1041 #define CONFIG_NFSBOOTCOMMAND	\
1042 "setenv bootargs root=/dev/nfs rw "	\
1043 "nfsroot=$serverip:$rootpath "	\
1044 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
1045 "console=$consoledev,$baudrate $othbootargs;" \
1046 "tftp $loadaddr $bootfile;"	\
1047 "tftp $fdtaddr $fdtfile;"	\
1048 "bootm $loadaddr - $fdtaddr"
1049 
1050 #define CONFIG_HDBOOT	\
1051 "setenv bootargs root=/dev/$bdev rw rootdelay=30 "	\
1052 "console=$consoledev,$baudrate $othbootargs;" \
1053 "usb start;"	\
1054 "ext2load usb 0:1 $loadaddr /boot/$bootfile;"	\
1055 "ext2load usb 0:1 $fdtaddr /boot/$fdtfile;"	\
1056 "bootm $loadaddr - $fdtaddr"
1057 
1058 #define CONFIG_USB_FAT_BOOT	\
1059 "setenv bootargs root=/dev/ram rw "	\
1060 "console=$consoledev,$baudrate $othbootargs " \
1061 "ramdisk_size=$ramdisk_size;"	\
1062 "usb start;"	\
1063 "fatload usb 0:2 $loadaddr $bootfile;"	\
1064 "fatload usb 0:2 $fdtaddr $fdtfile;"	\
1065 "fatload usb 0:2 $ramdiskaddr $ramdiskfile;"	\
1066 "bootm $loadaddr $ramdiskaddr $fdtaddr"
1067 
1068 #define CONFIG_USB_EXT2_BOOT	\
1069 "setenv bootargs root=/dev/ram rw "	\
1070 "console=$consoledev,$baudrate $othbootargs " \
1071 "ramdisk_size=$ramdisk_size;"	\
1072 "usb start;"	\
1073 "ext2load usb 0:4 $loadaddr $bootfile;"	\
1074 "ext2load usb 0:4 $fdtaddr $fdtfile;" \
1075 "ext2load usb 0:4 $ramdiskaddr $ramdiskfile;" \
1076 "bootm $loadaddr $ramdiskaddr $fdtaddr"
1077 
1078 #define CONFIG_NORBOOT	\
1079 "setenv bootargs root=/dev/$jffs2nor rw "	\
1080 "console=$consoledev,$baudrate rootfstype=jffs2 $othbootargs;"	\
1081 "bootm $norbootaddr - $norfdtaddr"
1082 
1083 #define CONFIG_RAMBOOTCOMMAND	\
1084 "setenv bootargs root=/dev/ram rw "	\
1085 "console=$consoledev,$baudrate $othbootargs " \
1086 "ramdisk_size=$ramdisk_size;"	\
1087 "tftp $ramdiskaddr $ramdiskfile;"	\
1088 "tftp $loadaddr $bootfile;"	\
1089 "tftp $fdtaddr $fdtfile;"	\
1090 "bootm $loadaddr $ramdiskaddr $fdtaddr"
1091 
1092 #define CONFIG_BOOTCOMMAND	CONFIG_HDBOOT
1093 
1094 #endif /* __CONFIG_H */
1095