1 /* 2 * Copyright 2010-2011 Freescale Semiconductor, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 /* 8 * QorIQ RDB boards configuration file 9 */ 10 #ifndef __CONFIG_H 11 #define __CONFIG_H 12 13 #define CONFIG_DISPLAY_BOARDINFO 14 15 #if defined(CONFIG_P1020MBG) 16 #define CONFIG_BOARDNAME "P1020MBG-PC" 17 #define CONFIG_P1020 18 #define CONFIG_VSC7385_ENET 19 #define CONFIG_SLIC 20 #define __SW_BOOT_MASK 0x03 21 #define __SW_BOOT_NOR 0xe4 22 #define __SW_BOOT_SD 0x54 23 #define CONFIG_SYS_L2_SIZE (256 << 10) 24 #endif 25 26 #if defined(CONFIG_P1020UTM) 27 #define CONFIG_BOARDNAME "P1020UTM-PC" 28 #define CONFIG_P1020 29 #define __SW_BOOT_MASK 0x03 30 #define __SW_BOOT_NOR 0xe0 31 #define __SW_BOOT_SD 0x50 32 #define CONFIG_SYS_L2_SIZE (256 << 10) 33 #endif 34 35 #if defined(CONFIG_P1020RDB_PC) 36 #define CONFIG_BOARDNAME "P1020RDB-PC" 37 #define CONFIG_NAND_FSL_ELBC 38 #define CONFIG_P1020 39 #define CONFIG_VSC7385_ENET 40 #define CONFIG_SLIC 41 #define __SW_BOOT_MASK 0x03 42 #define __SW_BOOT_NOR 0x5c 43 #define __SW_BOOT_SPI 0x1c 44 #define __SW_BOOT_SD 0x9c 45 #define __SW_BOOT_NAND 0xec 46 #define __SW_BOOT_PCIE 0x6c 47 #define CONFIG_SYS_L2_SIZE (256 << 10) 48 #endif 49 50 /* 51 * P1020RDB-PD board has user selectable switches for evaluating different 52 * frequency and boot options for the P1020 device. The table that 53 * follow describe the available options. The front six binary number was in 54 * accordance with SW3[1:6]. 55 * 111101 533 533 267 667 NOR Core0 boot; Core1 hold-off 56 * 101101 667 667 333 667 NOR Core0 boot; Core1 hold-off 57 * 011001 800 800 400 667 NOR Core0 boot; Core1 hold-off 58 * 001001 800 800 400 667 SD/MMC Core0 boot; Core1 hold-off 59 * 001101 800 800 400 667 SPI Core0 boot; Core1 hold-off 60 * 010001 800 800 400 667 NAND Core0 boot; Core1 hold-off 61 * 011101 800 800 400 667 PCIe-2 Core0 boot; Core1 hold-off 62 */ 63 #if defined(CONFIG_P1020RDB_PD) 64 #define CONFIG_BOARDNAME "P1020RDB-PD" 65 #define CONFIG_NAND_FSL_ELBC 66 #define CONFIG_P1020 67 #define CONFIG_VSC7385_ENET 68 #define CONFIG_SLIC 69 #define __SW_BOOT_MASK 0x03 70 #define __SW_BOOT_NOR 0x64 71 #define __SW_BOOT_SPI 0x34 72 #define __SW_BOOT_SD 0x24 73 #define __SW_BOOT_NAND 0x44 74 #define __SW_BOOT_PCIE 0x74 75 #define CONFIG_SYS_L2_SIZE (256 << 10) 76 /* 77 * Dynamic MTD Partition support with mtdparts 78 */ 79 #define CONFIG_MTD_DEVICE 80 #define CONFIG_MTD_PARTITIONS 81 #define CONFIG_CMD_MTDPARTS 82 #define CONFIG_FLASH_CFI_MTD 83 #define MTDIDS_DEFAULT "nor0=ec000000.nor" 84 #define MTDPARTS_DEFAULT "mtdparts=ec000000.nor:128k(dtb),6016k(kernel)," \ 85 "57088k(fs),1m(vsc7385-firmware),1280k(u-boot)" 86 #endif 87 88 #if defined(CONFIG_P1021RDB) 89 #define CONFIG_BOARDNAME "P1021RDB-PC" 90 #define CONFIG_NAND_FSL_ELBC 91 #define CONFIG_P1021 92 #define CONFIG_QE 93 #define CONFIG_VSC7385_ENET 94 #define CONFIG_SYS_LBC_LBCR 0x00080000 /* Implement conversion of 95 addresses in the LBC */ 96 #define __SW_BOOT_MASK 0x03 97 #define __SW_BOOT_NOR 0x5c 98 #define __SW_BOOT_SPI 0x1c 99 #define __SW_BOOT_SD 0x9c 100 #define __SW_BOOT_NAND 0xec 101 #define __SW_BOOT_PCIE 0x6c 102 #define CONFIG_SYS_L2_SIZE (256 << 10) 103 /* 104 * Dynamic MTD Partition support with mtdparts 105 */ 106 #define CONFIG_MTD_DEVICE 107 #define CONFIG_MTD_PARTITIONS 108 #define CONFIG_CMD_MTDPARTS 109 #define CONFIG_FLASH_CFI_MTD 110 #ifdef CONFIG_PHYS_64BIT 111 #define MTDIDS_DEFAULT "nor0=fef000000.nor" 112 #define MTDPARTS_DEFAULT "mtdparts=fef000000.nor:256k(vsc7385-firmware)," \ 113 "256k(dtb),4608k(kernel),9728k(fs)," \ 114 "256k(qe-ucode-firmware),1280k(u-boot)" 115 #else 116 #define MTDIDS_DEFAULT "nor0=ef000000.nor" 117 #define MTDPARTS_DEFAULT "mtdparts=ef000000.nor:256k(vsc7385-firmware)," \ 118 "256k(dtb),4608k(kernel),9728k(fs)," \ 119 "256k(qe-ucode-firmware),1280k(u-boot)" 120 #endif 121 #endif 122 123 #if defined(CONFIG_P1024RDB) 124 #define CONFIG_BOARDNAME "P1024RDB" 125 #define CONFIG_NAND_FSL_ELBC 126 #define CONFIG_P1024 127 #define CONFIG_SLIC 128 #define __SW_BOOT_MASK 0xf3 129 #define __SW_BOOT_NOR 0x00 130 #define __SW_BOOT_SPI 0x08 131 #define __SW_BOOT_SD 0x04 132 #define __SW_BOOT_NAND 0x0c 133 #define CONFIG_SYS_L2_SIZE (256 << 10) 134 #endif 135 136 #if defined(CONFIG_P1025RDB) 137 #define CONFIG_BOARDNAME "P1025RDB" 138 #define CONFIG_NAND_FSL_ELBC 139 #define CONFIG_P1025 140 #define CONFIG_QE 141 #define CONFIG_SLIC 142 143 #define CONFIG_SYS_LBC_LBCR 0x00080000 /* Implement conversion of 144 addresses in the LBC */ 145 #define __SW_BOOT_MASK 0xf3 146 #define __SW_BOOT_NOR 0x00 147 #define __SW_BOOT_SPI 0x08 148 #define __SW_BOOT_SD 0x04 149 #define __SW_BOOT_NAND 0x0c 150 #define CONFIG_SYS_L2_SIZE (256 << 10) 151 #endif 152 153 #if defined(CONFIG_P2020RDB) 154 #define CONFIG_BOARDNAME "P2020RDB-PCA" 155 #define CONFIG_NAND_FSL_ELBC 156 #define CONFIG_P2020 157 #define CONFIG_VSC7385_ENET 158 #define __SW_BOOT_MASK 0x03 159 #define __SW_BOOT_NOR 0xc8 160 #define __SW_BOOT_SPI 0x28 161 #define __SW_BOOT_SD 0x68 /* or 0x18 */ 162 #define __SW_BOOT_NAND 0xe8 163 #define __SW_BOOT_PCIE 0xa8 164 #define CONFIG_SYS_L2_SIZE (512 << 10) 165 /* 166 * Dynamic MTD Partition support with mtdparts 167 */ 168 #define CONFIG_MTD_DEVICE 169 #define CONFIG_MTD_PARTITIONS 170 #define CONFIG_CMD_MTDPARTS 171 #define CONFIG_FLASH_CFI_MTD 172 #ifdef CONFIG_PHYS_64BIT 173 #define MTDIDS_DEFAULT "nor0=fef000000.nor" 174 #define MTDPARTS_DEFAULT "mtdparts=fef000000.nor:256k(vsc7385-firmware)," \ 175 "256k(dtb),4608k(kernel),9984k(fs),1280k(u-boot)" 176 #else 177 #define MTDIDS_DEFAULT "nor0=ef000000.nor" 178 #define MTDPARTS_DEFAULT "mtdparts=ef000000.nor:256k(vsc7385-firmware)," \ 179 "256k(dtb),4608k(kernel),9984k(fs),1280k(u-boot)" 180 #endif 181 #endif 182 183 #ifdef CONFIG_SDCARD 184 #define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT 185 #define CONFIG_SPL_SERIAL_SUPPORT 186 #define CONFIG_SPL_MMC_SUPPORT 187 #define CONFIG_SPL_MMC_MINIMAL 188 #define CONFIG_SPL_FLUSH_IMAGE 189 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 190 #define CONFIG_SPL_LIBGENERIC_SUPPORT 191 #define CONFIG_SPL_LIBCOMMON_SUPPORT 192 #define CONFIG_FSL_LAW /* Use common FSL init code */ 193 #define CONFIG_SYS_TEXT_BASE 0x11001000 194 #define CONFIG_SPL_TEXT_BASE 0xf8f81000 195 #define CONFIG_SPL_PAD_TO 0x20000 196 #define CONFIG_SPL_MAX_SIZE (128 * 1024) 197 #define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10) 198 #define CONFIG_SYS_MMC_U_BOOT_DST (0x11000000) 199 #define CONFIG_SYS_MMC_U_BOOT_START (0x11000000) 200 #define CONFIG_SYS_MMC_U_BOOT_OFFS (128 << 10) 201 #define CONFIG_SYS_MPC85XX_NO_RESETVEC 202 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds" 203 #define CONFIG_SPL_MMC_BOOT 204 #ifdef CONFIG_SPL_BUILD 205 #define CONFIG_SPL_COMMON_INIT_DDR 206 #endif 207 #endif 208 209 #ifdef CONFIG_SPIFLASH 210 #define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT 211 #define CONFIG_SPL_SERIAL_SUPPORT 212 #define CONFIG_SPL_SPI_SUPPORT 213 #define CONFIG_SPL_SPI_FLASH_SUPPORT 214 #define CONFIG_SPL_SPI_FLASH_MINIMAL 215 #define CONFIG_SPL_FLUSH_IMAGE 216 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 217 #define CONFIG_SPL_LIBGENERIC_SUPPORT 218 #define CONFIG_SPL_LIBCOMMON_SUPPORT 219 #define CONFIG_FSL_LAW /* Use common FSL init code */ 220 #define CONFIG_SYS_TEXT_BASE 0x11001000 221 #define CONFIG_SPL_TEXT_BASE 0xf8f81000 222 #define CONFIG_SPL_PAD_TO 0x20000 223 #define CONFIG_SPL_MAX_SIZE (128 * 1024) 224 #define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (768 << 10) 225 #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x11000000) 226 #define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x11000000) 227 #define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (128 << 10) 228 #define CONFIG_SYS_MPC85XX_NO_RESETVEC 229 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds" 230 #define CONFIG_SPL_SPI_BOOT 231 #ifdef CONFIG_SPL_BUILD 232 #define CONFIG_SPL_COMMON_INIT_DDR 233 #endif 234 #endif 235 236 #ifdef CONFIG_NAND 237 #ifdef CONFIG_TPL_BUILD 238 #define CONFIG_SPL_NAND_BOOT 239 #define CONFIG_SPL_FLUSH_IMAGE 240 #define CONFIG_SPL_NAND_INIT 241 #define CONFIG_TPL_SERIAL_SUPPORT 242 #define CONFIG_TPL_LIBGENERIC_SUPPORT 243 #define CONFIG_TPL_LIBCOMMON_SUPPORT 244 #define CONFIG_TPL_NAND_SUPPORT 245 #define CONFIG_TPL_MPC8XXX_INIT_DDR_SUPPORT 246 #define CONFIG_SPL_COMMON_INIT_DDR 247 #define CONFIG_SPL_MAX_SIZE (128 << 10) 248 #define CONFIG_SPL_TEXT_BASE 0xf8f81000 249 #define CONFIG_SYS_MPC85XX_NO_RESETVEC 250 #define CONFIG_SYS_NAND_U_BOOT_SIZE (832 << 10) 251 #define CONFIG_SYS_NAND_U_BOOT_DST (0x11000000) 252 #define CONFIG_SYS_NAND_U_BOOT_START (0x11000000) 253 #define CONFIG_SYS_NAND_U_BOOT_OFFS ((128 + 128) << 10) 254 #elif defined(CONFIG_SPL_BUILD) 255 #define CONFIG_SPL_INIT_MINIMAL 256 #define CONFIG_SPL_SERIAL_SUPPORT 257 #define CONFIG_SPL_NAND_SUPPORT 258 #define CONFIG_SPL_FLUSH_IMAGE 259 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 260 #define CONFIG_SPL_TEXT_BASE 0xff800000 261 #define CONFIG_SPL_MAX_SIZE 4096 262 #define CONFIG_SYS_NAND_U_BOOT_SIZE (128 << 10) 263 #define CONFIG_SYS_NAND_U_BOOT_DST 0xf8f80000 264 #define CONFIG_SYS_NAND_U_BOOT_START 0xf8f80000 265 #define CONFIG_SYS_NAND_U_BOOT_OFFS (128 << 10) 266 #endif /* not CONFIG_TPL_BUILD */ 267 268 #define CONFIG_SPL_PAD_TO 0x20000 269 #define CONFIG_TPL_PAD_TO 0x20000 270 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 271 #define CONFIG_SYS_TEXT_BASE 0x11001000 272 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds" 273 #endif 274 275 #ifndef CONFIG_SYS_TEXT_BASE 276 #define CONFIG_SYS_TEXT_BASE 0xeff40000 277 #endif 278 279 #ifndef CONFIG_RESET_VECTOR_ADDRESS 280 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc 281 #endif 282 283 #ifndef CONFIG_SYS_MONITOR_BASE 284 #ifdef CONFIG_SPL_BUILD 285 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE 286 #else 287 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 288 #endif 289 #endif 290 291 /* High Level Configuration Options */ 292 #define CONFIG_BOOKE 293 #define CONFIG_E500 294 295 #define CONFIG_MP 296 297 #define CONFIG_FSL_ELBC 298 #define CONFIG_PCI 299 #define CONFIG_PCIE1 /* PCIE controller 1 (slot 1) */ 300 #define CONFIG_PCIE2 /* PCIE controller 2 (slot 2) */ 301 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ 302 #define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */ 303 #define CONFIG_FSL_PCIE_RESET /* need PCIe reset errata */ 304 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ 305 306 #define CONFIG_FSL_LAW 307 #define CONFIG_TSEC_ENET /* tsec ethernet support */ 308 #define CONFIG_ENV_OVERWRITE 309 310 #define CONFIG_CMD_SATA 311 #define CONFIG_SATA_SIL 312 #define CONFIG_SYS_SATA_MAX_DEVICE 2 313 #define CONFIG_LIBATA 314 #define CONFIG_LBA48 315 316 #if defined(CONFIG_P2020RDB) 317 #define CONFIG_SYS_CLK_FREQ 100000000 318 #else 319 #define CONFIG_SYS_CLK_FREQ 66666666 320 #endif 321 #define CONFIG_DDR_CLK_FREQ 66666666 322 323 #define CONFIG_HWCONFIG 324 /* 325 * These can be toggled for performance analysis, otherwise use default. 326 */ 327 #define CONFIG_L2_CACHE 328 #define CONFIG_BTB 329 330 #define CONFIG_BOARD_EARLY_INIT_F /* Call board_pre_init */ 331 332 #define CONFIG_ENABLE_36BIT_PHYS 333 334 #ifdef CONFIG_PHYS_64BIT 335 #define CONFIG_ADDR_MAP 1 336 #define CONFIG_SYS_NUM_ADDR_MAP 16 /* number of TLB1 entries */ 337 #endif 338 339 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ 340 #define CONFIG_SYS_MEMTEST_END 0x1fffffff 341 #define CONFIG_PANIC_HANG /* do not reset board on panic */ 342 343 #define CONFIG_SYS_CCSRBAR 0xffe00000 344 #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR 345 346 /* IN case of NAND bootloader relocate CCSRBAR in RAMboot code not in the 4k 347 SPL code*/ 348 #ifdef CONFIG_SPL_BUILD 349 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE 350 #endif 351 352 /* DDR Setup */ 353 #define CONFIG_SYS_FSL_DDR3 354 #define CONFIG_SYS_DDR_RAW_TIMING 355 #define CONFIG_DDR_SPD 356 #define CONFIG_SYS_SPD_BUS_NUM 1 357 #define SPD_EEPROM_ADDRESS 0x52 358 #undef CONFIG_FSL_DDR_INTERACTIVE 359 360 #if (defined(CONFIG_P1020MBG) || defined(CONFIG_P1020RDB_PD)) 361 #define CONFIG_SYS_SDRAM_SIZE_LAW LAW_SIZE_2G 362 #define CONFIG_CHIP_SELECTS_PER_CTRL 2 363 #else 364 #define CONFIG_SYS_SDRAM_SIZE_LAW LAW_SIZE_1G 365 #define CONFIG_CHIP_SELECTS_PER_CTRL 1 366 #endif 367 #define CONFIG_SYS_SDRAM_SIZE (1u << (CONFIG_SYS_SDRAM_SIZE_LAW - 19)) 368 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 369 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 370 371 #define CONFIG_NUM_DDR_CONTROLLERS 1 372 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 373 374 /* Default settings for DDR3 */ 375 #ifndef CONFIG_P2020RDB 376 #define CONFIG_SYS_DDR_CS0_BNDS 0x0000003f 377 #define CONFIG_SYS_DDR_CS0_CONFIG 0x80014302 378 #define CONFIG_SYS_DDR_CS0_CONFIG_2 0x00000000 379 #define CONFIG_SYS_DDR_CS1_BNDS 0x0040007f 380 #define CONFIG_SYS_DDR_CS1_CONFIG 0x80014302 381 #define CONFIG_SYS_DDR_CS1_CONFIG_2 0x00000000 382 383 #define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef 384 #define CONFIG_SYS_DDR_INIT_ADDR 0x00000000 385 #define CONFIG_SYS_DDR_INIT_EXT_ADDR 0x00000000 386 #define CONFIG_SYS_DDR_MODE_CONTROL 0x00000000 387 388 #define CONFIG_SYS_DDR_ZQ_CONTROL 0x89080600 389 #define CONFIG_SYS_DDR_WRLVL_CONTROL 0x8655A608 390 #define CONFIG_SYS_DDR_SR_CNTR 0x00000000 391 #define CONFIG_SYS_DDR_RCW_1 0x00000000 392 #define CONFIG_SYS_DDR_RCW_2 0x00000000 393 #define CONFIG_SYS_DDR_CONTROL 0xC70C0000 /* Type = DDR3 */ 394 #define CONFIG_SYS_DDR_CONTROL_2 0x04401050 395 #define CONFIG_SYS_DDR_TIMING_4 0x00220001 396 #define CONFIG_SYS_DDR_TIMING_5 0x03402400 397 398 #define CONFIG_SYS_DDR_TIMING_3 0x00020000 399 #define CONFIG_SYS_DDR_TIMING_0 0x00330004 400 #define CONFIG_SYS_DDR_TIMING_1 0x6f6B4846 401 #define CONFIG_SYS_DDR_TIMING_2 0x0FA8C8CF 402 #define CONFIG_SYS_DDR_CLK_CTRL 0x03000000 403 #define CONFIG_SYS_DDR_MODE_1 0x40461520 404 #define CONFIG_SYS_DDR_MODE_2 0x8000c000 405 #define CONFIG_SYS_DDR_INTERVAL 0x0C300000 406 #endif 407 408 #undef CONFIG_CLOCKS_IN_MHZ 409 410 /* 411 * Memory map 412 * 413 * 0x0000_0000 0x7fff_ffff DDR Up to 2GB cacheable 414 * 0x8000_0000 0xdfff_ffff PCI Express Mem 1.5G non-cacheable(PCIe * 3) 415 * 0xec00_0000 0xefff_ffff NOR flash Up to 64M non-cacheable CS0/1 416 * 0xf8f8_0000 0xf8ff_ffff L2 SRAM Up to 512K cacheable 417 * (early boot only) 418 * 0xff80_0000 0xff80_7fff NAND flash 32K non-cacheable CS1/0 419 * 0xff98_0000 0xff98_ffff PMC 64K non-cacheable CS2 420 * 0xffa0_0000 0xffaf_ffff CPLD 1M non-cacheable CS3 421 * 0xffb0_0000 0xffbf_ffff VSC7385 switch 1M non-cacheable CS2 422 * 0xffc0_0000 0xffc3_ffff PCI IO range 256k non-cacheable 423 * 0xffd0_0000 0xffd0_3fff L1 for stack 16K cacheable 424 * 0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable 425 */ 426 427 /* 428 * Local Bus Definitions 429 */ 430 #if (defined(CONFIG_P1020MBG) || defined(CONFIG_P1020RDB_PD)) 431 #define CONFIG_SYS_MAX_FLASH_SECT 512 /* 64M */ 432 #define CONFIG_SYS_FLASH_BASE 0xec000000 433 #elif defined(CONFIG_P1020UTM) 434 #define CONFIG_SYS_MAX_FLASH_SECT 256 /* 32M */ 435 #define CONFIG_SYS_FLASH_BASE 0xee000000 436 #else 437 #define CONFIG_SYS_MAX_FLASH_SECT 128 /* 16M */ 438 #define CONFIG_SYS_FLASH_BASE 0xef000000 439 #endif 440 441 #ifdef CONFIG_PHYS_64BIT 442 #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE) 443 #else 444 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE 445 #endif 446 447 #define CONFIG_FLASH_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) \ 448 | BR_PS_16 | BR_V) 449 450 #define CONFIG_FLASH_OR_PRELIM 0xfc000ff7 451 452 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS} 453 #define CONFIG_SYS_FLASH_QUIET_TEST 454 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 455 456 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ 457 458 #undef CONFIG_SYS_FLASH_CHECKSUM 459 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 460 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 461 462 #define CONFIG_FLASH_CFI_DRIVER 463 #define CONFIG_SYS_FLASH_CFI 464 #define CONFIG_SYS_FLASH_EMPTY_INFO 465 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 466 467 /* Nand Flash */ 468 #ifdef CONFIG_NAND_FSL_ELBC 469 #define CONFIG_SYS_NAND_BASE 0xff800000 470 #ifdef CONFIG_PHYS_64BIT 471 #define CONFIG_SYS_NAND_BASE_PHYS 0xfff800000ull 472 #else 473 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE 474 #endif 475 476 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } 477 #define CONFIG_SYS_MAX_NAND_DEVICE 1 478 #define CONFIG_CMD_NAND 479 #if defined(CONFIG_P1020RDB_PD) 480 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) 481 #else 482 #define CONFIG_SYS_NAND_BLOCK_SIZE (16 * 1024) 483 #endif 484 485 #define CONFIG_SYS_NAND_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 486 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ 487 | BR_PS_8 /* Port Size = 8 bit */ \ 488 | BR_MS_FCM /* MSEL = FCM */ \ 489 | BR_V) /* valid */ 490 #if defined(CONFIG_P1020RDB_PD) 491 #define CONFIG_SYS_NAND_OR_PRELIM (OR_AM_32KB \ 492 | OR_FCM_PGS /* Large Page*/ \ 493 | OR_FCM_CSCT \ 494 | OR_FCM_CST \ 495 | OR_FCM_CHT \ 496 | OR_FCM_SCY_1 \ 497 | OR_FCM_TRLX \ 498 | OR_FCM_EHTR) 499 #else 500 #define CONFIG_SYS_NAND_OR_PRELIM (OR_AM_32KB /* small page */ \ 501 | OR_FCM_CSCT \ 502 | OR_FCM_CST \ 503 | OR_FCM_CHT \ 504 | OR_FCM_SCY_1 \ 505 | OR_FCM_TRLX \ 506 | OR_FCM_EHTR) 507 #endif 508 #endif /* CONFIG_NAND_FSL_ELBC */ 509 510 #define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */ 511 512 #define CONFIG_SYS_INIT_RAM_LOCK 513 #define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* stack in RAM */ 514 #ifdef CONFIG_PHYS_64BIT 515 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf 516 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR 517 /* The assembler doesn't like typecast */ 518 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \ 519 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \ 520 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) 521 #else 522 /* Initial L1 address */ 523 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS CONFIG_SYS_INIT_RAM_ADDR 524 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0 525 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS 526 #endif 527 /* Size of used area in RAM */ 528 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 529 530 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ 531 GENERATED_GBL_DATA_SIZE) 532 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 533 534 #define CONFIG_SYS_MONITOR_LEN (768 * 1024) 535 #define CONFIG_SYS_MALLOC_LEN (1024 * 1024)/* Reserved for malloc */ 536 537 #define CONFIG_SYS_CPLD_BASE 0xffa00000 538 #ifdef CONFIG_PHYS_64BIT 539 #define CONFIG_SYS_CPLD_BASE_PHYS 0xfffa00000ull 540 #else 541 #define CONFIG_SYS_CPLD_BASE_PHYS CONFIG_SYS_CPLD_BASE 542 #endif 543 /* CPLD config size: 1Mb */ 544 #define CONFIG_CPLD_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE_PHYS) | \ 545 BR_PS_8 | BR_V) 546 #define CONFIG_CPLD_OR_PRELIM (0xfff009f7) 547 548 #define CONFIG_SYS_PMC_BASE 0xff980000 549 #define CONFIG_SYS_PMC_BASE_PHYS CONFIG_SYS_PMC_BASE 550 #define CONFIG_PMC_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_PMC_BASE_PHYS) | \ 551 BR_PS_8 | BR_V) 552 #define CONFIG_PMC_OR_PRELIM (OR_AM_64KB | OR_GPCM_CSNT | OR_GPCM_XACS | \ 553 OR_GPCM_SCY | OR_GPCM_TRLX | OR_GPCM_EHTR | \ 554 OR_GPCM_EAD) 555 556 #ifdef CONFIG_NAND 557 #define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Addr */ 558 #define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */ 559 #define CONFIG_SYS_BR1_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */ 560 #define CONFIG_SYS_OR1_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */ 561 #else 562 #define CONFIG_SYS_BR0_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */ 563 #define CONFIG_SYS_OR0_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */ 564 #ifdef CONFIG_NAND_FSL_ELBC 565 #define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Addr */ 566 #define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */ 567 #endif 568 #endif 569 #define CONFIG_SYS_BR3_PRELIM CONFIG_CPLD_BR_PRELIM /* CPLD Base Address */ 570 #define CONFIG_SYS_OR3_PRELIM CONFIG_CPLD_OR_PRELIM /* CPLD Options */ 571 572 /* Vsc7385 switch */ 573 #ifdef CONFIG_VSC7385_ENET 574 #define CONFIG_SYS_VSC7385_BASE 0xffb00000 575 576 #ifdef CONFIG_PHYS_64BIT 577 #define CONFIG_SYS_VSC7385_BASE_PHYS 0xfffb00000ull 578 #else 579 #define CONFIG_SYS_VSC7385_BASE_PHYS CONFIG_SYS_VSC7385_BASE 580 #endif 581 582 #define CONFIG_SYS_VSC7385_BR_PRELIM \ 583 (BR_PHYS_ADDR(CONFIG_SYS_VSC7385_BASE_PHYS) | BR_PS_8 | BR_V) 584 #define CONFIG_SYS_VSC7385_OR_PRELIM (OR_AM_128KB | OR_GPCM_CSNT | \ 585 OR_GPCM_XACS | OR_GPCM_SCY_15 | OR_GPCM_SETA | \ 586 OR_GPCM_TRLX | OR_GPCM_EHTR | OR_GPCM_EAD) 587 588 #define CONFIG_SYS_BR2_PRELIM CONFIG_SYS_VSC7385_BR_PRELIM 589 #define CONFIG_SYS_OR2_PRELIM CONFIG_SYS_VSC7385_OR_PRELIM 590 591 /* The size of the VSC7385 firmware image */ 592 #define CONFIG_VSC7385_IMAGE_SIZE 8192 593 #endif 594 595 /* 596 * Config the L2 Cache as L2 SRAM 597 */ 598 #if defined(CONFIG_SPL_BUILD) 599 #if defined(CONFIG_SDCARD) || defined(CONFIG_SPIFLASH) 600 #define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000 601 #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR 602 #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) 603 #define CONFIG_SPL_RELOC_TEXT_BASE 0xf8f81000 604 #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L2_ADDR + 112 * 1024) 605 #define CONFIG_SPL_RELOC_STACK (CONFIG_SYS_INIT_L2_ADDR + 116 * 1024) 606 #define CONFIG_SPL_RELOC_STACK_SIZE (32 << 10) 607 #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SYS_INIT_L2_ADDR + 148 * 1024) 608 #if defined(CONFIG_P2020RDB) 609 #define CONFIG_SPL_RELOC_MALLOC_SIZE (364 << 10) 610 #else 611 #define CONFIG_SPL_RELOC_MALLOC_SIZE (108 << 10) 612 #endif 613 #elif defined(CONFIG_NAND) 614 #ifdef CONFIG_TPL_BUILD 615 #define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000 616 #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR 617 #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) 618 #define CONFIG_SPL_RELOC_TEXT_BASE 0xf8f81000 619 #define CONFIG_SPL_RELOC_STACK (CONFIG_SYS_INIT_L2_ADDR + 192 * 1024) 620 #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SYS_INIT_L2_ADDR + 208 * 1024) 621 #define CONFIG_SPL_RELOC_MALLOC_SIZE (48 << 10) 622 #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L2_ADDR + 176 * 1024) 623 #else 624 #define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000 625 #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR 626 #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) 627 #define CONFIG_SPL_RELOC_TEXT_BASE (CONFIG_SYS_INIT_L2_END - 0x2000) 628 #define CONFIG_SPL_RELOC_STACK ((CONFIG_SYS_INIT_L2_END - 1) & ~0xF) 629 #endif /* CONFIG_TPL_BUILD */ 630 #endif 631 #endif 632 633 /* Serial Port - controlled on board with jumper J8 634 * open - index 2 635 * shorted - index 1 636 */ 637 #define CONFIG_CONS_INDEX 1 638 #undef CONFIG_SERIAL_SOFTWARE_FIFO 639 #define CONFIG_SYS_NS16550_SERIAL 640 #define CONFIG_SYS_NS16550_REG_SIZE 1 641 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) 642 #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_INIT_MINIMAL) 643 #define CONFIG_NS16550_MIN_FUNCTIONS 644 #endif 645 646 #define CONFIG_SYS_BAUDRATE_TABLE \ 647 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} 648 649 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) 650 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) 651 652 /* I2C */ 653 #define CONFIG_SYS_I2C 654 #define CONFIG_SYS_I2C_FSL 655 #define CONFIG_SYS_FSL_I2C_SPEED 400000 656 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 657 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 658 #define CONFIG_SYS_FSL_I2C2_SPEED 400000 659 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F 660 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100 661 #define CONFIG_SYS_I2C_NOPROBES { {0, 0x29} } 662 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x52 663 #define CONFIG_SYS_SPD_BUS_NUM 1 /* For rom_loc and flash bank */ 664 665 /* 666 * I2C2 EEPROM 667 */ 668 #undef CONFIG_ID_EEPROM 669 670 #define CONFIG_RTC_PT7C4338 671 #define CONFIG_SYS_I2C_RTC_ADDR 0x68 672 #define CONFIG_SYS_I2C_PCA9557_ADDR 0x18 673 674 /* enable read and write access to EEPROM */ 675 #define CONFIG_CMD_EEPROM 676 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 677 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 678 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 679 680 /* 681 * eSPI - Enhanced SPI 682 */ 683 #define CONFIG_HARD_SPI 684 685 #if defined(CONFIG_SPI_FLASH) 686 #define CONFIG_SF_DEFAULT_SPEED 10000000 687 #define CONFIG_SF_DEFAULT_MODE 0 688 #endif 689 690 #if defined(CONFIG_PCI) 691 /* 692 * General PCI 693 * Memory space is mapped 1-1, but I/O space must start from 0. 694 */ 695 696 /* controller 2, direct to uli, tgtid 2, Base address 9000 */ 697 #define CONFIG_SYS_PCIE2_NAME "PCIe SLOT" 698 #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000 699 #ifdef CONFIG_PHYS_64BIT 700 #define CONFIG_SYS_PCIE2_MEM_BUS 0xc0000000 701 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull 702 #else 703 #define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000 704 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000 705 #endif 706 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */ 707 #define CONFIG_SYS_PCIE2_IO_VIRT 0xffc10000 708 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 709 #ifdef CONFIG_PHYS_64BIT 710 #define CONFIG_SYS_PCIE2_IO_PHYS 0xfffc10000ull 711 #else 712 #define CONFIG_SYS_PCIE2_IO_PHYS 0xffc10000 713 #endif 714 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ 715 716 /* controller 1, Slot 2, tgtid 1, Base address a000 */ 717 #define CONFIG_SYS_PCIE1_NAME "mini PCIe SLOT" 718 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 719 #ifdef CONFIG_PHYS_64BIT 720 #define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000 721 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull 722 #else 723 #define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000 724 #define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000 725 #endif 726 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ 727 #define CONFIG_SYS_PCIE1_IO_VIRT 0xffc00000 728 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 729 #ifdef CONFIG_PHYS_64BIT 730 #define CONFIG_SYS_PCIE1_IO_PHYS 0xfffc00000ull 731 #else 732 #define CONFIG_SYS_PCIE1_IO_PHYS 0xffc00000 733 #endif 734 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ 735 736 #define CONFIG_PCI_PNP /* do pci plug-and-play */ 737 #define CONFIG_CMD_PCI 738 739 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 740 #define CONFIG_DOS_PARTITION 741 #endif /* CONFIG_PCI */ 742 743 #if defined(CONFIG_TSEC_ENET) 744 #define CONFIG_MII /* MII PHY management */ 745 #define CONFIG_TSEC1 746 #define CONFIG_TSEC1_NAME "eTSEC1" 747 #define CONFIG_TSEC2 748 #define CONFIG_TSEC2_NAME "eTSEC2" 749 #define CONFIG_TSEC3 750 #define CONFIG_TSEC3_NAME "eTSEC3" 751 752 #define TSEC1_PHY_ADDR 2 753 #define TSEC2_PHY_ADDR 0 754 #define TSEC3_PHY_ADDR 1 755 756 #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 757 #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 758 #define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 759 760 #define TSEC1_PHYIDX 0 761 #define TSEC2_PHYIDX 0 762 #define TSEC3_PHYIDX 0 763 764 #define CONFIG_ETHPRIME "eTSEC1" 765 766 #define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */ 767 768 #define CONFIG_HAS_ETH0 769 #define CONFIG_HAS_ETH1 770 #define CONFIG_HAS_ETH2 771 #endif /* CONFIG_TSEC_ENET */ 772 773 #ifdef CONFIG_QE 774 /* QE microcode/firmware address */ 775 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR 776 #define CONFIG_SYS_QE_FW_ADDR 0xefec0000 777 #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 778 #endif /* CONFIG_QE */ 779 780 #ifdef CONFIG_P1025RDB 781 /* 782 * QE UEC ethernet configuration 783 */ 784 #define CONFIG_MIIM_ADDRESS (CONFIG_SYS_CCSRBAR + 0x82120) 785 786 #undef CONFIG_UEC_ETH 787 #define CONFIG_PHY_MODE_NEED_CHANGE 788 789 #define CONFIG_UEC_ETH1 /* ETH1 */ 790 #define CONFIG_HAS_ETH0 791 792 #ifdef CONFIG_UEC_ETH1 793 #define CONFIG_SYS_UEC1_UCC_NUM 0 /* UCC1 */ 794 #define CONFIG_SYS_UEC1_RX_CLK QE_CLK12 /* CLK12 for MII */ 795 #define CONFIG_SYS_UEC1_TX_CLK QE_CLK9 /* CLK9 for MII */ 796 #define CONFIG_SYS_UEC1_ETH_TYPE FAST_ETH 797 #define CONFIG_SYS_UEC1_PHY_ADDR 0x0 /* 0x0 for MII */ 798 #define CONFIG_SYS_UEC1_INTERFACE_TYPE PHY_INTERFACE_MODE_RMII 799 #define CONFIG_SYS_UEC1_INTERFACE_SPEED 100 800 #endif /* CONFIG_UEC_ETH1 */ 801 802 #define CONFIG_UEC_ETH5 /* ETH5 */ 803 #define CONFIG_HAS_ETH1 804 805 #ifdef CONFIG_UEC_ETH5 806 #define CONFIG_SYS_UEC5_UCC_NUM 4 /* UCC5 */ 807 #define CONFIG_SYS_UEC5_RX_CLK QE_CLK_NONE 808 #define CONFIG_SYS_UEC5_TX_CLK QE_CLK13 /* CLK 13 for RMII */ 809 #define CONFIG_SYS_UEC5_ETH_TYPE FAST_ETH 810 #define CONFIG_SYS_UEC5_PHY_ADDR 0x3 /* 0x3 for RMII */ 811 #define CONFIG_SYS_UEC5_INTERFACE_TYPE PHY_INTERFACE_MODE_RMII 812 #define CONFIG_SYS_UEC5_INTERFACE_SPEED 100 813 #endif /* CONFIG_UEC_ETH5 */ 814 #endif /* CONFIG_P1025RDB */ 815 816 /* 817 * Environment 818 */ 819 #ifdef CONFIG_SPIFLASH 820 #define CONFIG_ENV_IS_IN_SPI_FLASH 821 #define CONFIG_ENV_SPI_BUS 0 822 #define CONFIG_ENV_SPI_CS 0 823 #define CONFIG_ENV_SPI_MAX_HZ 10000000 824 #define CONFIG_ENV_SPI_MODE 0 825 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */ 826 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ 827 #define CONFIG_ENV_SECT_SIZE 0x10000 828 #elif defined(CONFIG_SDCARD) 829 #define CONFIG_ENV_IS_IN_MMC 830 #define CONFIG_FSL_FIXED_MMC_LOCATION 831 #define CONFIG_ENV_SIZE 0x2000 832 #define CONFIG_SYS_MMC_ENV_DEV 0 833 #elif defined(CONFIG_NAND) 834 #ifdef CONFIG_TPL_BUILD 835 #define CONFIG_ENV_SIZE 0x2000 836 #define CONFIG_ENV_ADDR (CONFIG_SYS_INIT_L2_ADDR + (160 << 10)) 837 #else 838 #define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE 839 #endif 840 #define CONFIG_ENV_IS_IN_NAND 841 #define CONFIG_ENV_OFFSET (1024 * 1024) 842 #define CONFIG_ENV_RANGE (3 * CONFIG_ENV_SIZE) 843 #elif defined(CONFIG_SYS_RAMBOOT) 844 #define CONFIG_ENV_IS_NOWHERE /* Store ENV in memory only */ 845 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) 846 #define CONFIG_ENV_SIZE 0x2000 847 #else 848 #define CONFIG_ENV_IS_IN_FLASH 849 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) 850 #define CONFIG_ENV_SIZE 0x2000 851 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ 852 #endif 853 854 #define CONFIG_LOADS_ECHO /* echo on for serial download */ 855 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ 856 857 /* 858 * Command line configuration. 859 */ 860 #define CONFIG_CMD_IRQ 861 #define CONFIG_CMD_DATE 862 #define CONFIG_CMD_REGINFO 863 864 /* 865 * USB 866 */ 867 #define CONFIG_HAS_FSL_DR_USB 868 869 #if defined(CONFIG_HAS_FSL_DR_USB) 870 #define CONFIG_USB_EHCI 871 872 #ifdef CONFIG_USB_EHCI 873 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 874 #define CONFIG_USB_EHCI_FSL 875 #endif 876 #endif 877 878 #if defined(CONFIG_P1020RDB_PD) 879 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1 880 #endif 881 882 #define CONFIG_MMC 883 884 #ifdef CONFIG_MMC 885 #define CONFIG_FSL_ESDHC 886 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR 887 #define CONFIG_GENERIC_MMC 888 #endif 889 890 #if defined(CONFIG_MMC) || defined(CONFIG_USB_EHCI) \ 891 || defined(CONFIG_FSL_SATA) 892 #define CONFIG_DOS_PARTITION 893 #endif 894 895 #undef CONFIG_WATCHDOG /* watchdog disabled */ 896 897 /* 898 * Miscellaneous configurable options 899 */ 900 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 901 #define CONFIG_CMDLINE_EDITING /* Command-line editing */ 902 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 903 #if defined(CONFIG_CMD_KGDB) 904 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 905 #else 906 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 907 #endif 908 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) 909 /* Print Buffer Size */ 910 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 911 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */ 912 913 /* 914 * For booting Linux, the board info and command line data 915 * have to be in the first 64 MB of memory, since this is 916 * the maximum mapped by the Linux kernel during initialization. 917 */ 918 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory for Linux*/ 919 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 920 921 #if defined(CONFIG_CMD_KGDB) 922 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 923 #endif 924 925 /* 926 * Environment Configuration 927 */ 928 #define CONFIG_HOSTNAME unknown 929 #define CONFIG_ROOTPATH "/opt/nfsroot" 930 #define CONFIG_BOOTFILE "uImage" 931 #define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */ 932 933 /* default location for tftp and bootm */ 934 #define CONFIG_LOADADDR 1000000 935 936 #define CONFIG_BOOTARGS /* the boot command will set bootargs */ 937 938 #define CONFIG_BAUDRATE 115200 939 940 #ifdef __SW_BOOT_NOR 941 #define __NOR_RST_CMD \ 942 norboot=i2c dev 1; i2c mw 18 1 __SW_BOOT_NOR 1; \ 943 i2c mw 18 3 __SW_BOOT_MASK 1; reset 944 #endif 945 #ifdef __SW_BOOT_SPI 946 #define __SPI_RST_CMD \ 947 spiboot=i2c dev 1; i2c mw 18 1 __SW_BOOT_SPI 1; \ 948 i2c mw 18 3 __SW_BOOT_MASK 1; reset 949 #endif 950 #ifdef __SW_BOOT_SD 951 #define __SD_RST_CMD \ 952 sdboot=i2c dev 1; i2c mw 18 1 __SW_BOOT_SD 1; \ 953 i2c mw 18 3 __SW_BOOT_MASK 1; reset 954 #endif 955 #ifdef __SW_BOOT_NAND 956 #define __NAND_RST_CMD \ 957 nandboot=i2c dev 1; i2c mw 18 1 __SW_BOOT_NAND 1; \ 958 i2c mw 18 3 __SW_BOOT_MASK 1; reset 959 #endif 960 #ifdef __SW_BOOT_PCIE 961 #define __PCIE_RST_CMD \ 962 pciboot=i2c dev 1; i2c mw 18 1 __SW_BOOT_PCIE 1; \ 963 i2c mw 18 3 __SW_BOOT_MASK 1; reset 964 #endif 965 966 #define CONFIG_EXTRA_ENV_SETTINGS \ 967 "netdev=eth0\0" \ 968 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ 969 "loadaddr=1000000\0" \ 970 "bootfile=uImage\0" \ 971 "tftpflash=tftpboot $loadaddr $uboot; " \ 972 "protect off " __stringify(CONFIG_SYS_TEXT_BASE) " +$filesize; " \ 973 "erase " __stringify(CONFIG_SYS_TEXT_BASE) " +$filesize; " \ 974 "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) " $filesize; " \ 975 "protect on " __stringify(CONFIG_SYS_TEXT_BASE) " +$filesize; " \ 976 "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) " $filesize\0" \ 977 "hwconfig=usb1:dr_mode=host,phy_type=ulpi\0" \ 978 "consoledev=ttyS0\0" \ 979 "ramdiskaddr=2000000\0" \ 980 "ramdiskfile=rootfs.ext2.gz.uboot\0" \ 981 "fdtaddr=1e00000\0" \ 982 "bdev=sda1\0" \ 983 "jffs2nor=mtdblock3\0" \ 984 "norbootaddr=ef080000\0" \ 985 "norfdtaddr=ef040000\0" \ 986 "jffs2nand=mtdblock9\0" \ 987 "nandbootaddr=100000\0" \ 988 "nandfdtaddr=80000\0" \ 989 "ramdisk_size=120000\0" \ 990 "map_lowernorbank=i2c dev 1; i2c mw 18 1 02 1; i2c mw 18 3 fd 1\0" \ 991 "map_uppernorbank=i2c dev 1; i2c mw 18 1 00 1; i2c mw 18 3 fd 1\0" \ 992 __stringify(__NOR_RST_CMD)"\0" \ 993 __stringify(__SPI_RST_CMD)"\0" \ 994 __stringify(__SD_RST_CMD)"\0" \ 995 __stringify(__NAND_RST_CMD)"\0" \ 996 __stringify(__PCIE_RST_CMD)"\0" 997 998 #define CONFIG_NFSBOOTCOMMAND \ 999 "setenv bootargs root=/dev/nfs rw " \ 1000 "nfsroot=$serverip:$rootpath " \ 1001 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 1002 "console=$consoledev,$baudrate $othbootargs;" \ 1003 "tftp $loadaddr $bootfile;" \ 1004 "tftp $fdtaddr $fdtfile;" \ 1005 "bootm $loadaddr - $fdtaddr" 1006 1007 #define CONFIG_HDBOOT \ 1008 "setenv bootargs root=/dev/$bdev rw rootdelay=30 " \ 1009 "console=$consoledev,$baudrate $othbootargs;" \ 1010 "usb start;" \ 1011 "ext2load usb 0:1 $loadaddr /boot/$bootfile;" \ 1012 "ext2load usb 0:1 $fdtaddr /boot/$fdtfile;" \ 1013 "bootm $loadaddr - $fdtaddr" 1014 1015 #define CONFIG_USB_FAT_BOOT \ 1016 "setenv bootargs root=/dev/ram rw " \ 1017 "console=$consoledev,$baudrate $othbootargs " \ 1018 "ramdisk_size=$ramdisk_size;" \ 1019 "usb start;" \ 1020 "fatload usb 0:2 $loadaddr $bootfile;" \ 1021 "fatload usb 0:2 $fdtaddr $fdtfile;" \ 1022 "fatload usb 0:2 $ramdiskaddr $ramdiskfile;" \ 1023 "bootm $loadaddr $ramdiskaddr $fdtaddr" 1024 1025 #define CONFIG_USB_EXT2_BOOT \ 1026 "setenv bootargs root=/dev/ram rw " \ 1027 "console=$consoledev,$baudrate $othbootargs " \ 1028 "ramdisk_size=$ramdisk_size;" \ 1029 "usb start;" \ 1030 "ext2load usb 0:4 $loadaddr $bootfile;" \ 1031 "ext2load usb 0:4 $fdtaddr $fdtfile;" \ 1032 "ext2load usb 0:4 $ramdiskaddr $ramdiskfile;" \ 1033 "bootm $loadaddr $ramdiskaddr $fdtaddr" 1034 1035 #define CONFIG_NORBOOT \ 1036 "setenv bootargs root=/dev/$jffs2nor rw " \ 1037 "console=$consoledev,$baudrate rootfstype=jffs2 $othbootargs;" \ 1038 "bootm $norbootaddr - $norfdtaddr" 1039 1040 #define CONFIG_RAMBOOTCOMMAND \ 1041 "setenv bootargs root=/dev/ram rw " \ 1042 "console=$consoledev,$baudrate $othbootargs " \ 1043 "ramdisk_size=$ramdisk_size;" \ 1044 "tftp $ramdiskaddr $ramdiskfile;" \ 1045 "tftp $loadaddr $bootfile;" \ 1046 "tftp $fdtaddr $fdtfile;" \ 1047 "bootm $loadaddr $ramdiskaddr $fdtaddr" 1048 1049 #define CONFIG_BOOTCOMMAND CONFIG_HDBOOT 1050 1051 #endif /* __CONFIG_H */ 1052