1 /* 2 * Copyright 2010-2011 Freescale Semiconductor, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 /* 8 * QorIQ RDB boards configuration file 9 */ 10 #ifndef __CONFIG_H 11 #define __CONFIG_H 12 13 #define CONFIG_DISPLAY_BOARDINFO 14 15 #if defined(CONFIG_P1020MBG) 16 #define CONFIG_BOARDNAME "P1020MBG-PC" 17 #define CONFIG_P1020 18 #define CONFIG_VSC7385_ENET 19 #define CONFIG_SLIC 20 #define __SW_BOOT_MASK 0x03 21 #define __SW_BOOT_NOR 0xe4 22 #define __SW_BOOT_SD 0x54 23 #define CONFIG_SYS_L2_SIZE (256 << 10) 24 #endif 25 26 #if defined(CONFIG_P1020UTM) 27 #define CONFIG_BOARDNAME "P1020UTM-PC" 28 #define CONFIG_P1020 29 #define __SW_BOOT_MASK 0x03 30 #define __SW_BOOT_NOR 0xe0 31 #define __SW_BOOT_SD 0x50 32 #define CONFIG_SYS_L2_SIZE (256 << 10) 33 #endif 34 35 #if defined(CONFIG_P1020RDB_PC) 36 #define CONFIG_BOARDNAME "P1020RDB-PC" 37 #define CONFIG_NAND_FSL_ELBC 38 #define CONFIG_P1020 39 #define CONFIG_VSC7385_ENET 40 #define CONFIG_SLIC 41 #define __SW_BOOT_MASK 0x03 42 #define __SW_BOOT_NOR 0x5c 43 #define __SW_BOOT_SPI 0x1c 44 #define __SW_BOOT_SD 0x9c 45 #define __SW_BOOT_NAND 0xec 46 #define __SW_BOOT_PCIE 0x6c 47 #define CONFIG_SYS_L2_SIZE (256 << 10) 48 #endif 49 50 /* 51 * P1020RDB-PD board has user selectable switches for evaluating different 52 * frequency and boot options for the P1020 device. The table that 53 * follow describe the available options. The front six binary number was in 54 * accordance with SW3[1:6]. 55 * 111101 533 533 267 667 NOR Core0 boot; Core1 hold-off 56 * 101101 667 667 333 667 NOR Core0 boot; Core1 hold-off 57 * 011001 800 800 400 667 NOR Core0 boot; Core1 hold-off 58 * 001001 800 800 400 667 SD/MMC Core0 boot; Core1 hold-off 59 * 001101 800 800 400 667 SPI Core0 boot; Core1 hold-off 60 * 010001 800 800 400 667 NAND Core0 boot; Core1 hold-off 61 * 011101 800 800 400 667 PCIe-2 Core0 boot; Core1 hold-off 62 */ 63 #if defined(CONFIG_P1020RDB_PD) 64 #define CONFIG_BOARDNAME "P1020RDB-PD" 65 #define CONFIG_NAND_FSL_ELBC 66 #define CONFIG_P1020 67 #define CONFIG_VSC7385_ENET 68 #define CONFIG_SLIC 69 #define __SW_BOOT_MASK 0x03 70 #define __SW_BOOT_NOR 0x64 71 #define __SW_BOOT_SPI 0x34 72 #define __SW_BOOT_SD 0x24 73 #define __SW_BOOT_NAND 0x44 74 #define __SW_BOOT_PCIE 0x74 75 #define CONFIG_SYS_L2_SIZE (256 << 10) 76 /* 77 * Dynamic MTD Partition support with mtdparts 78 */ 79 #define CONFIG_MTD_DEVICE 80 #define CONFIG_MTD_PARTITIONS 81 #define CONFIG_CMD_MTDPARTS 82 #define CONFIG_FLASH_CFI_MTD 83 #define MTDIDS_DEFAULT "nor0=ec000000.nor" 84 #define MTDPARTS_DEFAULT "mtdparts=ec000000.nor:128k(dtb),6016k(kernel)," \ 85 "57088k(fs),1m(vsc7385-firmware),1280k(u-boot)" 86 #endif 87 88 #if defined(CONFIG_P1021RDB) 89 #define CONFIG_BOARDNAME "P1021RDB-PC" 90 #define CONFIG_NAND_FSL_ELBC 91 #define CONFIG_P1021 92 #define CONFIG_QE 93 #define CONFIG_VSC7385_ENET 94 #define CONFIG_SYS_LBC_LBCR 0x00080000 /* Implement conversion of 95 addresses in the LBC */ 96 #define __SW_BOOT_MASK 0x03 97 #define __SW_BOOT_NOR 0x5c 98 #define __SW_BOOT_SPI 0x1c 99 #define __SW_BOOT_SD 0x9c 100 #define __SW_BOOT_NAND 0xec 101 #define __SW_BOOT_PCIE 0x6c 102 #define CONFIG_SYS_L2_SIZE (256 << 10) 103 /* 104 * Dynamic MTD Partition support with mtdparts 105 */ 106 #define CONFIG_MTD_DEVICE 107 #define CONFIG_MTD_PARTITIONS 108 #define CONFIG_CMD_MTDPARTS 109 #define CONFIG_FLASH_CFI_MTD 110 #ifdef CONFIG_PHYS_64BIT 111 #define MTDIDS_DEFAULT "nor0=fef000000.nor" 112 #define MTDPARTS_DEFAULT "mtdparts=fef000000.nor:256k(vsc7385-firmware)," \ 113 "256k(dtb),4608k(kernel),9728k(fs)," \ 114 "256k(qe-ucode-firmware),1280k(u-boot)" 115 #else 116 #define MTDIDS_DEFAULT "nor0=ef000000.nor" 117 #define MTDPARTS_DEFAULT "mtdparts=ef000000.nor:256k(vsc7385-firmware)," \ 118 "256k(dtb),4608k(kernel),9728k(fs)," \ 119 "256k(qe-ucode-firmware),1280k(u-boot)" 120 #endif 121 #endif 122 123 #if defined(CONFIG_P1024RDB) 124 #define CONFIG_BOARDNAME "P1024RDB" 125 #define CONFIG_NAND_FSL_ELBC 126 #define CONFIG_P1024 127 #define CONFIG_SLIC 128 #define __SW_BOOT_MASK 0xf3 129 #define __SW_BOOT_NOR 0x00 130 #define __SW_BOOT_SPI 0x08 131 #define __SW_BOOT_SD 0x04 132 #define __SW_BOOT_NAND 0x0c 133 #define CONFIG_SYS_L2_SIZE (256 << 10) 134 #endif 135 136 #if defined(CONFIG_P1025RDB) 137 #define CONFIG_BOARDNAME "P1025RDB" 138 #define CONFIG_NAND_FSL_ELBC 139 #define CONFIG_P1025 140 #define CONFIG_QE 141 #define CONFIG_SLIC 142 143 #define CONFIG_SYS_LBC_LBCR 0x00080000 /* Implement conversion of 144 addresses in the LBC */ 145 #define __SW_BOOT_MASK 0xf3 146 #define __SW_BOOT_NOR 0x00 147 #define __SW_BOOT_SPI 0x08 148 #define __SW_BOOT_SD 0x04 149 #define __SW_BOOT_NAND 0x0c 150 #define CONFIG_SYS_L2_SIZE (256 << 10) 151 #endif 152 153 #if defined(CONFIG_P2020RDB) 154 #define CONFIG_BOARDNAME "P2020RDB-PCA" 155 #define CONFIG_NAND_FSL_ELBC 156 #define CONFIG_P2020 157 #define CONFIG_VSC7385_ENET 158 #define __SW_BOOT_MASK 0x03 159 #define __SW_BOOT_NOR 0xc8 160 #define __SW_BOOT_SPI 0x28 161 #define __SW_BOOT_SD 0x68 /* or 0x18 */ 162 #define __SW_BOOT_NAND 0xe8 163 #define __SW_BOOT_PCIE 0xa8 164 #define CONFIG_SYS_L2_SIZE (512 << 10) 165 /* 166 * Dynamic MTD Partition support with mtdparts 167 */ 168 #define CONFIG_MTD_DEVICE 169 #define CONFIG_MTD_PARTITIONS 170 #define CONFIG_CMD_MTDPARTS 171 #define CONFIG_FLASH_CFI_MTD 172 #ifdef CONFIG_PHYS_64BIT 173 #define MTDIDS_DEFAULT "nor0=fef000000.nor" 174 #define MTDPARTS_DEFAULT "mtdparts=fef000000.nor:256k(vsc7385-firmware)," \ 175 "256k(dtb),4608k(kernel),9984k(fs),1280k(u-boot)" 176 #else 177 #define MTDIDS_DEFAULT "nor0=ef000000.nor" 178 #define MTDPARTS_DEFAULT "mtdparts=ef000000.nor:256k(vsc7385-firmware)," \ 179 "256k(dtb),4608k(kernel),9984k(fs),1280k(u-boot)" 180 #endif 181 #endif 182 183 #ifdef CONFIG_SDCARD 184 #define CONFIG_SPL_SERIAL_SUPPORT 185 #define CONFIG_SPL_MMC_MINIMAL 186 #define CONFIG_SPL_FLUSH_IMAGE 187 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 188 #define CONFIG_FSL_LAW /* Use common FSL init code */ 189 #define CONFIG_SYS_TEXT_BASE 0x11001000 190 #define CONFIG_SPL_TEXT_BASE 0xf8f81000 191 #define CONFIG_SPL_PAD_TO 0x20000 192 #define CONFIG_SPL_MAX_SIZE (128 * 1024) 193 #define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10) 194 #define CONFIG_SYS_MMC_U_BOOT_DST (0x11000000) 195 #define CONFIG_SYS_MMC_U_BOOT_START (0x11000000) 196 #define CONFIG_SYS_MMC_U_BOOT_OFFS (128 << 10) 197 #define CONFIG_SYS_MPC85XX_NO_RESETVEC 198 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds" 199 #define CONFIG_SPL_MMC_BOOT 200 #ifdef CONFIG_SPL_BUILD 201 #define CONFIG_SPL_COMMON_INIT_DDR 202 #endif 203 #endif 204 205 #ifdef CONFIG_SPIFLASH 206 #define CONFIG_SPL_SERIAL_SUPPORT 207 #define CONFIG_SPL_SPI_SUPPORT 208 #define CONFIG_SPL_SPI_FLASH_SUPPORT 209 #define CONFIG_SPL_SPI_FLASH_MINIMAL 210 #define CONFIG_SPL_FLUSH_IMAGE 211 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 212 #define CONFIG_FSL_LAW /* Use common FSL init code */ 213 #define CONFIG_SYS_TEXT_BASE 0x11001000 214 #define CONFIG_SPL_TEXT_BASE 0xf8f81000 215 #define CONFIG_SPL_PAD_TO 0x20000 216 #define CONFIG_SPL_MAX_SIZE (128 * 1024) 217 #define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (768 << 10) 218 #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x11000000) 219 #define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x11000000) 220 #define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (128 << 10) 221 #define CONFIG_SYS_MPC85XX_NO_RESETVEC 222 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds" 223 #define CONFIG_SPL_SPI_BOOT 224 #ifdef CONFIG_SPL_BUILD 225 #define CONFIG_SPL_COMMON_INIT_DDR 226 #endif 227 #endif 228 229 #ifdef CONFIG_NAND 230 #ifdef CONFIG_TPL_BUILD 231 #define CONFIG_SPL_NAND_BOOT 232 #define CONFIG_SPL_FLUSH_IMAGE 233 #define CONFIG_SPL_NAND_INIT 234 #define CONFIG_TPL_SERIAL_SUPPORT 235 #define CONFIG_TPL_NAND_SUPPORT 236 #define CONFIG_SPL_COMMON_INIT_DDR 237 #define CONFIG_SPL_MAX_SIZE (128 << 10) 238 #define CONFIG_SPL_TEXT_BASE 0xf8f81000 239 #define CONFIG_SYS_MPC85XX_NO_RESETVEC 240 #define CONFIG_SYS_NAND_U_BOOT_SIZE (832 << 10) 241 #define CONFIG_SYS_NAND_U_BOOT_DST (0x11000000) 242 #define CONFIG_SYS_NAND_U_BOOT_START (0x11000000) 243 #define CONFIG_SYS_NAND_U_BOOT_OFFS ((128 + 128) << 10) 244 #elif defined(CONFIG_SPL_BUILD) 245 #define CONFIG_SPL_INIT_MINIMAL 246 #define CONFIG_SPL_SERIAL_SUPPORT 247 #define CONFIG_SPL_NAND_SUPPORT 248 #define CONFIG_SPL_FLUSH_IMAGE 249 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 250 #define CONFIG_SPL_TEXT_BASE 0xff800000 251 #define CONFIG_SPL_MAX_SIZE 4096 252 #define CONFIG_SYS_NAND_U_BOOT_SIZE (128 << 10) 253 #define CONFIG_SYS_NAND_U_BOOT_DST 0xf8f80000 254 #define CONFIG_SYS_NAND_U_BOOT_START 0xf8f80000 255 #define CONFIG_SYS_NAND_U_BOOT_OFFS (128 << 10) 256 #endif /* not CONFIG_TPL_BUILD */ 257 258 #define CONFIG_SPL_PAD_TO 0x20000 259 #define CONFIG_TPL_PAD_TO 0x20000 260 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 261 #define CONFIG_SYS_TEXT_BASE 0x11001000 262 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds" 263 #endif 264 265 #ifndef CONFIG_SYS_TEXT_BASE 266 #define CONFIG_SYS_TEXT_BASE 0xeff40000 267 #endif 268 269 #ifndef CONFIG_RESET_VECTOR_ADDRESS 270 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc 271 #endif 272 273 #ifndef CONFIG_SYS_MONITOR_BASE 274 #ifdef CONFIG_SPL_BUILD 275 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE 276 #else 277 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 278 #endif 279 #endif 280 281 /* High Level Configuration Options */ 282 #define CONFIG_BOOKE 283 #define CONFIG_E500 284 285 #define CONFIG_MP 286 287 #define CONFIG_FSL_ELBC 288 #define CONFIG_PCI 289 #define CONFIG_PCIE1 /* PCIE controller 1 (slot 1) */ 290 #define CONFIG_PCIE2 /* PCIE controller 2 (slot 2) */ 291 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ 292 #define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */ 293 #define CONFIG_FSL_PCIE_RESET /* need PCIe reset errata */ 294 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ 295 296 #define CONFIG_FSL_LAW 297 #define CONFIG_TSEC_ENET /* tsec ethernet support */ 298 #define CONFIG_ENV_OVERWRITE 299 300 #define CONFIG_CMD_SATA 301 #define CONFIG_SATA_SIL 302 #define CONFIG_SYS_SATA_MAX_DEVICE 2 303 #define CONFIG_LIBATA 304 #define CONFIG_LBA48 305 306 #if defined(CONFIG_P2020RDB) 307 #define CONFIG_SYS_CLK_FREQ 100000000 308 #else 309 #define CONFIG_SYS_CLK_FREQ 66666666 310 #endif 311 #define CONFIG_DDR_CLK_FREQ 66666666 312 313 #define CONFIG_HWCONFIG 314 /* 315 * These can be toggled for performance analysis, otherwise use default. 316 */ 317 #define CONFIG_L2_CACHE 318 #define CONFIG_BTB 319 320 #define CONFIG_BOARD_EARLY_INIT_F /* Call board_pre_init */ 321 322 #define CONFIG_ENABLE_36BIT_PHYS 323 324 #ifdef CONFIG_PHYS_64BIT 325 #define CONFIG_ADDR_MAP 1 326 #define CONFIG_SYS_NUM_ADDR_MAP 16 /* number of TLB1 entries */ 327 #endif 328 329 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ 330 #define CONFIG_SYS_MEMTEST_END 0x1fffffff 331 #define CONFIG_PANIC_HANG /* do not reset board on panic */ 332 333 #define CONFIG_SYS_CCSRBAR 0xffe00000 334 #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR 335 336 /* IN case of NAND bootloader relocate CCSRBAR in RAMboot code not in the 4k 337 SPL code*/ 338 #ifdef CONFIG_SPL_BUILD 339 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE 340 #endif 341 342 /* DDR Setup */ 343 #define CONFIG_SYS_FSL_DDR3 344 #define CONFIG_SYS_DDR_RAW_TIMING 345 #define CONFIG_DDR_SPD 346 #define CONFIG_SYS_SPD_BUS_NUM 1 347 #define SPD_EEPROM_ADDRESS 0x52 348 #undef CONFIG_FSL_DDR_INTERACTIVE 349 350 #if (defined(CONFIG_P1020MBG) || defined(CONFIG_P1020RDB_PD)) 351 #define CONFIG_SYS_SDRAM_SIZE_LAW LAW_SIZE_2G 352 #define CONFIG_CHIP_SELECTS_PER_CTRL 2 353 #else 354 #define CONFIG_SYS_SDRAM_SIZE_LAW LAW_SIZE_1G 355 #define CONFIG_CHIP_SELECTS_PER_CTRL 1 356 #endif 357 #define CONFIG_SYS_SDRAM_SIZE (1u << (CONFIG_SYS_SDRAM_SIZE_LAW - 19)) 358 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 359 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 360 361 #define CONFIG_NUM_DDR_CONTROLLERS 1 362 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 363 364 /* Default settings for DDR3 */ 365 #ifndef CONFIG_P2020RDB 366 #define CONFIG_SYS_DDR_CS0_BNDS 0x0000003f 367 #define CONFIG_SYS_DDR_CS0_CONFIG 0x80014302 368 #define CONFIG_SYS_DDR_CS0_CONFIG_2 0x00000000 369 #define CONFIG_SYS_DDR_CS1_BNDS 0x0040007f 370 #define CONFIG_SYS_DDR_CS1_CONFIG 0x80014302 371 #define CONFIG_SYS_DDR_CS1_CONFIG_2 0x00000000 372 373 #define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef 374 #define CONFIG_SYS_DDR_INIT_ADDR 0x00000000 375 #define CONFIG_SYS_DDR_INIT_EXT_ADDR 0x00000000 376 #define CONFIG_SYS_DDR_MODE_CONTROL 0x00000000 377 378 #define CONFIG_SYS_DDR_ZQ_CONTROL 0x89080600 379 #define CONFIG_SYS_DDR_WRLVL_CONTROL 0x8655A608 380 #define CONFIG_SYS_DDR_SR_CNTR 0x00000000 381 #define CONFIG_SYS_DDR_RCW_1 0x00000000 382 #define CONFIG_SYS_DDR_RCW_2 0x00000000 383 #define CONFIG_SYS_DDR_CONTROL 0xC70C0000 /* Type = DDR3 */ 384 #define CONFIG_SYS_DDR_CONTROL_2 0x04401050 385 #define CONFIG_SYS_DDR_TIMING_4 0x00220001 386 #define CONFIG_SYS_DDR_TIMING_5 0x03402400 387 388 #define CONFIG_SYS_DDR_TIMING_3 0x00020000 389 #define CONFIG_SYS_DDR_TIMING_0 0x00330004 390 #define CONFIG_SYS_DDR_TIMING_1 0x6f6B4846 391 #define CONFIG_SYS_DDR_TIMING_2 0x0FA8C8CF 392 #define CONFIG_SYS_DDR_CLK_CTRL 0x03000000 393 #define CONFIG_SYS_DDR_MODE_1 0x40461520 394 #define CONFIG_SYS_DDR_MODE_2 0x8000c000 395 #define CONFIG_SYS_DDR_INTERVAL 0x0C300000 396 #endif 397 398 #undef CONFIG_CLOCKS_IN_MHZ 399 400 /* 401 * Memory map 402 * 403 * 0x0000_0000 0x7fff_ffff DDR Up to 2GB cacheable 404 * 0x8000_0000 0xdfff_ffff PCI Express Mem 1.5G non-cacheable(PCIe * 3) 405 * 0xec00_0000 0xefff_ffff NOR flash Up to 64M non-cacheable CS0/1 406 * 0xf8f8_0000 0xf8ff_ffff L2 SRAM Up to 512K cacheable 407 * (early boot only) 408 * 0xff80_0000 0xff80_7fff NAND flash 32K non-cacheable CS1/0 409 * 0xff98_0000 0xff98_ffff PMC 64K non-cacheable CS2 410 * 0xffa0_0000 0xffaf_ffff CPLD 1M non-cacheable CS3 411 * 0xffb0_0000 0xffbf_ffff VSC7385 switch 1M non-cacheable CS2 412 * 0xffc0_0000 0xffc3_ffff PCI IO range 256k non-cacheable 413 * 0xffd0_0000 0xffd0_3fff L1 for stack 16K cacheable 414 * 0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable 415 */ 416 417 /* 418 * Local Bus Definitions 419 */ 420 #if (defined(CONFIG_P1020MBG) || defined(CONFIG_P1020RDB_PD)) 421 #define CONFIG_SYS_MAX_FLASH_SECT 512 /* 64M */ 422 #define CONFIG_SYS_FLASH_BASE 0xec000000 423 #elif defined(CONFIG_P1020UTM) 424 #define CONFIG_SYS_MAX_FLASH_SECT 256 /* 32M */ 425 #define CONFIG_SYS_FLASH_BASE 0xee000000 426 #else 427 #define CONFIG_SYS_MAX_FLASH_SECT 128 /* 16M */ 428 #define CONFIG_SYS_FLASH_BASE 0xef000000 429 #endif 430 431 #ifdef CONFIG_PHYS_64BIT 432 #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE) 433 #else 434 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE 435 #endif 436 437 #define CONFIG_FLASH_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) \ 438 | BR_PS_16 | BR_V) 439 440 #define CONFIG_FLASH_OR_PRELIM 0xfc000ff7 441 442 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS} 443 #define CONFIG_SYS_FLASH_QUIET_TEST 444 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 445 446 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ 447 448 #undef CONFIG_SYS_FLASH_CHECKSUM 449 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 450 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 451 452 #define CONFIG_FLASH_CFI_DRIVER 453 #define CONFIG_SYS_FLASH_CFI 454 #define CONFIG_SYS_FLASH_EMPTY_INFO 455 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 456 457 /* Nand Flash */ 458 #ifdef CONFIG_NAND_FSL_ELBC 459 #define CONFIG_SYS_NAND_BASE 0xff800000 460 #ifdef CONFIG_PHYS_64BIT 461 #define CONFIG_SYS_NAND_BASE_PHYS 0xfff800000ull 462 #else 463 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE 464 #endif 465 466 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } 467 #define CONFIG_SYS_MAX_NAND_DEVICE 1 468 #define CONFIG_CMD_NAND 469 #if defined(CONFIG_P1020RDB_PD) 470 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) 471 #else 472 #define CONFIG_SYS_NAND_BLOCK_SIZE (16 * 1024) 473 #endif 474 475 #define CONFIG_SYS_NAND_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 476 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ 477 | BR_PS_8 /* Port Size = 8 bit */ \ 478 | BR_MS_FCM /* MSEL = FCM */ \ 479 | BR_V) /* valid */ 480 #if defined(CONFIG_P1020RDB_PD) 481 #define CONFIG_SYS_NAND_OR_PRELIM (OR_AM_32KB \ 482 | OR_FCM_PGS /* Large Page*/ \ 483 | OR_FCM_CSCT \ 484 | OR_FCM_CST \ 485 | OR_FCM_CHT \ 486 | OR_FCM_SCY_1 \ 487 | OR_FCM_TRLX \ 488 | OR_FCM_EHTR) 489 #else 490 #define CONFIG_SYS_NAND_OR_PRELIM (OR_AM_32KB /* small page */ \ 491 | OR_FCM_CSCT \ 492 | OR_FCM_CST \ 493 | OR_FCM_CHT \ 494 | OR_FCM_SCY_1 \ 495 | OR_FCM_TRLX \ 496 | OR_FCM_EHTR) 497 #endif 498 #endif /* CONFIG_NAND_FSL_ELBC */ 499 500 #define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */ 501 502 #define CONFIG_SYS_INIT_RAM_LOCK 503 #define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* stack in RAM */ 504 #ifdef CONFIG_PHYS_64BIT 505 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf 506 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR 507 /* The assembler doesn't like typecast */ 508 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \ 509 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \ 510 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) 511 #else 512 /* Initial L1 address */ 513 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS CONFIG_SYS_INIT_RAM_ADDR 514 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0 515 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS 516 #endif 517 /* Size of used area in RAM */ 518 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 519 520 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ 521 GENERATED_GBL_DATA_SIZE) 522 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 523 524 #define CONFIG_SYS_MONITOR_LEN (768 * 1024) 525 #define CONFIG_SYS_MALLOC_LEN (1024 * 1024)/* Reserved for malloc */ 526 527 #define CONFIG_SYS_CPLD_BASE 0xffa00000 528 #ifdef CONFIG_PHYS_64BIT 529 #define CONFIG_SYS_CPLD_BASE_PHYS 0xfffa00000ull 530 #else 531 #define CONFIG_SYS_CPLD_BASE_PHYS CONFIG_SYS_CPLD_BASE 532 #endif 533 /* CPLD config size: 1Mb */ 534 #define CONFIG_CPLD_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE_PHYS) | \ 535 BR_PS_8 | BR_V) 536 #define CONFIG_CPLD_OR_PRELIM (0xfff009f7) 537 538 #define CONFIG_SYS_PMC_BASE 0xff980000 539 #define CONFIG_SYS_PMC_BASE_PHYS CONFIG_SYS_PMC_BASE 540 #define CONFIG_PMC_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_PMC_BASE_PHYS) | \ 541 BR_PS_8 | BR_V) 542 #define CONFIG_PMC_OR_PRELIM (OR_AM_64KB | OR_GPCM_CSNT | OR_GPCM_XACS | \ 543 OR_GPCM_SCY | OR_GPCM_TRLX | OR_GPCM_EHTR | \ 544 OR_GPCM_EAD) 545 546 #ifdef CONFIG_NAND 547 #define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Addr */ 548 #define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */ 549 #define CONFIG_SYS_BR1_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */ 550 #define CONFIG_SYS_OR1_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */ 551 #else 552 #define CONFIG_SYS_BR0_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */ 553 #define CONFIG_SYS_OR0_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */ 554 #ifdef CONFIG_NAND_FSL_ELBC 555 #define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Addr */ 556 #define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */ 557 #endif 558 #endif 559 #define CONFIG_SYS_BR3_PRELIM CONFIG_CPLD_BR_PRELIM /* CPLD Base Address */ 560 #define CONFIG_SYS_OR3_PRELIM CONFIG_CPLD_OR_PRELIM /* CPLD Options */ 561 562 /* Vsc7385 switch */ 563 #ifdef CONFIG_VSC7385_ENET 564 #define CONFIG_SYS_VSC7385_BASE 0xffb00000 565 566 #ifdef CONFIG_PHYS_64BIT 567 #define CONFIG_SYS_VSC7385_BASE_PHYS 0xfffb00000ull 568 #else 569 #define CONFIG_SYS_VSC7385_BASE_PHYS CONFIG_SYS_VSC7385_BASE 570 #endif 571 572 #define CONFIG_SYS_VSC7385_BR_PRELIM \ 573 (BR_PHYS_ADDR(CONFIG_SYS_VSC7385_BASE_PHYS) | BR_PS_8 | BR_V) 574 #define CONFIG_SYS_VSC7385_OR_PRELIM (OR_AM_128KB | OR_GPCM_CSNT | \ 575 OR_GPCM_XACS | OR_GPCM_SCY_15 | OR_GPCM_SETA | \ 576 OR_GPCM_TRLX | OR_GPCM_EHTR | OR_GPCM_EAD) 577 578 #define CONFIG_SYS_BR2_PRELIM CONFIG_SYS_VSC7385_BR_PRELIM 579 #define CONFIG_SYS_OR2_PRELIM CONFIG_SYS_VSC7385_OR_PRELIM 580 581 /* The size of the VSC7385 firmware image */ 582 #define CONFIG_VSC7385_IMAGE_SIZE 8192 583 #endif 584 585 /* 586 * Config the L2 Cache as L2 SRAM 587 */ 588 #if defined(CONFIG_SPL_BUILD) 589 #if defined(CONFIG_SDCARD) || defined(CONFIG_SPIFLASH) 590 #define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000 591 #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR 592 #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) 593 #define CONFIG_SPL_RELOC_TEXT_BASE 0xf8f81000 594 #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L2_ADDR + 112 * 1024) 595 #define CONFIG_SPL_RELOC_STACK (CONFIG_SYS_INIT_L2_ADDR + 116 * 1024) 596 #define CONFIG_SPL_RELOC_STACK_SIZE (32 << 10) 597 #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SYS_INIT_L2_ADDR + 148 * 1024) 598 #if defined(CONFIG_P2020RDB) 599 #define CONFIG_SPL_RELOC_MALLOC_SIZE (364 << 10) 600 #else 601 #define CONFIG_SPL_RELOC_MALLOC_SIZE (108 << 10) 602 #endif 603 #elif defined(CONFIG_NAND) 604 #ifdef CONFIG_TPL_BUILD 605 #define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000 606 #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR 607 #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) 608 #define CONFIG_SPL_RELOC_TEXT_BASE 0xf8f81000 609 #define CONFIG_SPL_RELOC_STACK (CONFIG_SYS_INIT_L2_ADDR + 192 * 1024) 610 #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SYS_INIT_L2_ADDR + 208 * 1024) 611 #define CONFIG_SPL_RELOC_MALLOC_SIZE (48 << 10) 612 #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L2_ADDR + 176 * 1024) 613 #else 614 #define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000 615 #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR 616 #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) 617 #define CONFIG_SPL_RELOC_TEXT_BASE (CONFIG_SYS_INIT_L2_END - 0x2000) 618 #define CONFIG_SPL_RELOC_STACK ((CONFIG_SYS_INIT_L2_END - 1) & ~0xF) 619 #endif /* CONFIG_TPL_BUILD */ 620 #endif 621 #endif 622 623 /* Serial Port - controlled on board with jumper J8 624 * open - index 2 625 * shorted - index 1 626 */ 627 #define CONFIG_CONS_INDEX 1 628 #undef CONFIG_SERIAL_SOFTWARE_FIFO 629 #define CONFIG_SYS_NS16550_SERIAL 630 #define CONFIG_SYS_NS16550_REG_SIZE 1 631 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) 632 #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_INIT_MINIMAL) 633 #define CONFIG_NS16550_MIN_FUNCTIONS 634 #endif 635 636 #define CONFIG_SYS_BAUDRATE_TABLE \ 637 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} 638 639 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) 640 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) 641 642 /* I2C */ 643 #define CONFIG_SYS_I2C 644 #define CONFIG_SYS_I2C_FSL 645 #define CONFIG_SYS_FSL_I2C_SPEED 400000 646 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 647 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 648 #define CONFIG_SYS_FSL_I2C2_SPEED 400000 649 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F 650 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100 651 #define CONFIG_SYS_I2C_NOPROBES { {0, 0x29} } 652 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x52 653 #define CONFIG_SYS_SPD_BUS_NUM 1 /* For rom_loc and flash bank */ 654 655 /* 656 * I2C2 EEPROM 657 */ 658 #undef CONFIG_ID_EEPROM 659 660 #define CONFIG_RTC_PT7C4338 661 #define CONFIG_SYS_I2C_RTC_ADDR 0x68 662 #define CONFIG_SYS_I2C_PCA9557_ADDR 0x18 663 664 /* enable read and write access to EEPROM */ 665 #define CONFIG_CMD_EEPROM 666 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 667 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 668 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 669 670 /* 671 * eSPI - Enhanced SPI 672 */ 673 #define CONFIG_HARD_SPI 674 675 #if defined(CONFIG_SPI_FLASH) 676 #define CONFIG_SF_DEFAULT_SPEED 10000000 677 #define CONFIG_SF_DEFAULT_MODE 0 678 #endif 679 680 #if defined(CONFIG_PCI) 681 /* 682 * General PCI 683 * Memory space is mapped 1-1, but I/O space must start from 0. 684 */ 685 686 /* controller 2, direct to uli, tgtid 2, Base address 9000 */ 687 #define CONFIG_SYS_PCIE2_NAME "PCIe SLOT" 688 #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000 689 #ifdef CONFIG_PHYS_64BIT 690 #define CONFIG_SYS_PCIE2_MEM_BUS 0xc0000000 691 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull 692 #else 693 #define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000 694 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000 695 #endif 696 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */ 697 #define CONFIG_SYS_PCIE2_IO_VIRT 0xffc10000 698 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 699 #ifdef CONFIG_PHYS_64BIT 700 #define CONFIG_SYS_PCIE2_IO_PHYS 0xfffc10000ull 701 #else 702 #define CONFIG_SYS_PCIE2_IO_PHYS 0xffc10000 703 #endif 704 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ 705 706 /* controller 1, Slot 2, tgtid 1, Base address a000 */ 707 #define CONFIG_SYS_PCIE1_NAME "mini PCIe SLOT" 708 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 709 #ifdef CONFIG_PHYS_64BIT 710 #define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000 711 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull 712 #else 713 #define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000 714 #define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000 715 #endif 716 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ 717 #define CONFIG_SYS_PCIE1_IO_VIRT 0xffc00000 718 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 719 #ifdef CONFIG_PHYS_64BIT 720 #define CONFIG_SYS_PCIE1_IO_PHYS 0xfffc00000ull 721 #else 722 #define CONFIG_SYS_PCIE1_IO_PHYS 0xffc00000 723 #endif 724 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ 725 726 #define CONFIG_PCI_PNP /* do pci plug-and-play */ 727 #define CONFIG_CMD_PCI 728 729 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 730 #define CONFIG_DOS_PARTITION 731 #endif /* CONFIG_PCI */ 732 733 #if defined(CONFIG_TSEC_ENET) 734 #define CONFIG_MII /* MII PHY management */ 735 #define CONFIG_TSEC1 736 #define CONFIG_TSEC1_NAME "eTSEC1" 737 #define CONFIG_TSEC2 738 #define CONFIG_TSEC2_NAME "eTSEC2" 739 #define CONFIG_TSEC3 740 #define CONFIG_TSEC3_NAME "eTSEC3" 741 742 #define TSEC1_PHY_ADDR 2 743 #define TSEC2_PHY_ADDR 0 744 #define TSEC3_PHY_ADDR 1 745 746 #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 747 #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 748 #define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 749 750 #define TSEC1_PHYIDX 0 751 #define TSEC2_PHYIDX 0 752 #define TSEC3_PHYIDX 0 753 754 #define CONFIG_ETHPRIME "eTSEC1" 755 756 #define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */ 757 758 #define CONFIG_HAS_ETH0 759 #define CONFIG_HAS_ETH1 760 #define CONFIG_HAS_ETH2 761 #endif /* CONFIG_TSEC_ENET */ 762 763 #ifdef CONFIG_QE 764 /* QE microcode/firmware address */ 765 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR 766 #define CONFIG_SYS_QE_FW_ADDR 0xefec0000 767 #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 768 #endif /* CONFIG_QE */ 769 770 #ifdef CONFIG_P1025RDB 771 /* 772 * QE UEC ethernet configuration 773 */ 774 #define CONFIG_MIIM_ADDRESS (CONFIG_SYS_CCSRBAR + 0x82120) 775 776 #undef CONFIG_UEC_ETH 777 #define CONFIG_PHY_MODE_NEED_CHANGE 778 779 #define CONFIG_UEC_ETH1 /* ETH1 */ 780 #define CONFIG_HAS_ETH0 781 782 #ifdef CONFIG_UEC_ETH1 783 #define CONFIG_SYS_UEC1_UCC_NUM 0 /* UCC1 */ 784 #define CONFIG_SYS_UEC1_RX_CLK QE_CLK12 /* CLK12 for MII */ 785 #define CONFIG_SYS_UEC1_TX_CLK QE_CLK9 /* CLK9 for MII */ 786 #define CONFIG_SYS_UEC1_ETH_TYPE FAST_ETH 787 #define CONFIG_SYS_UEC1_PHY_ADDR 0x0 /* 0x0 for MII */ 788 #define CONFIG_SYS_UEC1_INTERFACE_TYPE PHY_INTERFACE_MODE_RMII 789 #define CONFIG_SYS_UEC1_INTERFACE_SPEED 100 790 #endif /* CONFIG_UEC_ETH1 */ 791 792 #define CONFIG_UEC_ETH5 /* ETH5 */ 793 #define CONFIG_HAS_ETH1 794 795 #ifdef CONFIG_UEC_ETH5 796 #define CONFIG_SYS_UEC5_UCC_NUM 4 /* UCC5 */ 797 #define CONFIG_SYS_UEC5_RX_CLK QE_CLK_NONE 798 #define CONFIG_SYS_UEC5_TX_CLK QE_CLK13 /* CLK 13 for RMII */ 799 #define CONFIG_SYS_UEC5_ETH_TYPE FAST_ETH 800 #define CONFIG_SYS_UEC5_PHY_ADDR 0x3 /* 0x3 for RMII */ 801 #define CONFIG_SYS_UEC5_INTERFACE_TYPE PHY_INTERFACE_MODE_RMII 802 #define CONFIG_SYS_UEC5_INTERFACE_SPEED 100 803 #endif /* CONFIG_UEC_ETH5 */ 804 #endif /* CONFIG_P1025RDB */ 805 806 /* 807 * Environment 808 */ 809 #ifdef CONFIG_SPIFLASH 810 #define CONFIG_ENV_IS_IN_SPI_FLASH 811 #define CONFIG_ENV_SPI_BUS 0 812 #define CONFIG_ENV_SPI_CS 0 813 #define CONFIG_ENV_SPI_MAX_HZ 10000000 814 #define CONFIG_ENV_SPI_MODE 0 815 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */ 816 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ 817 #define CONFIG_ENV_SECT_SIZE 0x10000 818 #elif defined(CONFIG_SDCARD) 819 #define CONFIG_ENV_IS_IN_MMC 820 #define CONFIG_FSL_FIXED_MMC_LOCATION 821 #define CONFIG_ENV_SIZE 0x2000 822 #define CONFIG_SYS_MMC_ENV_DEV 0 823 #elif defined(CONFIG_NAND) 824 #ifdef CONFIG_TPL_BUILD 825 #define CONFIG_ENV_SIZE 0x2000 826 #define CONFIG_ENV_ADDR (CONFIG_SYS_INIT_L2_ADDR + (160 << 10)) 827 #else 828 #define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE 829 #endif 830 #define CONFIG_ENV_IS_IN_NAND 831 #define CONFIG_ENV_OFFSET (1024 * 1024) 832 #define CONFIG_ENV_RANGE (3 * CONFIG_ENV_SIZE) 833 #elif defined(CONFIG_SYS_RAMBOOT) 834 #define CONFIG_ENV_IS_NOWHERE /* Store ENV in memory only */ 835 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) 836 #define CONFIG_ENV_SIZE 0x2000 837 #else 838 #define CONFIG_ENV_IS_IN_FLASH 839 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) 840 #define CONFIG_ENV_SIZE 0x2000 841 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ 842 #endif 843 844 #define CONFIG_LOADS_ECHO /* echo on for serial download */ 845 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ 846 847 /* 848 * Command line configuration. 849 */ 850 #define CONFIG_CMD_IRQ 851 #define CONFIG_CMD_DATE 852 #define CONFIG_CMD_REGINFO 853 854 /* 855 * USB 856 */ 857 #define CONFIG_HAS_FSL_DR_USB 858 859 #if defined(CONFIG_HAS_FSL_DR_USB) 860 #define CONFIG_USB_EHCI 861 862 #ifdef CONFIG_USB_EHCI 863 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 864 #define CONFIG_USB_EHCI_FSL 865 #endif 866 #endif 867 868 #if defined(CONFIG_P1020RDB_PD) 869 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1 870 #endif 871 872 #define CONFIG_MMC 873 874 #ifdef CONFIG_MMC 875 #define CONFIG_FSL_ESDHC 876 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR 877 #define CONFIG_GENERIC_MMC 878 #endif 879 880 #if defined(CONFIG_MMC) || defined(CONFIG_USB_EHCI) \ 881 || defined(CONFIG_FSL_SATA) 882 #define CONFIG_DOS_PARTITION 883 #endif 884 885 #undef CONFIG_WATCHDOG /* watchdog disabled */ 886 887 /* 888 * Miscellaneous configurable options 889 */ 890 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 891 #define CONFIG_CMDLINE_EDITING /* Command-line editing */ 892 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 893 #if defined(CONFIG_CMD_KGDB) 894 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 895 #else 896 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 897 #endif 898 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) 899 /* Print Buffer Size */ 900 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 901 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */ 902 903 /* 904 * For booting Linux, the board info and command line data 905 * have to be in the first 64 MB of memory, since this is 906 * the maximum mapped by the Linux kernel during initialization. 907 */ 908 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory for Linux*/ 909 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 910 911 #if defined(CONFIG_CMD_KGDB) 912 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 913 #endif 914 915 /* 916 * Environment Configuration 917 */ 918 #define CONFIG_HOSTNAME unknown 919 #define CONFIG_ROOTPATH "/opt/nfsroot" 920 #define CONFIG_BOOTFILE "uImage" 921 #define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */ 922 923 /* default location for tftp and bootm */ 924 #define CONFIG_LOADADDR 1000000 925 926 #define CONFIG_BOOTARGS /* the boot command will set bootargs */ 927 928 #define CONFIG_BAUDRATE 115200 929 930 #ifdef __SW_BOOT_NOR 931 #define __NOR_RST_CMD \ 932 norboot=i2c dev 1; i2c mw 18 1 __SW_BOOT_NOR 1; \ 933 i2c mw 18 3 __SW_BOOT_MASK 1; reset 934 #endif 935 #ifdef __SW_BOOT_SPI 936 #define __SPI_RST_CMD \ 937 spiboot=i2c dev 1; i2c mw 18 1 __SW_BOOT_SPI 1; \ 938 i2c mw 18 3 __SW_BOOT_MASK 1; reset 939 #endif 940 #ifdef __SW_BOOT_SD 941 #define __SD_RST_CMD \ 942 sdboot=i2c dev 1; i2c mw 18 1 __SW_BOOT_SD 1; \ 943 i2c mw 18 3 __SW_BOOT_MASK 1; reset 944 #endif 945 #ifdef __SW_BOOT_NAND 946 #define __NAND_RST_CMD \ 947 nandboot=i2c dev 1; i2c mw 18 1 __SW_BOOT_NAND 1; \ 948 i2c mw 18 3 __SW_BOOT_MASK 1; reset 949 #endif 950 #ifdef __SW_BOOT_PCIE 951 #define __PCIE_RST_CMD \ 952 pciboot=i2c dev 1; i2c mw 18 1 __SW_BOOT_PCIE 1; \ 953 i2c mw 18 3 __SW_BOOT_MASK 1; reset 954 #endif 955 956 #define CONFIG_EXTRA_ENV_SETTINGS \ 957 "netdev=eth0\0" \ 958 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ 959 "loadaddr=1000000\0" \ 960 "bootfile=uImage\0" \ 961 "tftpflash=tftpboot $loadaddr $uboot; " \ 962 "protect off " __stringify(CONFIG_SYS_TEXT_BASE) " +$filesize; " \ 963 "erase " __stringify(CONFIG_SYS_TEXT_BASE) " +$filesize; " \ 964 "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) " $filesize; " \ 965 "protect on " __stringify(CONFIG_SYS_TEXT_BASE) " +$filesize; " \ 966 "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) " $filesize\0" \ 967 "hwconfig=usb1:dr_mode=host,phy_type=ulpi\0" \ 968 "consoledev=ttyS0\0" \ 969 "ramdiskaddr=2000000\0" \ 970 "ramdiskfile=rootfs.ext2.gz.uboot\0" \ 971 "fdtaddr=1e00000\0" \ 972 "bdev=sda1\0" \ 973 "jffs2nor=mtdblock3\0" \ 974 "norbootaddr=ef080000\0" \ 975 "norfdtaddr=ef040000\0" \ 976 "jffs2nand=mtdblock9\0" \ 977 "nandbootaddr=100000\0" \ 978 "nandfdtaddr=80000\0" \ 979 "ramdisk_size=120000\0" \ 980 "map_lowernorbank=i2c dev 1; i2c mw 18 1 02 1; i2c mw 18 3 fd 1\0" \ 981 "map_uppernorbank=i2c dev 1; i2c mw 18 1 00 1; i2c mw 18 3 fd 1\0" \ 982 __stringify(__NOR_RST_CMD)"\0" \ 983 __stringify(__SPI_RST_CMD)"\0" \ 984 __stringify(__SD_RST_CMD)"\0" \ 985 __stringify(__NAND_RST_CMD)"\0" \ 986 __stringify(__PCIE_RST_CMD)"\0" 987 988 #define CONFIG_NFSBOOTCOMMAND \ 989 "setenv bootargs root=/dev/nfs rw " \ 990 "nfsroot=$serverip:$rootpath " \ 991 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 992 "console=$consoledev,$baudrate $othbootargs;" \ 993 "tftp $loadaddr $bootfile;" \ 994 "tftp $fdtaddr $fdtfile;" \ 995 "bootm $loadaddr - $fdtaddr" 996 997 #define CONFIG_HDBOOT \ 998 "setenv bootargs root=/dev/$bdev rw rootdelay=30 " \ 999 "console=$consoledev,$baudrate $othbootargs;" \ 1000 "usb start;" \ 1001 "ext2load usb 0:1 $loadaddr /boot/$bootfile;" \ 1002 "ext2load usb 0:1 $fdtaddr /boot/$fdtfile;" \ 1003 "bootm $loadaddr - $fdtaddr" 1004 1005 #define CONFIG_USB_FAT_BOOT \ 1006 "setenv bootargs root=/dev/ram rw " \ 1007 "console=$consoledev,$baudrate $othbootargs " \ 1008 "ramdisk_size=$ramdisk_size;" \ 1009 "usb start;" \ 1010 "fatload usb 0:2 $loadaddr $bootfile;" \ 1011 "fatload usb 0:2 $fdtaddr $fdtfile;" \ 1012 "fatload usb 0:2 $ramdiskaddr $ramdiskfile;" \ 1013 "bootm $loadaddr $ramdiskaddr $fdtaddr" 1014 1015 #define CONFIG_USB_EXT2_BOOT \ 1016 "setenv bootargs root=/dev/ram rw " \ 1017 "console=$consoledev,$baudrate $othbootargs " \ 1018 "ramdisk_size=$ramdisk_size;" \ 1019 "usb start;" \ 1020 "ext2load usb 0:4 $loadaddr $bootfile;" \ 1021 "ext2load usb 0:4 $fdtaddr $fdtfile;" \ 1022 "ext2load usb 0:4 $ramdiskaddr $ramdiskfile;" \ 1023 "bootm $loadaddr $ramdiskaddr $fdtaddr" 1024 1025 #define CONFIG_NORBOOT \ 1026 "setenv bootargs root=/dev/$jffs2nor rw " \ 1027 "console=$consoledev,$baudrate rootfstype=jffs2 $othbootargs;" \ 1028 "bootm $norbootaddr - $norfdtaddr" 1029 1030 #define CONFIG_RAMBOOTCOMMAND \ 1031 "setenv bootargs root=/dev/ram rw " \ 1032 "console=$consoledev,$baudrate $othbootargs " \ 1033 "ramdisk_size=$ramdisk_size;" \ 1034 "tftp $ramdiskaddr $ramdiskfile;" \ 1035 "tftp $loadaddr $bootfile;" \ 1036 "tftp $fdtaddr $fdtfile;" \ 1037 "bootm $loadaddr $ramdiskaddr $fdtaddr" 1038 1039 #define CONFIG_BOOTCOMMAND CONFIG_HDBOOT 1040 1041 #endif /* __CONFIG_H */ 1042