1 /* 2 * Copyright 2010-2011 Freescale Semiconductor, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 /* 8 * QorIQ RDB boards configuration file 9 */ 10 #ifndef __CONFIG_H 11 #define __CONFIG_H 12 13 #ifdef CONFIG_36BIT 14 #define CONFIG_PHYS_64BIT 15 #endif 16 17 #if defined(CONFIG_P1020MBG) 18 #define CONFIG_BOARDNAME "P1020MBG-PC" 19 #define CONFIG_P1020 20 #define CONFIG_VSC7385_ENET 21 #define CONFIG_SLIC 22 #define __SW_BOOT_MASK 0x03 23 #define __SW_BOOT_NOR 0xe4 24 #define __SW_BOOT_SD 0x54 25 #define CONFIG_SYS_L2_SIZE (256 << 10) 26 #endif 27 28 #if defined(CONFIG_P1020UTM) 29 #define CONFIG_BOARDNAME "P1020UTM-PC" 30 #define CONFIG_P1020 31 #define __SW_BOOT_MASK 0x03 32 #define __SW_BOOT_NOR 0xe0 33 #define __SW_BOOT_SD 0x50 34 #define CONFIG_SYS_L2_SIZE (256 << 10) 35 #endif 36 37 #if defined(CONFIG_P1020RDB_PC) 38 #define CONFIG_BOARDNAME "P1020RDB-PC" 39 #define CONFIG_NAND_FSL_ELBC 40 #define CONFIG_P1020 41 #define CONFIG_SPI_FLASH 42 #define CONFIG_VSC7385_ENET 43 #define CONFIG_SLIC 44 #define __SW_BOOT_MASK 0x03 45 #define __SW_BOOT_NOR 0x5c 46 #define __SW_BOOT_SPI 0x1c 47 #define __SW_BOOT_SD 0x9c 48 #define __SW_BOOT_NAND 0xec 49 #define __SW_BOOT_PCIE 0x6c 50 #define CONFIG_SYS_L2_SIZE (256 << 10) 51 #endif 52 53 /* 54 * P1020RDB-PD board has user selectable switches for evaluating different 55 * frequency and boot options for the P1020 device. The table that 56 * follow describe the available options. The front six binary number was in 57 * accordance with SW3[1:6]. 58 * 111101 533 533 267 667 NOR Core0 boot; Core1 hold-off 59 * 101101 667 667 333 667 NOR Core0 boot; Core1 hold-off 60 * 011001 800 800 400 667 NOR Core0 boot; Core1 hold-off 61 * 001001 800 800 400 667 SD/MMC Core0 boot; Core1 hold-off 62 * 001101 800 800 400 667 SPI Core0 boot; Core1 hold-off 63 * 010001 800 800 400 667 NAND Core0 boot; Core1 hold-off 64 * 011101 800 800 400 667 PCIe-2 Core0 boot; Core1 hold-off 65 */ 66 #if defined(CONFIG_P1020RDB_PD) 67 #define CONFIG_BOARDNAME "P1020RDB-PD" 68 #define CONFIG_NAND_FSL_ELBC 69 #define CONFIG_P1020 70 #define CONFIG_SPI_FLASH 71 #define CONFIG_VSC7385_ENET 72 #define CONFIG_SLIC 73 #define __SW_BOOT_MASK 0x03 74 #define __SW_BOOT_NOR 0x64 75 #define __SW_BOOT_SPI 0x34 76 #define __SW_BOOT_SD 0x24 77 #define __SW_BOOT_NAND 0x44 78 #define __SW_BOOT_PCIE 0x74 79 #define CONFIG_SYS_L2_SIZE (256 << 10) 80 #endif 81 82 #if defined(CONFIG_P1021RDB) 83 #define CONFIG_BOARDNAME "P1021RDB-PC" 84 #define CONFIG_NAND_FSL_ELBC 85 #define CONFIG_P1021 86 #define CONFIG_QE 87 #define CONFIG_SPI_FLASH 88 #define CONFIG_VSC7385_ENET 89 #define CONFIG_SYS_LBC_LBCR 0x00080000 /* Implement conversion of 90 addresses in the LBC */ 91 #define __SW_BOOT_MASK 0x03 92 #define __SW_BOOT_NOR 0x5c 93 #define __SW_BOOT_SPI 0x1c 94 #define __SW_BOOT_SD 0x9c 95 #define __SW_BOOT_NAND 0xec 96 #define __SW_BOOT_PCIE 0x6c 97 #define CONFIG_SYS_L2_SIZE (256 << 10) 98 #endif 99 100 #if defined(CONFIG_P1024RDB) 101 #define CONFIG_BOARDNAME "P1024RDB" 102 #define CONFIG_NAND_FSL_ELBC 103 #define CONFIG_P1024 104 #define CONFIG_SLIC 105 #define CONFIG_SPI_FLASH 106 #define __SW_BOOT_MASK 0xf3 107 #define __SW_BOOT_NOR 0x00 108 #define __SW_BOOT_SPI 0x08 109 #define __SW_BOOT_SD 0x04 110 #define __SW_BOOT_NAND 0x0c 111 #define CONFIG_SYS_L2_SIZE (256 << 10) 112 #endif 113 114 #if defined(CONFIG_P1025RDB) 115 #define CONFIG_BOARDNAME "P1025RDB" 116 #define CONFIG_NAND_FSL_ELBC 117 #define CONFIG_P1025 118 #define CONFIG_QE 119 #define CONFIG_SLIC 120 #define CONFIG_SPI_FLASH 121 122 #define CONFIG_SYS_LBC_LBCR 0x00080000 /* Implement conversion of 123 addresses in the LBC */ 124 #define __SW_BOOT_MASK 0xf3 125 #define __SW_BOOT_NOR 0x00 126 #define __SW_BOOT_SPI 0x08 127 #define __SW_BOOT_SD 0x04 128 #define __SW_BOOT_NAND 0x0c 129 #define CONFIG_SYS_L2_SIZE (256 << 10) 130 #endif 131 132 #if defined(CONFIG_P2020RDB) 133 #define CONFIG_BOARDNAME "P2020RDB-PCA" 134 #define CONFIG_NAND_FSL_ELBC 135 #define CONFIG_P2020 136 #define CONFIG_SPI_FLASH 137 #define CONFIG_VSC7385_ENET 138 #define __SW_BOOT_MASK 0x03 139 #define __SW_BOOT_NOR 0xc8 140 #define __SW_BOOT_SPI 0x28 141 #define __SW_BOOT_SD 0x68 /* or 0x18 */ 142 #define __SW_BOOT_NAND 0xe8 143 #define __SW_BOOT_PCIE 0xa8 144 #define CONFIG_SYS_L2_SIZE (512 << 10) 145 #endif 146 147 #ifdef CONFIG_SDCARD 148 #define CONFIG_SPL 149 #define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT 150 #define CONFIG_SPL_ENV_SUPPORT 151 #define CONFIG_SPL_SERIAL_SUPPORT 152 #define CONFIG_SPL_MMC_SUPPORT 153 #define CONFIG_SPL_MMC_MINIMAL 154 #define CONFIG_SPL_FLUSH_IMAGE 155 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 156 #define CONFIG_SPL_LIBGENERIC_SUPPORT 157 #define CONFIG_SPL_LIBCOMMON_SUPPORT 158 #define CONFIG_SPL_I2C_SUPPORT 159 #define CONFIG_FSL_LAW /* Use common FSL init code */ 160 #define CONFIG_SYS_TEXT_BASE 0x11001000 161 #define CONFIG_SPL_TEXT_BASE 0xf8f81000 162 #define CONFIG_SPL_PAD_TO 0x18000 163 #define CONFIG_SPL_MAX_SIZE (96 * 1024) 164 #define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10) 165 #define CONFIG_SYS_MMC_U_BOOT_DST (0x11000000) 166 #define CONFIG_SYS_MMC_U_BOOT_START (0x11000000) 167 #define CONFIG_SYS_MMC_U_BOOT_OFFS (96 << 10) 168 #define CONFIG_SYS_MPC85XX_NO_RESETVEC 169 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds" 170 #define CONFIG_SPL_MMC_BOOT 171 #ifdef CONFIG_SPL_BUILD 172 #define CONFIG_SPL_COMMON_INIT_DDR 173 #endif 174 #endif 175 176 #ifdef CONFIG_SPIFLASH 177 #define CONFIG_SPL 178 #define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT 179 #define CONFIG_SPL_ENV_SUPPORT 180 #define CONFIG_SPL_SERIAL_SUPPORT 181 #define CONFIG_SPL_SPI_SUPPORT 182 #define CONFIG_SPL_SPI_FLASH_SUPPORT 183 #define CONFIG_SPL_SPI_FLASH_MINIMAL 184 #define CONFIG_SPL_FLUSH_IMAGE 185 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 186 #define CONFIG_SPL_LIBGENERIC_SUPPORT 187 #define CONFIG_SPL_LIBCOMMON_SUPPORT 188 #define CONFIG_SPL_I2C_SUPPORT 189 #define CONFIG_FSL_LAW /* Use common FSL init code */ 190 #define CONFIG_SYS_TEXT_BASE 0x11001000 191 #define CONFIG_SPL_TEXT_BASE 0xf8f81000 192 #define CONFIG_SPL_PAD_TO 0x18000 193 #define CONFIG_SPL_MAX_SIZE (96 * 1024) 194 #define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (768 << 10) 195 #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x11000000) 196 #define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x11000000) 197 #define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (96 << 10) 198 #define CONFIG_SYS_MPC85XX_NO_RESETVEC 199 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds" 200 #define CONFIG_SPL_SPI_BOOT 201 #ifdef CONFIG_SPL_BUILD 202 #define CONFIG_SPL_COMMON_INIT_DDR 203 #endif 204 #endif 205 206 #ifdef CONFIG_NAND 207 #define CONFIG_SPL 208 #define CONFIG_TPL 209 #ifdef CONFIG_TPL_BUILD 210 #define CONFIG_SPL_NAND_BOOT 211 #define CONFIG_SPL_FLUSH_IMAGE 212 #define CONFIG_SPL_ENV_SUPPORT 213 #define CONFIG_SPL_NAND_INIT 214 #define CONFIG_SPL_SERIAL_SUPPORT 215 #define CONFIG_SPL_LIBGENERIC_SUPPORT 216 #define CONFIG_SPL_LIBCOMMON_SUPPORT 217 #define CONFIG_SPL_I2C_SUPPORT 218 #define CONFIG_SPL_NAND_SUPPORT 219 #define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT 220 #define CONFIG_SPL_COMMON_INIT_DDR 221 #define CONFIG_SPL_MAX_SIZE (128 << 10) 222 #define CONFIG_SPL_TEXT_BASE 0xf8f81000 223 #define CONFIG_SYS_MPC85XX_NO_RESETVEC 224 #define CONFIG_SYS_NAND_U_BOOT_SIZE (832 << 10) 225 #define CONFIG_SYS_NAND_U_BOOT_DST (0x11000000) 226 #define CONFIG_SYS_NAND_U_BOOT_START (0x11000000) 227 #define CONFIG_SYS_NAND_U_BOOT_OFFS ((128 + 128) << 10) 228 #elif defined(CONFIG_SPL_BUILD) 229 #define CONFIG_SPL_INIT_MINIMAL 230 #define CONFIG_SPL_SERIAL_SUPPORT 231 #define CONFIG_SPL_NAND_SUPPORT 232 #define CONFIG_SPL_FLUSH_IMAGE 233 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 234 #define CONFIG_SPL_TEXT_BASE 0xff800000 235 #define CONFIG_SPL_MAX_SIZE 4096 236 #define CONFIG_SYS_NAND_U_BOOT_SIZE (128 << 10) 237 #define CONFIG_SYS_NAND_U_BOOT_DST 0xf8f80000 238 #define CONFIG_SYS_NAND_U_BOOT_START 0xf8f80000 239 #define CONFIG_SYS_NAND_U_BOOT_OFFS (128 << 10) 240 #endif /* not CONFIG_TPL_BUILD */ 241 242 #define CONFIG_SPL_PAD_TO 0x20000 243 #define CONFIG_TPL_PAD_TO 0x20000 244 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 245 #define CONFIG_SYS_TEXT_BASE 0x11001000 246 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds" 247 #endif 248 249 #ifndef CONFIG_SYS_TEXT_BASE 250 #define CONFIG_SYS_TEXT_BASE 0xeff40000 251 #endif 252 253 #ifndef CONFIG_RESET_VECTOR_ADDRESS 254 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc 255 #endif 256 257 #ifndef CONFIG_SYS_MONITOR_BASE 258 #ifdef CONFIG_SPL_BUILD 259 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE 260 #else 261 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 262 #endif 263 #endif 264 265 /* High Level Configuration Options */ 266 #define CONFIG_BOOKE 267 #define CONFIG_E500 268 269 #define CONFIG_MP 270 271 #define CONFIG_FSL_ELBC 272 #define CONFIG_PCI 273 #define CONFIG_PCIE1 /* PCIE controler 1 (slot 1) */ 274 #define CONFIG_PCIE2 /* PCIE controler 2 (slot 2) */ 275 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ 276 #define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */ 277 #define CONFIG_FSL_PCIE_RESET /* need PCIe reset errata */ 278 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ 279 280 #define CONFIG_FSL_LAW 281 #define CONFIG_TSEC_ENET /* tsec ethernet support */ 282 #define CONFIG_ENV_OVERWRITE 283 284 #define CONFIG_CMD_SATA 285 #define CONFIG_SATA_SIL 286 #define CONFIG_SYS_SATA_MAX_DEVICE 2 287 #define CONFIG_LIBATA 288 #define CONFIG_LBA48 289 290 #if defined(CONFIG_P2020RDB) 291 #define CONFIG_SYS_CLK_FREQ 100000000 292 #else 293 #define CONFIG_SYS_CLK_FREQ 66666666 294 #endif 295 #define CONFIG_DDR_CLK_FREQ 66666666 296 297 #define CONFIG_HWCONFIG 298 /* 299 * These can be toggled for performance analysis, otherwise use default. 300 */ 301 #define CONFIG_L2_CACHE 302 #define CONFIG_BTB 303 304 #define CONFIG_BOARD_EARLY_INIT_F /* Call board_pre_init */ 305 306 #define CONFIG_ENABLE_36BIT_PHYS 307 308 #ifdef CONFIG_PHYS_64BIT 309 #define CONFIG_ADDR_MAP 1 310 #define CONFIG_SYS_NUM_ADDR_MAP 16 /* number of TLB1 entries */ 311 #endif 312 313 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ 314 #define CONFIG_SYS_MEMTEST_END 0x1fffffff 315 #define CONFIG_PANIC_HANG /* do not reset board on panic */ 316 317 #define CONFIG_SYS_CCSRBAR 0xffe00000 318 #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR 319 320 /* IN case of NAND bootloader relocate CCSRBAR in RAMboot code not in the 4k 321 SPL code*/ 322 #ifdef CONFIG_SPL_BUILD 323 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE 324 #endif 325 326 /* DDR Setup */ 327 #define CONFIG_SYS_FSL_DDR3 328 #define CONFIG_SYS_DDR_RAW_TIMING 329 #define CONFIG_DDR_SPD 330 #define CONFIG_SYS_SPD_BUS_NUM 1 331 #define SPD_EEPROM_ADDRESS 0x52 332 #undef CONFIG_FSL_DDR_INTERACTIVE 333 334 #if (defined(CONFIG_P1020MBG) || defined(CONFIG_P1020RDB_PD)) 335 #define CONFIG_SYS_SDRAM_SIZE_LAW LAW_SIZE_2G 336 #define CONFIG_CHIP_SELECTS_PER_CTRL 2 337 #else 338 #define CONFIG_SYS_SDRAM_SIZE_LAW LAW_SIZE_1G 339 #define CONFIG_CHIP_SELECTS_PER_CTRL 1 340 #endif 341 #define CONFIG_SYS_SDRAM_SIZE (1u << (CONFIG_SYS_SDRAM_SIZE_LAW - 19)) 342 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 343 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 344 345 #define CONFIG_NUM_DDR_CONTROLLERS 1 346 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 347 348 /* Default settings for DDR3 */ 349 #ifndef CONFIG_P2020RDB 350 #define CONFIG_SYS_DDR_CS0_BNDS 0x0000003f 351 #define CONFIG_SYS_DDR_CS0_CONFIG 0x80014302 352 #define CONFIG_SYS_DDR_CS0_CONFIG_2 0x00000000 353 #define CONFIG_SYS_DDR_CS1_BNDS 0x0040007f 354 #define CONFIG_SYS_DDR_CS1_CONFIG 0x80014302 355 #define CONFIG_SYS_DDR_CS1_CONFIG_2 0x00000000 356 357 #define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef 358 #define CONFIG_SYS_DDR_INIT_ADDR 0x00000000 359 #define CONFIG_SYS_DDR_INIT_EXT_ADDR 0x00000000 360 #define CONFIG_SYS_DDR_MODE_CONTROL 0x00000000 361 362 #define CONFIG_SYS_DDR_ZQ_CONTROL 0x89080600 363 #define CONFIG_SYS_DDR_WRLVL_CONTROL 0x8655A608 364 #define CONFIG_SYS_DDR_SR_CNTR 0x00000000 365 #define CONFIG_SYS_DDR_RCW_1 0x00000000 366 #define CONFIG_SYS_DDR_RCW_2 0x00000000 367 #define CONFIG_SYS_DDR_CONTROL 0xC70C0000 /* Type = DDR3 */ 368 #define CONFIG_SYS_DDR_CONTROL_2 0x04401050 369 #define CONFIG_SYS_DDR_TIMING_4 0x00220001 370 #define CONFIG_SYS_DDR_TIMING_5 0x03402400 371 372 #define CONFIG_SYS_DDR_TIMING_3 0x00020000 373 #define CONFIG_SYS_DDR_TIMING_0 0x00330004 374 #define CONFIG_SYS_DDR_TIMING_1 0x6f6B4846 375 #define CONFIG_SYS_DDR_TIMING_2 0x0FA8C8CF 376 #define CONFIG_SYS_DDR_CLK_CTRL 0x03000000 377 #define CONFIG_SYS_DDR_MODE_1 0x40461520 378 #define CONFIG_SYS_DDR_MODE_2 0x8000c000 379 #define CONFIG_SYS_DDR_INTERVAL 0x0C300000 380 #endif 381 382 #undef CONFIG_CLOCKS_IN_MHZ 383 384 /* 385 * Memory map 386 * 387 * 0x0000_0000 0x7fff_ffff DDR Up to 2GB cacheable 388 * 0x8000_0000 0xdfff_ffff PCI Express Mem 1.5G non-cacheable(PCIe * 3) 389 * 0xec00_0000 0xefff_ffff NOR flash Up to 64M non-cacheable CS0/1 390 * 0xf8f8_0000 0xf8ff_ffff L2 SRAM Up to 512K cacheable 391 * (early boot only) 392 * 0xff80_0000 0xff80_7fff NAND flash 32K non-cacheable CS1/0 393 * 0xff98_0000 0xff98_ffff PMC 64K non-cacheable CS2 394 * 0xffa0_0000 0xffaf_ffff CPLD 1M non-cacheable CS3 395 * 0xffb0_0000 0xffbf_ffff VSC7385 switch 1M non-cacheable CS2 396 * 0xffc0_0000 0xffc3_ffff PCI IO range 256k non-cacheable 397 * 0xffd0_0000 0xffd0_3fff L1 for stack 16K cacheable 398 * 0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable 399 */ 400 401 402 /* 403 * Local Bus Definitions 404 */ 405 #if (defined(CONFIG_P1020MBG) || defined(CONFIG_P1020RDB_PD)) 406 #define CONFIG_SYS_MAX_FLASH_SECT 512 /* 64M */ 407 #define CONFIG_SYS_FLASH_BASE 0xec000000 408 #elif defined(CONFIG_P1020UTM) 409 #define CONFIG_SYS_MAX_FLASH_SECT 256 /* 32M */ 410 #define CONFIG_SYS_FLASH_BASE 0xee000000 411 #else 412 #define CONFIG_SYS_MAX_FLASH_SECT 128 /* 16M */ 413 #define CONFIG_SYS_FLASH_BASE 0xef000000 414 #endif 415 416 417 #ifdef CONFIG_PHYS_64BIT 418 #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE) 419 #else 420 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE 421 #endif 422 423 #define CONFIG_FLASH_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) \ 424 | BR_PS_16 | BR_V) 425 426 #define CONFIG_FLASH_OR_PRELIM 0xfc000ff7 427 428 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS} 429 #define CONFIG_SYS_FLASH_QUIET_TEST 430 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 431 432 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ 433 434 #undef CONFIG_SYS_FLASH_CHECKSUM 435 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 436 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 437 438 #define CONFIG_FLASH_CFI_DRIVER 439 #define CONFIG_SYS_FLASH_CFI 440 #define CONFIG_SYS_FLASH_EMPTY_INFO 441 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 442 443 /* Nand Flash */ 444 #ifdef CONFIG_NAND_FSL_ELBC 445 #define CONFIG_SYS_NAND_BASE 0xff800000 446 #ifdef CONFIG_PHYS_64BIT 447 #define CONFIG_SYS_NAND_BASE_PHYS 0xfff800000ull 448 #else 449 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE 450 #endif 451 452 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } 453 #define CONFIG_SYS_MAX_NAND_DEVICE 1 454 #define CONFIG_MTD_NAND_VERIFY_WRITE 455 #define CONFIG_CMD_NAND 456 #if defined(CONFIG_P1020RDB_PD) 457 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) 458 #else 459 #define CONFIG_SYS_NAND_BLOCK_SIZE (16 * 1024) 460 #endif 461 462 #define CONFIG_SYS_NAND_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 463 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ 464 | BR_PS_8 /* Port Size = 8 bit */ \ 465 | BR_MS_FCM /* MSEL = FCM */ \ 466 | BR_V) /* valid */ 467 #if defined(CONFIG_P1020RDB_PD) 468 #define CONFIG_SYS_NAND_OR_PRELIM (OR_AM_32KB \ 469 | OR_FCM_PGS /* Large Page*/ \ 470 | OR_FCM_CSCT \ 471 | OR_FCM_CST \ 472 | OR_FCM_CHT \ 473 | OR_FCM_SCY_1 \ 474 | OR_FCM_TRLX \ 475 | OR_FCM_EHTR) 476 #else 477 #define CONFIG_SYS_NAND_OR_PRELIM (OR_AM_32KB /* small page */ \ 478 | OR_FCM_CSCT \ 479 | OR_FCM_CST \ 480 | OR_FCM_CHT \ 481 | OR_FCM_SCY_1 \ 482 | OR_FCM_TRLX \ 483 | OR_FCM_EHTR) 484 #endif 485 #endif /* CONFIG_NAND_FSL_ELBC */ 486 487 #define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */ 488 489 #define CONFIG_SYS_INIT_RAM_LOCK 490 #define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* stack in RAM */ 491 #ifdef CONFIG_PHYS_64BIT 492 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf 493 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR 494 /* The assembler doesn't like typecast */ 495 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \ 496 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \ 497 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) 498 #else 499 /* Initial L1 address */ 500 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS CONFIG_SYS_INIT_RAM_ADDR 501 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0 502 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS 503 #endif 504 /* Size of used area in RAM */ 505 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 506 507 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ 508 GENERATED_GBL_DATA_SIZE) 509 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 510 511 #define CONFIG_SYS_MONITOR_LEN (256 * 1024)/* Reserve 256 kB for Mon */ 512 #define CONFIG_SYS_MALLOC_LEN (1024 * 1024)/* Reserved for malloc */ 513 514 #define CONFIG_SYS_CPLD_BASE 0xffa00000 515 #ifdef CONFIG_PHYS_64BIT 516 #define CONFIG_SYS_CPLD_BASE_PHYS 0xfffa00000ull 517 #else 518 #define CONFIG_SYS_CPLD_BASE_PHYS CONFIG_SYS_CPLD_BASE 519 #endif 520 /* CPLD config size: 1Mb */ 521 #define CONFIG_CPLD_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE_PHYS) | \ 522 BR_PS_8 | BR_V) 523 #define CONFIG_CPLD_OR_PRELIM (0xfff009f7) 524 525 #define CONFIG_SYS_PMC_BASE 0xff980000 526 #define CONFIG_SYS_PMC_BASE_PHYS CONFIG_SYS_PMC_BASE 527 #define CONFIG_PMC_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_PMC_BASE_PHYS) | \ 528 BR_PS_8 | BR_V) 529 #define CONFIG_PMC_OR_PRELIM (OR_AM_64KB | OR_GPCM_CSNT | OR_GPCM_XACS | \ 530 OR_GPCM_SCY | OR_GPCM_TRLX | OR_GPCM_EHTR | \ 531 OR_GPCM_EAD) 532 533 #ifdef CONFIG_NAND 534 #define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Addr */ 535 #define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */ 536 #define CONFIG_SYS_BR1_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */ 537 #define CONFIG_SYS_OR1_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */ 538 #else 539 #define CONFIG_SYS_BR0_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */ 540 #define CONFIG_SYS_OR0_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */ 541 #ifdef CONFIG_NAND_FSL_ELBC 542 #define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Addr */ 543 #define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */ 544 #endif 545 #endif 546 #define CONFIG_SYS_BR3_PRELIM CONFIG_CPLD_BR_PRELIM /* CPLD Base Address */ 547 #define CONFIG_SYS_OR3_PRELIM CONFIG_CPLD_OR_PRELIM /* CPLD Options */ 548 549 550 /* Vsc7385 switch */ 551 #ifdef CONFIG_VSC7385_ENET 552 #define CONFIG_SYS_VSC7385_BASE 0xffb00000 553 554 #ifdef CONFIG_PHYS_64BIT 555 #define CONFIG_SYS_VSC7385_BASE_PHYS 0xfffb00000ull 556 #else 557 #define CONFIG_SYS_VSC7385_BASE_PHYS CONFIG_SYS_VSC7385_BASE 558 #endif 559 560 #define CONFIG_SYS_VSC7385_BR_PRELIM \ 561 (BR_PHYS_ADDR(CONFIG_SYS_VSC7385_BASE_PHYS) | BR_PS_8 | BR_V) 562 #define CONFIG_SYS_VSC7385_OR_PRELIM (OR_AM_128KB | OR_GPCM_CSNT | \ 563 OR_GPCM_XACS | OR_GPCM_SCY_15 | OR_GPCM_SETA | \ 564 OR_GPCM_TRLX | OR_GPCM_EHTR | OR_GPCM_EAD) 565 566 #define CONFIG_SYS_BR2_PRELIM CONFIG_SYS_VSC7385_BR_PRELIM 567 #define CONFIG_SYS_OR2_PRELIM CONFIG_SYS_VSC7385_OR_PRELIM 568 569 /* The size of the VSC7385 firmware image */ 570 #define CONFIG_VSC7385_IMAGE_SIZE 8192 571 #endif 572 573 /* 574 * Config the L2 Cache as L2 SRAM 575 */ 576 #if defined(CONFIG_SPL_BUILD) 577 #if defined(CONFIG_SDCARD) || defined(CONFIG_SPIFLASH) 578 #define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000 579 #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR 580 #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) 581 #define CONFIG_SPL_RELOC_TEXT_BASE 0xf8f81000 582 #define CONFIG_SPL_RELOC_STACK (CONFIG_SYS_INIT_L2_ADDR + 128 * 1024) 583 #define CONFIG_SPL_RELOC_STACK_SIZE (32 << 10) 584 #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SYS_INIT_L2_ADDR + 160 * 1024) 585 #define CONFIG_SPL_RELOC_MALLOC_SIZE (96 << 10) 586 #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L2_ADDR + 112 * 1024) 587 #elif defined(CONFIG_NAND) 588 #ifdef CONFIG_TPL_BUILD 589 #define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000 590 #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR 591 #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) 592 #define CONFIG_SPL_RELOC_TEXT_BASE 0xf8f81000 593 #define CONFIG_SPL_RELOC_STACK (CONFIG_SYS_INIT_L2_ADDR + 192 * 1024) 594 #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SYS_INIT_L2_ADDR + 208 * 1024) 595 #define CONFIG_SPL_RELOC_MALLOC_SIZE (48 << 10) 596 #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L2_ADDR + 176 * 1024) 597 #else 598 #define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000 599 #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR 600 #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) 601 #define CONFIG_SPL_RELOC_TEXT_BASE (CONFIG_SYS_INIT_L2_END - 0x2000) 602 #define CONFIG_SPL_RELOC_STACK ((CONFIG_SYS_INIT_L2_END - 1) & ~0xF) 603 #endif /* CONFIG_TPL_BUILD */ 604 #endif 605 #endif 606 607 /* Serial Port - controlled on board with jumper J8 608 * open - index 2 609 * shorted - index 1 610 */ 611 #define CONFIG_CONS_INDEX 1 612 #undef CONFIG_SERIAL_SOFTWARE_FIFO 613 #define CONFIG_SYS_NS16550 614 #define CONFIG_SYS_NS16550_SERIAL 615 #define CONFIG_SYS_NS16550_REG_SIZE 1 616 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) 617 #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_INIT_MINIMAL) 618 #define CONFIG_NS16550_MIN_FUNCTIONS 619 #endif 620 621 #define CONFIG_SYS_BAUDRATE_TABLE \ 622 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} 623 624 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) 625 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) 626 627 /* Use the HUSH parser */ 628 #define CONFIG_SYS_HUSH_PARSER 629 630 /* 631 * Pass open firmware flat tree 632 */ 633 #define CONFIG_OF_LIBFDT 634 #define CONFIG_OF_BOARD_SETUP 635 #define CONFIG_OF_STDOUT_VIA_ALIAS 636 637 /* new uImage format support */ 638 #define CONFIG_FIT 639 #define CONFIG_FIT_VERBOSE /* enable fit_format_{error,warning}() */ 640 641 /* I2C */ 642 #define CONFIG_SYS_I2C 643 #define CONFIG_SYS_I2C_FSL 644 #define CONFIG_SYS_FSL_I2C_SPEED 400000 645 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 646 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 647 #define CONFIG_SYS_FSL_I2C2_SPEED 400000 648 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F 649 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100 650 #define CONFIG_SYS_I2C_NOPROBES { {0, 0x29} } 651 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x52 652 #define CONFIG_SYS_SPD_BUS_NUM 1 /* For rom_loc and flash bank */ 653 654 /* 655 * I2C2 EEPROM 656 */ 657 #undef CONFIG_ID_EEPROM 658 659 #define CONFIG_RTC_PT7C4338 660 #define CONFIG_SYS_I2C_RTC_ADDR 0x68 661 #define CONFIG_SYS_I2C_PCA9557_ADDR 0x18 662 663 /* enable read and write access to EEPROM */ 664 #define CONFIG_CMD_EEPROM 665 #define CONFIG_SYS_I2C_MULTI_EEPROMS 666 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 667 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 668 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 669 670 /* 671 * eSPI - Enhanced SPI 672 */ 673 #define CONFIG_HARD_SPI 674 #define CONFIG_FSL_ESPI 675 676 #if defined(CONFIG_SPI_FLASH) 677 #define CONFIG_SPI_FLASH_SPANSION 678 #define CONFIG_CMD_SF 679 #define CONFIG_SF_DEFAULT_SPEED 10000000 680 #define CONFIG_SF_DEFAULT_MODE 0 681 #endif 682 683 #if defined(CONFIG_PCI) 684 /* 685 * General PCI 686 * Memory space is mapped 1-1, but I/O space must start from 0. 687 */ 688 689 /* controller 2, direct to uli, tgtid 2, Base address 9000 */ 690 #define CONFIG_SYS_PCIE2_NAME "PCIe SLOT" 691 #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000 692 #ifdef CONFIG_PHYS_64BIT 693 #define CONFIG_SYS_PCIE2_MEM_BUS 0xc0000000 694 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull 695 #else 696 #define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000 697 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000 698 #endif 699 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */ 700 #define CONFIG_SYS_PCIE2_IO_VIRT 0xffc10000 701 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 702 #ifdef CONFIG_PHYS_64BIT 703 #define CONFIG_SYS_PCIE2_IO_PHYS 0xfffc10000ull 704 #else 705 #define CONFIG_SYS_PCIE2_IO_PHYS 0xffc10000 706 #endif 707 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ 708 709 /* controller 1, Slot 2, tgtid 1, Base address a000 */ 710 #define CONFIG_SYS_PCIE1_NAME "mini PCIe SLOT" 711 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 712 #ifdef CONFIG_PHYS_64BIT 713 #define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000 714 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull 715 #else 716 #define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000 717 #define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000 718 #endif 719 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ 720 #define CONFIG_SYS_PCIE1_IO_VIRT 0xffc00000 721 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 722 #ifdef CONFIG_PHYS_64BIT 723 #define CONFIG_SYS_PCIE1_IO_PHYS 0xfffc00000ull 724 #else 725 #define CONFIG_SYS_PCIE1_IO_PHYS 0xffc00000 726 #endif 727 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ 728 729 #define CONFIG_PCI_PNP /* do pci plug-and-play */ 730 #define CONFIG_E1000 /* Defind e1000 pci Ethernet card*/ 731 #define CONFIG_CMD_PCI 732 #define CONFIG_CMD_NET 733 734 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 735 #define CONFIG_DOS_PARTITION 736 #endif /* CONFIG_PCI */ 737 738 #if defined(CONFIG_TSEC_ENET) 739 #define CONFIG_MII /* MII PHY management */ 740 #define CONFIG_TSEC1 741 #define CONFIG_TSEC1_NAME "eTSEC1" 742 #define CONFIG_TSEC2 743 #define CONFIG_TSEC2_NAME "eTSEC2" 744 #define CONFIG_TSEC3 745 #define CONFIG_TSEC3_NAME "eTSEC3" 746 747 #define TSEC1_PHY_ADDR 2 748 #define TSEC2_PHY_ADDR 0 749 #define TSEC3_PHY_ADDR 1 750 751 #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 752 #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 753 #define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 754 755 #define TSEC1_PHYIDX 0 756 #define TSEC2_PHYIDX 0 757 #define TSEC3_PHYIDX 0 758 759 #define CONFIG_ETHPRIME "eTSEC1" 760 761 #define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */ 762 763 #define CONFIG_HAS_ETH0 764 #define CONFIG_HAS_ETH1 765 #define CONFIG_HAS_ETH2 766 #endif /* CONFIG_TSEC_ENET */ 767 768 #ifdef CONFIG_QE 769 /* QE microcode/firmware address */ 770 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR 771 #define CONFIG_SYS_QE_FMAN_FW_ADDR 0xefec0000 772 #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 773 #endif /* CONFIG_QE */ 774 775 #ifdef CONFIG_P1025RDB 776 /* 777 * QE UEC ethernet configuration 778 */ 779 #define CONFIG_MIIM_ADDRESS (CONFIG_SYS_CCSRBAR + 0x82120) 780 781 #undef CONFIG_UEC_ETH 782 #define CONFIG_PHY_MODE_NEED_CHANGE 783 784 #define CONFIG_UEC_ETH1 /* ETH1 */ 785 #define CONFIG_HAS_ETH0 786 787 #ifdef CONFIG_UEC_ETH1 788 #define CONFIG_SYS_UEC1_UCC_NUM 0 /* UCC1 */ 789 #define CONFIG_SYS_UEC1_RX_CLK QE_CLK12 /* CLK12 for MII */ 790 #define CONFIG_SYS_UEC1_TX_CLK QE_CLK9 /* CLK9 for MII */ 791 #define CONFIG_SYS_UEC1_ETH_TYPE FAST_ETH 792 #define CONFIG_SYS_UEC1_PHY_ADDR 0x0 /* 0x0 for MII */ 793 #define CONFIG_SYS_UEC1_INTERFACE_TYPE PHY_INTERFACE_MODE_RMII 794 #define CONFIG_SYS_UEC1_INTERFACE_SPEED 100 795 #endif /* CONFIG_UEC_ETH1 */ 796 797 #define CONFIG_UEC_ETH5 /* ETH5 */ 798 #define CONFIG_HAS_ETH1 799 800 #ifdef CONFIG_UEC_ETH5 801 #define CONFIG_SYS_UEC5_UCC_NUM 4 /* UCC5 */ 802 #define CONFIG_SYS_UEC5_RX_CLK QE_CLK_NONE 803 #define CONFIG_SYS_UEC5_TX_CLK QE_CLK13 /* CLK 13 for RMII */ 804 #define CONFIG_SYS_UEC5_ETH_TYPE FAST_ETH 805 #define CONFIG_SYS_UEC5_PHY_ADDR 0x3 /* 0x3 for RMII */ 806 #define CONFIG_SYS_UEC5_INTERFACE_TYPE PHY_INTERFACE_MODE_RMII 807 #define CONFIG_SYS_UEC5_INTERFACE_SPEED 100 808 #endif /* CONFIG_UEC_ETH5 */ 809 #endif /* CONFIG_P1025RDB */ 810 811 /* 812 * Environment 813 */ 814 #ifdef CONFIG_SPIFLASH 815 #define CONFIG_ENV_IS_IN_SPI_FLASH 816 #define CONFIG_ENV_SPI_BUS 0 817 #define CONFIG_ENV_SPI_CS 0 818 #define CONFIG_ENV_SPI_MAX_HZ 10000000 819 #define CONFIG_ENV_SPI_MODE 0 820 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */ 821 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ 822 #define CONFIG_ENV_SECT_SIZE 0x10000 823 #elif defined(CONFIG_SDCARD) 824 #define CONFIG_ENV_IS_IN_MMC 825 #define CONFIG_FSL_FIXED_MMC_LOCATION 826 #define CONFIG_ENV_SIZE 0x2000 827 #define CONFIG_SYS_MMC_ENV_DEV 0 828 #elif defined(CONFIG_NAND) 829 #ifdef CONFIG_TPL_BUILD 830 #define CONFIG_ENV_SIZE 0x2000 831 #define CONFIG_ENV_ADDR (CONFIG_SYS_INIT_L2_ADDR + (160 << 10)) 832 #else 833 #define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE 834 #endif 835 #define CONFIG_ENV_IS_IN_NAND 836 #define CONFIG_ENV_OFFSET (1024 * 1024) 837 #define CONFIG_ENV_RANGE (3 * CONFIG_ENV_SIZE) 838 #elif defined(CONFIG_SYS_RAMBOOT) 839 #define CONFIG_ENV_IS_NOWHERE /* Store ENV in memory only */ 840 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) 841 #define CONFIG_ENV_SIZE 0x2000 842 #else 843 #define CONFIG_ENV_IS_IN_FLASH 844 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) 845 #define CONFIG_ENV_SIZE 0x2000 846 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ 847 #endif 848 849 #define CONFIG_LOADS_ECHO /* echo on for serial download */ 850 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ 851 852 /* 853 * Command line configuration. 854 */ 855 #include <config_cmd_default.h> 856 857 #define CONFIG_CMD_IRQ 858 #define CONFIG_CMD_PING 859 #define CONFIG_CMD_I2C 860 #define CONFIG_CMD_MII 861 #define CONFIG_CMD_DATE 862 #define CONFIG_CMD_ELF 863 #define CONFIG_CMD_SETEXPR 864 #define CONFIG_CMD_REGINFO 865 866 /* 867 * USB 868 */ 869 #define CONFIG_HAS_FSL_DR_USB 870 871 #if defined(CONFIG_HAS_FSL_DR_USB) 872 #define CONFIG_USB_EHCI 873 874 #ifdef CONFIG_USB_EHCI 875 #define CONFIG_CMD_USB 876 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 877 #define CONFIG_USB_EHCI_FSL 878 #define CONFIG_USB_STORAGE 879 #endif 880 #endif 881 882 #define CONFIG_MMC 883 884 #ifdef CONFIG_MMC 885 #define CONFIG_FSL_ESDHC 886 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR 887 #define CONFIG_CMD_MMC 888 #define CONFIG_GENERIC_MMC 889 #endif 890 891 #if defined(CONFIG_MMC) || defined(CONFIG_USB_EHCI) \ 892 || defined(CONFIG_FSL_SATA) 893 #define CONFIG_CMD_EXT2 894 #define CONFIG_CMD_FAT 895 #define CONFIG_DOS_PARTITION 896 #endif 897 898 #undef CONFIG_WATCHDOG /* watchdog disabled */ 899 900 /* 901 * Miscellaneous configurable options 902 */ 903 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 904 #define CONFIG_CMDLINE_EDITING /* Command-line editing */ 905 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 906 #if defined(CONFIG_CMD_KGDB) 907 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 908 #else 909 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 910 #endif 911 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) 912 /* Print Buffer Size */ 913 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 914 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */ 915 916 /* 917 * For booting Linux, the board info and command line data 918 * have to be in the first 64 MB of memory, since this is 919 * the maximum mapped by the Linux kernel during initialization. 920 */ 921 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory for Linux*/ 922 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 923 924 #if defined(CONFIG_CMD_KGDB) 925 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 926 #endif 927 928 /* 929 * Environment Configuration 930 */ 931 #define CONFIG_HOSTNAME unknown 932 #define CONFIG_ROOTPATH "/opt/nfsroot" 933 #define CONFIG_BOOTFILE "uImage" 934 #define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */ 935 936 /* default location for tftp and bootm */ 937 #define CONFIG_LOADADDR 1000000 938 939 #define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */ 940 #define CONFIG_BOOTARGS /* the boot command will set bootargs */ 941 942 #define CONFIG_BAUDRATE 115200 943 944 #ifdef __SW_BOOT_NOR 945 #define __NOR_RST_CMD \ 946 norboot=i2c dev 1; i2c mw 18 1 __SW_BOOT_NOR 1; \ 947 i2c mw 18 3 __SW_BOOT_MASK 1; reset 948 #endif 949 #ifdef __SW_BOOT_SPI 950 #define __SPI_RST_CMD \ 951 spiboot=i2c dev 1; i2c mw 18 1 __SW_BOOT_SPI 1; \ 952 i2c mw 18 3 __SW_BOOT_MASK 1; reset 953 #endif 954 #ifdef __SW_BOOT_SD 955 #define __SD_RST_CMD \ 956 sdboot=i2c dev 1; i2c mw 18 1 __SW_BOOT_SD 1; \ 957 i2c mw 18 3 __SW_BOOT_MASK 1; reset 958 #endif 959 #ifdef __SW_BOOT_NAND 960 #define __NAND_RST_CMD \ 961 nandboot=i2c dev 1; i2c mw 18 1 __SW_BOOT_NAND 1; \ 962 i2c mw 18 3 __SW_BOOT_MASK 1; reset 963 #endif 964 #ifdef __SW_BOOT_PCIE 965 #define __PCIE_RST_CMD \ 966 pciboot=i2c dev 1; i2c mw 18 1 __SW_BOOT_PCIE 1; \ 967 i2c mw 18 3 __SW_BOOT_MASK 1; reset 968 #endif 969 970 #define CONFIG_EXTRA_ENV_SETTINGS \ 971 "netdev=eth0\0" \ 972 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ 973 "loadaddr=1000000\0" \ 974 "bootfile=uImage\0" \ 975 "tftpflash=tftpboot $loadaddr $uboot; " \ 976 "protect off " __stringify(CONFIG_SYS_TEXT_BASE) " +$filesize; " \ 977 "erase " __stringify(CONFIG_SYS_TEXT_BASE) " +$filesize; " \ 978 "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) " $filesize; " \ 979 "protect on " __stringify(CONFIG_SYS_TEXT_BASE) " +$filesize; " \ 980 "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) " $filesize\0" \ 981 "hwconfig=usb1:dr_mode=host,phy_type=ulpi\0" \ 982 "consoledev=ttyS0\0" \ 983 "ramdiskaddr=2000000\0" \ 984 "ramdiskfile=rootfs.ext2.gz.uboot\0" \ 985 "fdtaddr=c00000\0" \ 986 "bdev=sda1\0" \ 987 "jffs2nor=mtdblock3\0" \ 988 "norbootaddr=ef080000\0" \ 989 "norfdtaddr=ef040000\0" \ 990 "jffs2nand=mtdblock9\0" \ 991 "nandbootaddr=100000\0" \ 992 "nandfdtaddr=80000\0" \ 993 "ramdisk_size=120000\0" \ 994 "map_lowernorbank=i2c dev 1; i2c mw 18 1 02 1; i2c mw 18 3 fd 1\0" \ 995 "map_uppernorbank=i2c dev 1; i2c mw 18 1 00 1; i2c mw 18 3 fd 1\0" \ 996 __stringify(__NOR_RST_CMD)"\0" \ 997 __stringify(__SPI_RST_CMD)"\0" \ 998 __stringify(__SD_RST_CMD)"\0" \ 999 __stringify(__NAND_RST_CMD)"\0" \ 1000 __stringify(__PCIE_RST_CMD)"\0" 1001 1002 #define CONFIG_NFSBOOTCOMMAND \ 1003 "setenv bootargs root=/dev/nfs rw " \ 1004 "nfsroot=$serverip:$rootpath " \ 1005 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 1006 "console=$consoledev,$baudrate $othbootargs;" \ 1007 "tftp $loadaddr $bootfile;" \ 1008 "tftp $fdtaddr $fdtfile;" \ 1009 "bootm $loadaddr - $fdtaddr" 1010 1011 #define CONFIG_HDBOOT \ 1012 "setenv bootargs root=/dev/$bdev rw rootdelay=30 " \ 1013 "console=$consoledev,$baudrate $othbootargs;" \ 1014 "usb start;" \ 1015 "ext2load usb 0:1 $loadaddr /boot/$bootfile;" \ 1016 "ext2load usb 0:1 $fdtaddr /boot/$fdtfile;" \ 1017 "bootm $loadaddr - $fdtaddr" 1018 1019 #define CONFIG_USB_FAT_BOOT \ 1020 "setenv bootargs root=/dev/ram rw " \ 1021 "console=$consoledev,$baudrate $othbootargs " \ 1022 "ramdisk_size=$ramdisk_size;" \ 1023 "usb start;" \ 1024 "fatload usb 0:2 $loadaddr $bootfile;" \ 1025 "fatload usb 0:2 $fdtaddr $fdtfile;" \ 1026 "fatload usb 0:2 $ramdiskaddr $ramdiskfile;" \ 1027 "bootm $loadaddr $ramdiskaddr $fdtaddr" 1028 1029 #define CONFIG_USB_EXT2_BOOT \ 1030 "setenv bootargs root=/dev/ram rw " \ 1031 "console=$consoledev,$baudrate $othbootargs " \ 1032 "ramdisk_size=$ramdisk_size;" \ 1033 "usb start;" \ 1034 "ext2load usb 0:4 $loadaddr $bootfile;" \ 1035 "ext2load usb 0:4 $fdtaddr $fdtfile;" \ 1036 "ext2load usb 0:4 $ramdiskaddr $ramdiskfile;" \ 1037 "bootm $loadaddr $ramdiskaddr $fdtaddr" 1038 1039 #define CONFIG_NORBOOT \ 1040 "setenv bootargs root=/dev/$jffs2nor rw " \ 1041 "console=$consoledev,$baudrate rootfstype=jffs2 $othbootargs;" \ 1042 "bootm $norbootaddr - $norfdtaddr" 1043 1044 #define CONFIG_RAMBOOTCOMMAND \ 1045 "setenv bootargs root=/dev/ram rw " \ 1046 "console=$consoledev,$baudrate $othbootargs " \ 1047 "ramdisk_size=$ramdisk_size;" \ 1048 "tftp $ramdiskaddr $ramdiskfile;" \ 1049 "tftp $loadaddr $bootfile;" \ 1050 "tftp $fdtaddr $fdtfile;" \ 1051 "bootm $loadaddr $ramdiskaddr $fdtaddr" 1052 1053 #define CONFIG_BOOTCOMMAND CONFIG_HDBOOT 1054 1055 #endif /* __CONFIG_H */ 1056