1 /* 2 * Copyright 2010-2011 Freescale Semiconductor, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 /* 8 * QorIQ RDB boards configuration file 9 */ 10 #ifndef __CONFIG_H 11 #define __CONFIG_H 12 13 #define CONFIG_SYS_GENERIC_BOARD 14 #define CONFIG_DISPLAY_BOARDINFO 15 16 #ifdef CONFIG_36BIT 17 #define CONFIG_PHYS_64BIT 18 #endif 19 20 #if defined(CONFIG_P1020MBG) 21 #define CONFIG_BOARDNAME "P1020MBG-PC" 22 #define CONFIG_P1020 23 #define CONFIG_VSC7385_ENET 24 #define CONFIG_SLIC 25 #define __SW_BOOT_MASK 0x03 26 #define __SW_BOOT_NOR 0xe4 27 #define __SW_BOOT_SD 0x54 28 #define CONFIG_SYS_L2_SIZE (256 << 10) 29 #endif 30 31 #if defined(CONFIG_P1020UTM) 32 #define CONFIG_BOARDNAME "P1020UTM-PC" 33 #define CONFIG_P1020 34 #define __SW_BOOT_MASK 0x03 35 #define __SW_BOOT_NOR 0xe0 36 #define __SW_BOOT_SD 0x50 37 #define CONFIG_SYS_L2_SIZE (256 << 10) 38 #endif 39 40 #if defined(CONFIG_P1020RDB_PC) 41 #define CONFIG_BOARDNAME "P1020RDB-PC" 42 #define CONFIG_NAND_FSL_ELBC 43 #define CONFIG_P1020 44 #define CONFIG_SPI_FLASH 45 #define CONFIG_VSC7385_ENET 46 #define CONFIG_SLIC 47 #define __SW_BOOT_MASK 0x03 48 #define __SW_BOOT_NOR 0x5c 49 #define __SW_BOOT_SPI 0x1c 50 #define __SW_BOOT_SD 0x9c 51 #define __SW_BOOT_NAND 0xec 52 #define __SW_BOOT_PCIE 0x6c 53 #define CONFIG_SYS_L2_SIZE (256 << 10) 54 #endif 55 56 /* 57 * P1020RDB-PD board has user selectable switches for evaluating different 58 * frequency and boot options for the P1020 device. The table that 59 * follow describe the available options. The front six binary number was in 60 * accordance with SW3[1:6]. 61 * 111101 533 533 267 667 NOR Core0 boot; Core1 hold-off 62 * 101101 667 667 333 667 NOR Core0 boot; Core1 hold-off 63 * 011001 800 800 400 667 NOR Core0 boot; Core1 hold-off 64 * 001001 800 800 400 667 SD/MMC Core0 boot; Core1 hold-off 65 * 001101 800 800 400 667 SPI Core0 boot; Core1 hold-off 66 * 010001 800 800 400 667 NAND Core0 boot; Core1 hold-off 67 * 011101 800 800 400 667 PCIe-2 Core0 boot; Core1 hold-off 68 */ 69 #if defined(CONFIG_P1020RDB_PD) 70 #define CONFIG_BOARDNAME "P1020RDB-PD" 71 #define CONFIG_NAND_FSL_ELBC 72 #define CONFIG_P1020 73 #define CONFIG_SPI_FLASH 74 #define CONFIG_VSC7385_ENET 75 #define CONFIG_SLIC 76 #define __SW_BOOT_MASK 0x03 77 #define __SW_BOOT_NOR 0x64 78 #define __SW_BOOT_SPI 0x34 79 #define __SW_BOOT_SD 0x24 80 #define __SW_BOOT_NAND 0x44 81 #define __SW_BOOT_PCIE 0x74 82 #define CONFIG_SYS_L2_SIZE (256 << 10) 83 #endif 84 85 #if defined(CONFIG_P1021RDB) 86 #define CONFIG_BOARDNAME "P1021RDB-PC" 87 #define CONFIG_NAND_FSL_ELBC 88 #define CONFIG_P1021 89 #define CONFIG_QE 90 #define CONFIG_SPI_FLASH 91 #define CONFIG_VSC7385_ENET 92 #define CONFIG_SYS_LBC_LBCR 0x00080000 /* Implement conversion of 93 addresses in the LBC */ 94 #define __SW_BOOT_MASK 0x03 95 #define __SW_BOOT_NOR 0x5c 96 #define __SW_BOOT_SPI 0x1c 97 #define __SW_BOOT_SD 0x9c 98 #define __SW_BOOT_NAND 0xec 99 #define __SW_BOOT_PCIE 0x6c 100 #define CONFIG_SYS_L2_SIZE (256 << 10) 101 #endif 102 103 #if defined(CONFIG_P1024RDB) 104 #define CONFIG_BOARDNAME "P1024RDB" 105 #define CONFIG_NAND_FSL_ELBC 106 #define CONFIG_P1024 107 #define CONFIG_SLIC 108 #define CONFIG_SPI_FLASH 109 #define __SW_BOOT_MASK 0xf3 110 #define __SW_BOOT_NOR 0x00 111 #define __SW_BOOT_SPI 0x08 112 #define __SW_BOOT_SD 0x04 113 #define __SW_BOOT_NAND 0x0c 114 #define CONFIG_SYS_L2_SIZE (256 << 10) 115 #endif 116 117 #if defined(CONFIG_P1025RDB) 118 #define CONFIG_BOARDNAME "P1025RDB" 119 #define CONFIG_NAND_FSL_ELBC 120 #define CONFIG_P1025 121 #define CONFIG_QE 122 #define CONFIG_SLIC 123 #define CONFIG_SPI_FLASH 124 125 #define CONFIG_SYS_LBC_LBCR 0x00080000 /* Implement conversion of 126 addresses in the LBC */ 127 #define __SW_BOOT_MASK 0xf3 128 #define __SW_BOOT_NOR 0x00 129 #define __SW_BOOT_SPI 0x08 130 #define __SW_BOOT_SD 0x04 131 #define __SW_BOOT_NAND 0x0c 132 #define CONFIG_SYS_L2_SIZE (256 << 10) 133 #endif 134 135 #if defined(CONFIG_P2020RDB) 136 #define CONFIG_BOARDNAME "P2020RDB-PCA" 137 #define CONFIG_NAND_FSL_ELBC 138 #define CONFIG_P2020 139 #define CONFIG_SPI_FLASH 140 #define CONFIG_VSC7385_ENET 141 #define __SW_BOOT_MASK 0x03 142 #define __SW_BOOT_NOR 0xc8 143 #define __SW_BOOT_SPI 0x28 144 #define __SW_BOOT_SD 0x68 /* or 0x18 */ 145 #define __SW_BOOT_NAND 0xe8 146 #define __SW_BOOT_PCIE 0xa8 147 #define CONFIG_SYS_L2_SIZE (512 << 10) 148 #endif 149 150 #ifdef CONFIG_SDCARD 151 #define CONFIG_SPL 152 #define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT 153 #define CONFIG_SPL_ENV_SUPPORT 154 #define CONFIG_SPL_SERIAL_SUPPORT 155 #define CONFIG_SPL_MMC_SUPPORT 156 #define CONFIG_SPL_MMC_MINIMAL 157 #define CONFIG_SPL_FLUSH_IMAGE 158 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 159 #define CONFIG_SPL_LIBGENERIC_SUPPORT 160 #define CONFIG_SPL_LIBCOMMON_SUPPORT 161 #define CONFIG_SPL_I2C_SUPPORT 162 #define CONFIG_FSL_LAW /* Use common FSL init code */ 163 #define CONFIG_SYS_TEXT_BASE 0x11001000 164 #define CONFIG_SPL_TEXT_BASE 0xf8f81000 165 #define CONFIG_SPL_PAD_TO 0x20000 166 #define CONFIG_SPL_MAX_SIZE (128 * 1024) 167 #define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10) 168 #define CONFIG_SYS_MMC_U_BOOT_DST (0x11000000) 169 #define CONFIG_SYS_MMC_U_BOOT_START (0x11000000) 170 #define CONFIG_SYS_MMC_U_BOOT_OFFS (128 << 10) 171 #define CONFIG_SYS_MPC85XX_NO_RESETVEC 172 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds" 173 #define CONFIG_SPL_MMC_BOOT 174 #ifdef CONFIG_SPL_BUILD 175 #define CONFIG_SPL_COMMON_INIT_DDR 176 #endif 177 #endif 178 179 #ifdef CONFIG_SPIFLASH 180 #define CONFIG_SPL 181 #define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT 182 #define CONFIG_SPL_ENV_SUPPORT 183 #define CONFIG_SPL_SERIAL_SUPPORT 184 #define CONFIG_SPL_SPI_SUPPORT 185 #define CONFIG_SPL_SPI_FLASH_SUPPORT 186 #define CONFIG_SPL_SPI_FLASH_MINIMAL 187 #define CONFIG_SPL_FLUSH_IMAGE 188 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 189 #define CONFIG_SPL_LIBGENERIC_SUPPORT 190 #define CONFIG_SPL_LIBCOMMON_SUPPORT 191 #define CONFIG_SPL_I2C_SUPPORT 192 #define CONFIG_FSL_LAW /* Use common FSL init code */ 193 #define CONFIG_SYS_TEXT_BASE 0x11001000 194 #define CONFIG_SPL_TEXT_BASE 0xf8f81000 195 #define CONFIG_SPL_PAD_TO 0x20000 196 #define CONFIG_SPL_MAX_SIZE (128 * 1024) 197 #define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (768 << 10) 198 #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x11000000) 199 #define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x11000000) 200 #define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (128 << 10) 201 #define CONFIG_SYS_MPC85XX_NO_RESETVEC 202 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds" 203 #define CONFIG_SPL_SPI_BOOT 204 #ifdef CONFIG_SPL_BUILD 205 #define CONFIG_SPL_COMMON_INIT_DDR 206 #endif 207 #endif 208 209 #ifdef CONFIG_NAND 210 #define CONFIG_SPL 211 #define CONFIG_TPL 212 #ifdef CONFIG_TPL_BUILD 213 #define CONFIG_SPL_NAND_BOOT 214 #define CONFIG_SPL_FLUSH_IMAGE 215 #define CONFIG_SPL_ENV_SUPPORT 216 #define CONFIG_SPL_NAND_INIT 217 #define CONFIG_SPL_SERIAL_SUPPORT 218 #define CONFIG_SPL_LIBGENERIC_SUPPORT 219 #define CONFIG_SPL_LIBCOMMON_SUPPORT 220 #define CONFIG_SPL_I2C_SUPPORT 221 #define CONFIG_SPL_NAND_SUPPORT 222 #define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT 223 #define CONFIG_SPL_COMMON_INIT_DDR 224 #define CONFIG_SPL_MAX_SIZE (128 << 10) 225 #define CONFIG_SPL_TEXT_BASE 0xf8f81000 226 #define CONFIG_SYS_MPC85XX_NO_RESETVEC 227 #define CONFIG_SYS_NAND_U_BOOT_SIZE (832 << 10) 228 #define CONFIG_SYS_NAND_U_BOOT_DST (0x11000000) 229 #define CONFIG_SYS_NAND_U_BOOT_START (0x11000000) 230 #define CONFIG_SYS_NAND_U_BOOT_OFFS ((128 + 128) << 10) 231 #elif defined(CONFIG_SPL_BUILD) 232 #define CONFIG_SPL_INIT_MINIMAL 233 #define CONFIG_SPL_SERIAL_SUPPORT 234 #define CONFIG_SPL_NAND_SUPPORT 235 #define CONFIG_SPL_FLUSH_IMAGE 236 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 237 #define CONFIG_SPL_TEXT_BASE 0xff800000 238 #define CONFIG_SPL_MAX_SIZE 4096 239 #define CONFIG_SYS_NAND_U_BOOT_SIZE (128 << 10) 240 #define CONFIG_SYS_NAND_U_BOOT_DST 0xf8f80000 241 #define CONFIG_SYS_NAND_U_BOOT_START 0xf8f80000 242 #define CONFIG_SYS_NAND_U_BOOT_OFFS (128 << 10) 243 #endif /* not CONFIG_TPL_BUILD */ 244 245 #define CONFIG_SPL_PAD_TO 0x20000 246 #define CONFIG_TPL_PAD_TO 0x20000 247 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 248 #define CONFIG_SYS_TEXT_BASE 0x11001000 249 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds" 250 #endif 251 252 #ifndef CONFIG_SYS_TEXT_BASE 253 #define CONFIG_SYS_TEXT_BASE 0xeff40000 254 #endif 255 256 #ifndef CONFIG_RESET_VECTOR_ADDRESS 257 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc 258 #endif 259 260 #ifndef CONFIG_SYS_MONITOR_BASE 261 #ifdef CONFIG_SPL_BUILD 262 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE 263 #else 264 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 265 #endif 266 #endif 267 268 /* High Level Configuration Options */ 269 #define CONFIG_BOOKE 270 #define CONFIG_E500 271 272 #define CONFIG_MP 273 274 #define CONFIG_FSL_ELBC 275 #define CONFIG_PCI 276 #define CONFIG_PCIE1 /* PCIE controler 1 (slot 1) */ 277 #define CONFIG_PCIE2 /* PCIE controler 2 (slot 2) */ 278 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ 279 #define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */ 280 #define CONFIG_FSL_PCIE_RESET /* need PCIe reset errata */ 281 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ 282 283 #define CONFIG_FSL_LAW 284 #define CONFIG_TSEC_ENET /* tsec ethernet support */ 285 #define CONFIG_ENV_OVERWRITE 286 287 #define CONFIG_CMD_SATA 288 #define CONFIG_SATA_SIL 289 #define CONFIG_SYS_SATA_MAX_DEVICE 2 290 #define CONFIG_LIBATA 291 #define CONFIG_LBA48 292 293 #if defined(CONFIG_P2020RDB) 294 #define CONFIG_SYS_CLK_FREQ 100000000 295 #else 296 #define CONFIG_SYS_CLK_FREQ 66666666 297 #endif 298 #define CONFIG_DDR_CLK_FREQ 66666666 299 300 #define CONFIG_HWCONFIG 301 /* 302 * These can be toggled for performance analysis, otherwise use default. 303 */ 304 #define CONFIG_L2_CACHE 305 #define CONFIG_BTB 306 307 #define CONFIG_BOARD_EARLY_INIT_F /* Call board_pre_init */ 308 309 #define CONFIG_ENABLE_36BIT_PHYS 310 311 #ifdef CONFIG_PHYS_64BIT 312 #define CONFIG_ADDR_MAP 1 313 #define CONFIG_SYS_NUM_ADDR_MAP 16 /* number of TLB1 entries */ 314 #endif 315 316 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ 317 #define CONFIG_SYS_MEMTEST_END 0x1fffffff 318 #define CONFIG_PANIC_HANG /* do not reset board on panic */ 319 320 #define CONFIG_SYS_CCSRBAR 0xffe00000 321 #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR 322 323 /* IN case of NAND bootloader relocate CCSRBAR in RAMboot code not in the 4k 324 SPL code*/ 325 #ifdef CONFIG_SPL_BUILD 326 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE 327 #endif 328 329 /* DDR Setup */ 330 #define CONFIG_SYS_FSL_DDR3 331 #define CONFIG_SYS_DDR_RAW_TIMING 332 #define CONFIG_DDR_SPD 333 #define CONFIG_SYS_SPD_BUS_NUM 1 334 #define SPD_EEPROM_ADDRESS 0x52 335 #undef CONFIG_FSL_DDR_INTERACTIVE 336 337 #if (defined(CONFIG_P1020MBG) || defined(CONFIG_P1020RDB_PD)) 338 #define CONFIG_SYS_SDRAM_SIZE_LAW LAW_SIZE_2G 339 #define CONFIG_CHIP_SELECTS_PER_CTRL 2 340 #else 341 #define CONFIG_SYS_SDRAM_SIZE_LAW LAW_SIZE_1G 342 #define CONFIG_CHIP_SELECTS_PER_CTRL 1 343 #endif 344 #define CONFIG_SYS_SDRAM_SIZE (1u << (CONFIG_SYS_SDRAM_SIZE_LAW - 19)) 345 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 346 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 347 348 #define CONFIG_NUM_DDR_CONTROLLERS 1 349 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 350 351 /* Default settings for DDR3 */ 352 #ifndef CONFIG_P2020RDB 353 #define CONFIG_SYS_DDR_CS0_BNDS 0x0000003f 354 #define CONFIG_SYS_DDR_CS0_CONFIG 0x80014302 355 #define CONFIG_SYS_DDR_CS0_CONFIG_2 0x00000000 356 #define CONFIG_SYS_DDR_CS1_BNDS 0x0040007f 357 #define CONFIG_SYS_DDR_CS1_CONFIG 0x80014302 358 #define CONFIG_SYS_DDR_CS1_CONFIG_2 0x00000000 359 360 #define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef 361 #define CONFIG_SYS_DDR_INIT_ADDR 0x00000000 362 #define CONFIG_SYS_DDR_INIT_EXT_ADDR 0x00000000 363 #define CONFIG_SYS_DDR_MODE_CONTROL 0x00000000 364 365 #define CONFIG_SYS_DDR_ZQ_CONTROL 0x89080600 366 #define CONFIG_SYS_DDR_WRLVL_CONTROL 0x8655A608 367 #define CONFIG_SYS_DDR_SR_CNTR 0x00000000 368 #define CONFIG_SYS_DDR_RCW_1 0x00000000 369 #define CONFIG_SYS_DDR_RCW_2 0x00000000 370 #define CONFIG_SYS_DDR_CONTROL 0xC70C0000 /* Type = DDR3 */ 371 #define CONFIG_SYS_DDR_CONTROL_2 0x04401050 372 #define CONFIG_SYS_DDR_TIMING_4 0x00220001 373 #define CONFIG_SYS_DDR_TIMING_5 0x03402400 374 375 #define CONFIG_SYS_DDR_TIMING_3 0x00020000 376 #define CONFIG_SYS_DDR_TIMING_0 0x00330004 377 #define CONFIG_SYS_DDR_TIMING_1 0x6f6B4846 378 #define CONFIG_SYS_DDR_TIMING_2 0x0FA8C8CF 379 #define CONFIG_SYS_DDR_CLK_CTRL 0x03000000 380 #define CONFIG_SYS_DDR_MODE_1 0x40461520 381 #define CONFIG_SYS_DDR_MODE_2 0x8000c000 382 #define CONFIG_SYS_DDR_INTERVAL 0x0C300000 383 #endif 384 385 #undef CONFIG_CLOCKS_IN_MHZ 386 387 /* 388 * Memory map 389 * 390 * 0x0000_0000 0x7fff_ffff DDR Up to 2GB cacheable 391 * 0x8000_0000 0xdfff_ffff PCI Express Mem 1.5G non-cacheable(PCIe * 3) 392 * 0xec00_0000 0xefff_ffff NOR flash Up to 64M non-cacheable CS0/1 393 * 0xf8f8_0000 0xf8ff_ffff L2 SRAM Up to 512K cacheable 394 * (early boot only) 395 * 0xff80_0000 0xff80_7fff NAND flash 32K non-cacheable CS1/0 396 * 0xff98_0000 0xff98_ffff PMC 64K non-cacheable CS2 397 * 0xffa0_0000 0xffaf_ffff CPLD 1M non-cacheable CS3 398 * 0xffb0_0000 0xffbf_ffff VSC7385 switch 1M non-cacheable CS2 399 * 0xffc0_0000 0xffc3_ffff PCI IO range 256k non-cacheable 400 * 0xffd0_0000 0xffd0_3fff L1 for stack 16K cacheable 401 * 0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable 402 */ 403 404 405 /* 406 * Local Bus Definitions 407 */ 408 #if (defined(CONFIG_P1020MBG) || defined(CONFIG_P1020RDB_PD)) 409 #define CONFIG_SYS_MAX_FLASH_SECT 512 /* 64M */ 410 #define CONFIG_SYS_FLASH_BASE 0xec000000 411 #elif defined(CONFIG_P1020UTM) 412 #define CONFIG_SYS_MAX_FLASH_SECT 256 /* 32M */ 413 #define CONFIG_SYS_FLASH_BASE 0xee000000 414 #else 415 #define CONFIG_SYS_MAX_FLASH_SECT 128 /* 16M */ 416 #define CONFIG_SYS_FLASH_BASE 0xef000000 417 #endif 418 419 420 #ifdef CONFIG_PHYS_64BIT 421 #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE) 422 #else 423 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE 424 #endif 425 426 #define CONFIG_FLASH_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) \ 427 | BR_PS_16 | BR_V) 428 429 #define CONFIG_FLASH_OR_PRELIM 0xfc000ff7 430 431 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS} 432 #define CONFIG_SYS_FLASH_QUIET_TEST 433 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 434 435 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ 436 437 #undef CONFIG_SYS_FLASH_CHECKSUM 438 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 439 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 440 441 #define CONFIG_FLASH_CFI_DRIVER 442 #define CONFIG_SYS_FLASH_CFI 443 #define CONFIG_SYS_FLASH_EMPTY_INFO 444 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 445 446 /* Nand Flash */ 447 #ifdef CONFIG_NAND_FSL_ELBC 448 #define CONFIG_SYS_NAND_BASE 0xff800000 449 #ifdef CONFIG_PHYS_64BIT 450 #define CONFIG_SYS_NAND_BASE_PHYS 0xfff800000ull 451 #else 452 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE 453 #endif 454 455 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } 456 #define CONFIG_SYS_MAX_NAND_DEVICE 1 457 #define CONFIG_MTD_NAND_VERIFY_WRITE 458 #define CONFIG_CMD_NAND 459 #if defined(CONFIG_P1020RDB_PD) 460 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) 461 #else 462 #define CONFIG_SYS_NAND_BLOCK_SIZE (16 * 1024) 463 #endif 464 465 #define CONFIG_SYS_NAND_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 466 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ 467 | BR_PS_8 /* Port Size = 8 bit */ \ 468 | BR_MS_FCM /* MSEL = FCM */ \ 469 | BR_V) /* valid */ 470 #if defined(CONFIG_P1020RDB_PD) 471 #define CONFIG_SYS_NAND_OR_PRELIM (OR_AM_32KB \ 472 | OR_FCM_PGS /* Large Page*/ \ 473 | OR_FCM_CSCT \ 474 | OR_FCM_CST \ 475 | OR_FCM_CHT \ 476 | OR_FCM_SCY_1 \ 477 | OR_FCM_TRLX \ 478 | OR_FCM_EHTR) 479 #else 480 #define CONFIG_SYS_NAND_OR_PRELIM (OR_AM_32KB /* small page */ \ 481 | OR_FCM_CSCT \ 482 | OR_FCM_CST \ 483 | OR_FCM_CHT \ 484 | OR_FCM_SCY_1 \ 485 | OR_FCM_TRLX \ 486 | OR_FCM_EHTR) 487 #endif 488 #endif /* CONFIG_NAND_FSL_ELBC */ 489 490 #define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */ 491 492 #define CONFIG_SYS_INIT_RAM_LOCK 493 #define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* stack in RAM */ 494 #ifdef CONFIG_PHYS_64BIT 495 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf 496 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR 497 /* The assembler doesn't like typecast */ 498 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \ 499 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \ 500 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) 501 #else 502 /* Initial L1 address */ 503 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS CONFIG_SYS_INIT_RAM_ADDR 504 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0 505 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS 506 #endif 507 /* Size of used area in RAM */ 508 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 509 510 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ 511 GENERATED_GBL_DATA_SIZE) 512 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 513 514 #define CONFIG_SYS_MONITOR_LEN (768 * 1024) 515 #define CONFIG_SYS_MALLOC_LEN (1024 * 1024)/* Reserved for malloc */ 516 517 #define CONFIG_SYS_CPLD_BASE 0xffa00000 518 #ifdef CONFIG_PHYS_64BIT 519 #define CONFIG_SYS_CPLD_BASE_PHYS 0xfffa00000ull 520 #else 521 #define CONFIG_SYS_CPLD_BASE_PHYS CONFIG_SYS_CPLD_BASE 522 #endif 523 /* CPLD config size: 1Mb */ 524 #define CONFIG_CPLD_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE_PHYS) | \ 525 BR_PS_8 | BR_V) 526 #define CONFIG_CPLD_OR_PRELIM (0xfff009f7) 527 528 #define CONFIG_SYS_PMC_BASE 0xff980000 529 #define CONFIG_SYS_PMC_BASE_PHYS CONFIG_SYS_PMC_BASE 530 #define CONFIG_PMC_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_PMC_BASE_PHYS) | \ 531 BR_PS_8 | BR_V) 532 #define CONFIG_PMC_OR_PRELIM (OR_AM_64KB | OR_GPCM_CSNT | OR_GPCM_XACS | \ 533 OR_GPCM_SCY | OR_GPCM_TRLX | OR_GPCM_EHTR | \ 534 OR_GPCM_EAD) 535 536 #ifdef CONFIG_NAND 537 #define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Addr */ 538 #define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */ 539 #define CONFIG_SYS_BR1_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */ 540 #define CONFIG_SYS_OR1_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */ 541 #else 542 #define CONFIG_SYS_BR0_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */ 543 #define CONFIG_SYS_OR0_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */ 544 #ifdef CONFIG_NAND_FSL_ELBC 545 #define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Addr */ 546 #define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */ 547 #endif 548 #endif 549 #define CONFIG_SYS_BR3_PRELIM CONFIG_CPLD_BR_PRELIM /* CPLD Base Address */ 550 #define CONFIG_SYS_OR3_PRELIM CONFIG_CPLD_OR_PRELIM /* CPLD Options */ 551 552 553 /* Vsc7385 switch */ 554 #ifdef CONFIG_VSC7385_ENET 555 #define CONFIG_SYS_VSC7385_BASE 0xffb00000 556 557 #ifdef CONFIG_PHYS_64BIT 558 #define CONFIG_SYS_VSC7385_BASE_PHYS 0xfffb00000ull 559 #else 560 #define CONFIG_SYS_VSC7385_BASE_PHYS CONFIG_SYS_VSC7385_BASE 561 #endif 562 563 #define CONFIG_SYS_VSC7385_BR_PRELIM \ 564 (BR_PHYS_ADDR(CONFIG_SYS_VSC7385_BASE_PHYS) | BR_PS_8 | BR_V) 565 #define CONFIG_SYS_VSC7385_OR_PRELIM (OR_AM_128KB | OR_GPCM_CSNT | \ 566 OR_GPCM_XACS | OR_GPCM_SCY_15 | OR_GPCM_SETA | \ 567 OR_GPCM_TRLX | OR_GPCM_EHTR | OR_GPCM_EAD) 568 569 #define CONFIG_SYS_BR2_PRELIM CONFIG_SYS_VSC7385_BR_PRELIM 570 #define CONFIG_SYS_OR2_PRELIM CONFIG_SYS_VSC7385_OR_PRELIM 571 572 /* The size of the VSC7385 firmware image */ 573 #define CONFIG_VSC7385_IMAGE_SIZE 8192 574 #endif 575 576 /* 577 * Config the L2 Cache as L2 SRAM 578 */ 579 #if defined(CONFIG_SPL_BUILD) 580 #if defined(CONFIG_SDCARD) || defined(CONFIG_SPIFLASH) 581 #define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000 582 #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR 583 #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) 584 #define CONFIG_SPL_RELOC_TEXT_BASE 0xf8f81000 585 #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L2_ADDR + 112 * 1024) 586 #define CONFIG_SPL_RELOC_STACK (CONFIG_SYS_INIT_L2_ADDR + 116 * 1024) 587 #define CONFIG_SPL_RELOC_STACK_SIZE (32 << 10) 588 #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SYS_INIT_L2_ADDR + 148 * 1024) 589 #if defined(CONFIG_P2020RDB) 590 #define CONFIG_SPL_RELOC_MALLOC_SIZE (364 << 10) 591 #else 592 #define CONFIG_SPL_RELOC_MALLOC_SIZE (108 << 10) 593 #endif 594 #elif defined(CONFIG_NAND) 595 #ifdef CONFIG_TPL_BUILD 596 #define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000 597 #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR 598 #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) 599 #define CONFIG_SPL_RELOC_TEXT_BASE 0xf8f81000 600 #define CONFIG_SPL_RELOC_STACK (CONFIG_SYS_INIT_L2_ADDR + 192 * 1024) 601 #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SYS_INIT_L2_ADDR + 208 * 1024) 602 #define CONFIG_SPL_RELOC_MALLOC_SIZE (48 << 10) 603 #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L2_ADDR + 176 * 1024) 604 #else 605 #define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000 606 #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR 607 #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) 608 #define CONFIG_SPL_RELOC_TEXT_BASE (CONFIG_SYS_INIT_L2_END - 0x2000) 609 #define CONFIG_SPL_RELOC_STACK ((CONFIG_SYS_INIT_L2_END - 1) & ~0xF) 610 #endif /* CONFIG_TPL_BUILD */ 611 #endif 612 #endif 613 614 /* Serial Port - controlled on board with jumper J8 615 * open - index 2 616 * shorted - index 1 617 */ 618 #define CONFIG_CONS_INDEX 1 619 #undef CONFIG_SERIAL_SOFTWARE_FIFO 620 #define CONFIG_SYS_NS16550 621 #define CONFIG_SYS_NS16550_SERIAL 622 #define CONFIG_SYS_NS16550_REG_SIZE 1 623 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) 624 #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_INIT_MINIMAL) 625 #define CONFIG_NS16550_MIN_FUNCTIONS 626 #endif 627 628 #define CONFIG_SYS_BAUDRATE_TABLE \ 629 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} 630 631 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) 632 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) 633 634 /* Use the HUSH parser */ 635 #define CONFIG_SYS_HUSH_PARSER 636 637 /* 638 * Pass open firmware flat tree 639 */ 640 #define CONFIG_OF_LIBFDT 641 #define CONFIG_OF_BOARD_SETUP 642 #define CONFIG_OF_STDOUT_VIA_ALIAS 643 644 /* new uImage format support */ 645 #define CONFIG_FIT 646 #define CONFIG_FIT_VERBOSE /* enable fit_format_{error,warning}() */ 647 648 /* I2C */ 649 #define CONFIG_SYS_I2C 650 #define CONFIG_SYS_I2C_FSL 651 #define CONFIG_SYS_FSL_I2C_SPEED 400000 652 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 653 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 654 #define CONFIG_SYS_FSL_I2C2_SPEED 400000 655 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F 656 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100 657 #define CONFIG_SYS_I2C_NOPROBES { {0, 0x29} } 658 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x52 659 #define CONFIG_SYS_SPD_BUS_NUM 1 /* For rom_loc and flash bank */ 660 661 /* 662 * I2C2 EEPROM 663 */ 664 #undef CONFIG_ID_EEPROM 665 666 #define CONFIG_RTC_PT7C4338 667 #define CONFIG_SYS_I2C_RTC_ADDR 0x68 668 #define CONFIG_SYS_I2C_PCA9557_ADDR 0x18 669 670 /* enable read and write access to EEPROM */ 671 #define CONFIG_CMD_EEPROM 672 #define CONFIG_SYS_I2C_MULTI_EEPROMS 673 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 674 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 675 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 676 677 /* 678 * eSPI - Enhanced SPI 679 */ 680 #define CONFIG_HARD_SPI 681 #define CONFIG_FSL_ESPI 682 683 #if defined(CONFIG_SPI_FLASH) 684 #define CONFIG_SPI_FLASH_SPANSION 685 #define CONFIG_CMD_SF 686 #define CONFIG_SF_DEFAULT_SPEED 10000000 687 #define CONFIG_SF_DEFAULT_MODE 0 688 #endif 689 690 #if defined(CONFIG_PCI) 691 /* 692 * General PCI 693 * Memory space is mapped 1-1, but I/O space must start from 0. 694 */ 695 696 /* controller 2, direct to uli, tgtid 2, Base address 9000 */ 697 #define CONFIG_SYS_PCIE2_NAME "PCIe SLOT" 698 #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000 699 #ifdef CONFIG_PHYS_64BIT 700 #define CONFIG_SYS_PCIE2_MEM_BUS 0xc0000000 701 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull 702 #else 703 #define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000 704 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000 705 #endif 706 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */ 707 #define CONFIG_SYS_PCIE2_IO_VIRT 0xffc10000 708 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 709 #ifdef CONFIG_PHYS_64BIT 710 #define CONFIG_SYS_PCIE2_IO_PHYS 0xfffc10000ull 711 #else 712 #define CONFIG_SYS_PCIE2_IO_PHYS 0xffc10000 713 #endif 714 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ 715 716 /* controller 1, Slot 2, tgtid 1, Base address a000 */ 717 #define CONFIG_SYS_PCIE1_NAME "mini PCIe SLOT" 718 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 719 #ifdef CONFIG_PHYS_64BIT 720 #define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000 721 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull 722 #else 723 #define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000 724 #define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000 725 #endif 726 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ 727 #define CONFIG_SYS_PCIE1_IO_VIRT 0xffc00000 728 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 729 #ifdef CONFIG_PHYS_64BIT 730 #define CONFIG_SYS_PCIE1_IO_PHYS 0xfffc00000ull 731 #else 732 #define CONFIG_SYS_PCIE1_IO_PHYS 0xffc00000 733 #endif 734 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ 735 736 #define CONFIG_PCI_PNP /* do pci plug-and-play */ 737 #define CONFIG_E1000 /* Defind e1000 pci Ethernet card*/ 738 #define CONFIG_CMD_PCI 739 #define CONFIG_CMD_NET 740 741 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 742 #define CONFIG_DOS_PARTITION 743 #endif /* CONFIG_PCI */ 744 745 #if defined(CONFIG_TSEC_ENET) 746 #define CONFIG_MII /* MII PHY management */ 747 #define CONFIG_TSEC1 748 #define CONFIG_TSEC1_NAME "eTSEC1" 749 #define CONFIG_TSEC2 750 #define CONFIG_TSEC2_NAME "eTSEC2" 751 #define CONFIG_TSEC3 752 #define CONFIG_TSEC3_NAME "eTSEC3" 753 754 #define TSEC1_PHY_ADDR 2 755 #define TSEC2_PHY_ADDR 0 756 #define TSEC3_PHY_ADDR 1 757 758 #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 759 #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 760 #define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 761 762 #define TSEC1_PHYIDX 0 763 #define TSEC2_PHYIDX 0 764 #define TSEC3_PHYIDX 0 765 766 #define CONFIG_ETHPRIME "eTSEC1" 767 768 #define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */ 769 770 #define CONFIG_HAS_ETH0 771 #define CONFIG_HAS_ETH1 772 #define CONFIG_HAS_ETH2 773 #endif /* CONFIG_TSEC_ENET */ 774 775 #ifdef CONFIG_QE 776 /* QE microcode/firmware address */ 777 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR 778 #define CONFIG_SYS_QE_FW_ADDR 0xefec0000 779 #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 780 #endif /* CONFIG_QE */ 781 782 #ifdef CONFIG_P1025RDB 783 /* 784 * QE UEC ethernet configuration 785 */ 786 #define CONFIG_MIIM_ADDRESS (CONFIG_SYS_CCSRBAR + 0x82120) 787 788 #undef CONFIG_UEC_ETH 789 #define CONFIG_PHY_MODE_NEED_CHANGE 790 791 #define CONFIG_UEC_ETH1 /* ETH1 */ 792 #define CONFIG_HAS_ETH0 793 794 #ifdef CONFIG_UEC_ETH1 795 #define CONFIG_SYS_UEC1_UCC_NUM 0 /* UCC1 */ 796 #define CONFIG_SYS_UEC1_RX_CLK QE_CLK12 /* CLK12 for MII */ 797 #define CONFIG_SYS_UEC1_TX_CLK QE_CLK9 /* CLK9 for MII */ 798 #define CONFIG_SYS_UEC1_ETH_TYPE FAST_ETH 799 #define CONFIG_SYS_UEC1_PHY_ADDR 0x0 /* 0x0 for MII */ 800 #define CONFIG_SYS_UEC1_INTERFACE_TYPE PHY_INTERFACE_MODE_RMII 801 #define CONFIG_SYS_UEC1_INTERFACE_SPEED 100 802 #endif /* CONFIG_UEC_ETH1 */ 803 804 #define CONFIG_UEC_ETH5 /* ETH5 */ 805 #define CONFIG_HAS_ETH1 806 807 #ifdef CONFIG_UEC_ETH5 808 #define CONFIG_SYS_UEC5_UCC_NUM 4 /* UCC5 */ 809 #define CONFIG_SYS_UEC5_RX_CLK QE_CLK_NONE 810 #define CONFIG_SYS_UEC5_TX_CLK QE_CLK13 /* CLK 13 for RMII */ 811 #define CONFIG_SYS_UEC5_ETH_TYPE FAST_ETH 812 #define CONFIG_SYS_UEC5_PHY_ADDR 0x3 /* 0x3 for RMII */ 813 #define CONFIG_SYS_UEC5_INTERFACE_TYPE PHY_INTERFACE_MODE_RMII 814 #define CONFIG_SYS_UEC5_INTERFACE_SPEED 100 815 #endif /* CONFIG_UEC_ETH5 */ 816 #endif /* CONFIG_P1025RDB */ 817 818 /* 819 * Environment 820 */ 821 #ifdef CONFIG_SPIFLASH 822 #define CONFIG_ENV_IS_IN_SPI_FLASH 823 #define CONFIG_ENV_SPI_BUS 0 824 #define CONFIG_ENV_SPI_CS 0 825 #define CONFIG_ENV_SPI_MAX_HZ 10000000 826 #define CONFIG_ENV_SPI_MODE 0 827 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */ 828 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ 829 #define CONFIG_ENV_SECT_SIZE 0x10000 830 #elif defined(CONFIG_SDCARD) 831 #define CONFIG_ENV_IS_IN_MMC 832 #define CONFIG_FSL_FIXED_MMC_LOCATION 833 #define CONFIG_ENV_SIZE 0x2000 834 #define CONFIG_SYS_MMC_ENV_DEV 0 835 #elif defined(CONFIG_NAND) 836 #ifdef CONFIG_TPL_BUILD 837 #define CONFIG_ENV_SIZE 0x2000 838 #define CONFIG_ENV_ADDR (CONFIG_SYS_INIT_L2_ADDR + (160 << 10)) 839 #else 840 #define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE 841 #endif 842 #define CONFIG_ENV_IS_IN_NAND 843 #define CONFIG_ENV_OFFSET (1024 * 1024) 844 #define CONFIG_ENV_RANGE (3 * CONFIG_ENV_SIZE) 845 #elif defined(CONFIG_SYS_RAMBOOT) 846 #define CONFIG_ENV_IS_NOWHERE /* Store ENV in memory only */ 847 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) 848 #define CONFIG_ENV_SIZE 0x2000 849 #else 850 #define CONFIG_ENV_IS_IN_FLASH 851 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) 852 #define CONFIG_ENV_SIZE 0x2000 853 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ 854 #endif 855 856 #define CONFIG_LOADS_ECHO /* echo on for serial download */ 857 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ 858 859 /* 860 * Command line configuration. 861 */ 862 #include <config_cmd_default.h> 863 864 #define CONFIG_CMD_IRQ 865 #define CONFIG_CMD_PING 866 #define CONFIG_CMD_I2C 867 #define CONFIG_CMD_MII 868 #define CONFIG_CMD_DATE 869 #define CONFIG_CMD_ELF 870 #define CONFIG_CMD_SETEXPR 871 #define CONFIG_CMD_REGINFO 872 873 /* 874 * USB 875 */ 876 #define CONFIG_HAS_FSL_DR_USB 877 878 #if defined(CONFIG_HAS_FSL_DR_USB) 879 #define CONFIG_USB_EHCI 880 881 #ifdef CONFIG_USB_EHCI 882 #define CONFIG_CMD_USB 883 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 884 #define CONFIG_USB_EHCI_FSL 885 #define CONFIG_USB_STORAGE 886 #endif 887 #endif 888 889 #if defined(CONFIG_P1020RDB_PD) 890 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1 891 #endif 892 893 #define CONFIG_MMC 894 895 #ifdef CONFIG_MMC 896 #define CONFIG_FSL_ESDHC 897 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR 898 #define CONFIG_CMD_MMC 899 #define CONFIG_GENERIC_MMC 900 #endif 901 902 #if defined(CONFIG_MMC) || defined(CONFIG_USB_EHCI) \ 903 || defined(CONFIG_FSL_SATA) 904 #define CONFIG_CMD_EXT2 905 #define CONFIG_CMD_FAT 906 #define CONFIG_DOS_PARTITION 907 #endif 908 909 #undef CONFIG_WATCHDOG /* watchdog disabled */ 910 911 /* 912 * Miscellaneous configurable options 913 */ 914 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 915 #define CONFIG_CMDLINE_EDITING /* Command-line editing */ 916 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 917 #if defined(CONFIG_CMD_KGDB) 918 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 919 #else 920 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 921 #endif 922 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) 923 /* Print Buffer Size */ 924 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 925 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */ 926 927 /* 928 * For booting Linux, the board info and command line data 929 * have to be in the first 64 MB of memory, since this is 930 * the maximum mapped by the Linux kernel during initialization. 931 */ 932 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory for Linux*/ 933 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 934 935 #if defined(CONFIG_CMD_KGDB) 936 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 937 #endif 938 939 /* 940 * Environment Configuration 941 */ 942 #define CONFIG_HOSTNAME unknown 943 #define CONFIG_ROOTPATH "/opt/nfsroot" 944 #define CONFIG_BOOTFILE "uImage" 945 #define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */ 946 947 /* default location for tftp and bootm */ 948 #define CONFIG_LOADADDR 1000000 949 950 #define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */ 951 #define CONFIG_BOOTARGS /* the boot command will set bootargs */ 952 953 #define CONFIG_BAUDRATE 115200 954 955 #ifdef __SW_BOOT_NOR 956 #define __NOR_RST_CMD \ 957 norboot=i2c dev 1; i2c mw 18 1 __SW_BOOT_NOR 1; \ 958 i2c mw 18 3 __SW_BOOT_MASK 1; reset 959 #endif 960 #ifdef __SW_BOOT_SPI 961 #define __SPI_RST_CMD \ 962 spiboot=i2c dev 1; i2c mw 18 1 __SW_BOOT_SPI 1; \ 963 i2c mw 18 3 __SW_BOOT_MASK 1; reset 964 #endif 965 #ifdef __SW_BOOT_SD 966 #define __SD_RST_CMD \ 967 sdboot=i2c dev 1; i2c mw 18 1 __SW_BOOT_SD 1; \ 968 i2c mw 18 3 __SW_BOOT_MASK 1; reset 969 #endif 970 #ifdef __SW_BOOT_NAND 971 #define __NAND_RST_CMD \ 972 nandboot=i2c dev 1; i2c mw 18 1 __SW_BOOT_NAND 1; \ 973 i2c mw 18 3 __SW_BOOT_MASK 1; reset 974 #endif 975 #ifdef __SW_BOOT_PCIE 976 #define __PCIE_RST_CMD \ 977 pciboot=i2c dev 1; i2c mw 18 1 __SW_BOOT_PCIE 1; \ 978 i2c mw 18 3 __SW_BOOT_MASK 1; reset 979 #endif 980 981 #define CONFIG_EXTRA_ENV_SETTINGS \ 982 "netdev=eth0\0" \ 983 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ 984 "loadaddr=1000000\0" \ 985 "bootfile=uImage\0" \ 986 "tftpflash=tftpboot $loadaddr $uboot; " \ 987 "protect off " __stringify(CONFIG_SYS_TEXT_BASE) " +$filesize; " \ 988 "erase " __stringify(CONFIG_SYS_TEXT_BASE) " +$filesize; " \ 989 "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) " $filesize; " \ 990 "protect on " __stringify(CONFIG_SYS_TEXT_BASE) " +$filesize; " \ 991 "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) " $filesize\0" \ 992 "hwconfig=usb1:dr_mode=host,phy_type=ulpi\0" \ 993 "consoledev=ttyS0\0" \ 994 "ramdiskaddr=2000000\0" \ 995 "ramdiskfile=rootfs.ext2.gz.uboot\0" \ 996 "fdtaddr=c00000\0" \ 997 "bdev=sda1\0" \ 998 "jffs2nor=mtdblock3\0" \ 999 "norbootaddr=ef080000\0" \ 1000 "norfdtaddr=ef040000\0" \ 1001 "jffs2nand=mtdblock9\0" \ 1002 "nandbootaddr=100000\0" \ 1003 "nandfdtaddr=80000\0" \ 1004 "ramdisk_size=120000\0" \ 1005 "map_lowernorbank=i2c dev 1; i2c mw 18 1 02 1; i2c mw 18 3 fd 1\0" \ 1006 "map_uppernorbank=i2c dev 1; i2c mw 18 1 00 1; i2c mw 18 3 fd 1\0" \ 1007 __stringify(__NOR_RST_CMD)"\0" \ 1008 __stringify(__SPI_RST_CMD)"\0" \ 1009 __stringify(__SD_RST_CMD)"\0" \ 1010 __stringify(__NAND_RST_CMD)"\0" \ 1011 __stringify(__PCIE_RST_CMD)"\0" 1012 1013 #define CONFIG_NFSBOOTCOMMAND \ 1014 "setenv bootargs root=/dev/nfs rw " \ 1015 "nfsroot=$serverip:$rootpath " \ 1016 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 1017 "console=$consoledev,$baudrate $othbootargs;" \ 1018 "tftp $loadaddr $bootfile;" \ 1019 "tftp $fdtaddr $fdtfile;" \ 1020 "bootm $loadaddr - $fdtaddr" 1021 1022 #define CONFIG_HDBOOT \ 1023 "setenv bootargs root=/dev/$bdev rw rootdelay=30 " \ 1024 "console=$consoledev,$baudrate $othbootargs;" \ 1025 "usb start;" \ 1026 "ext2load usb 0:1 $loadaddr /boot/$bootfile;" \ 1027 "ext2load usb 0:1 $fdtaddr /boot/$fdtfile;" \ 1028 "bootm $loadaddr - $fdtaddr" 1029 1030 #define CONFIG_USB_FAT_BOOT \ 1031 "setenv bootargs root=/dev/ram rw " \ 1032 "console=$consoledev,$baudrate $othbootargs " \ 1033 "ramdisk_size=$ramdisk_size;" \ 1034 "usb start;" \ 1035 "fatload usb 0:2 $loadaddr $bootfile;" \ 1036 "fatload usb 0:2 $fdtaddr $fdtfile;" \ 1037 "fatload usb 0:2 $ramdiskaddr $ramdiskfile;" \ 1038 "bootm $loadaddr $ramdiskaddr $fdtaddr" 1039 1040 #define CONFIG_USB_EXT2_BOOT \ 1041 "setenv bootargs root=/dev/ram rw " \ 1042 "console=$consoledev,$baudrate $othbootargs " \ 1043 "ramdisk_size=$ramdisk_size;" \ 1044 "usb start;" \ 1045 "ext2load usb 0:4 $loadaddr $bootfile;" \ 1046 "ext2load usb 0:4 $fdtaddr $fdtfile;" \ 1047 "ext2load usb 0:4 $ramdiskaddr $ramdiskfile;" \ 1048 "bootm $loadaddr $ramdiskaddr $fdtaddr" 1049 1050 #define CONFIG_NORBOOT \ 1051 "setenv bootargs root=/dev/$jffs2nor rw " \ 1052 "console=$consoledev,$baudrate rootfstype=jffs2 $othbootargs;" \ 1053 "bootm $norbootaddr - $norfdtaddr" 1054 1055 #define CONFIG_RAMBOOTCOMMAND \ 1056 "setenv bootargs root=/dev/ram rw " \ 1057 "console=$consoledev,$baudrate $othbootargs " \ 1058 "ramdisk_size=$ramdisk_size;" \ 1059 "tftp $ramdiskaddr $ramdiskfile;" \ 1060 "tftp $loadaddr $bootfile;" \ 1061 "tftp $fdtaddr $fdtfile;" \ 1062 "bootm $loadaddr $ramdiskaddr $fdtaddr" 1063 1064 #define CONFIG_BOOTCOMMAND CONFIG_HDBOOT 1065 1066 #endif /* __CONFIG_H */ 1067